JP2012253330A - 半導体装置およびその作製方法 - Google Patents
半導体装置およびその作製方法 Download PDFInfo
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- JP2012253330A JP2012253330A JP2012105551A JP2012105551A JP2012253330A JP 2012253330 A JP2012253330 A JP 2012253330A JP 2012105551 A JP2012105551 A JP 2012105551A JP 2012105551 A JP2012105551 A JP 2012105551A JP 2012253330 A JP2012253330 A JP 2012253330A
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
- H01L29/4238—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the surface lay-out
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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Abstract
【解決手段】絶縁層にトレンチを形成し、トレンチの上端コーナー部と接する酸化物半導体膜に不純物を添加し、ソース領域およびドレイン領域を形成する。上記構造にすることで微細化することが可能である。また、トレンチを有することで、ソース電極層とドレイン電極層との距離を狭くしても該トレンチの深さを適宜設定することで、短チャネル効果を抑制することができる。
【選択図】図1
Description
本実施の形態では、開示する発明の一態様に係る半導体装置およびその作製工程の例について、図1乃至図3を用いて説明する。
本実施の形態では、上記実施の形態で示したトランジスタ162の他の作製方法を、図2および図5を用いて説明する。
本実施の形態では、上記実施の形態で示したトランジスタ162の他の作製方法を、図2および図6を用いて説明する。
本実施の形態では、実施の形態1に示すトランジスタ162を使用し、電力が供給されない状況でも記憶内容の保持が可能で、かつ、書き込み回数にも制限が無い半導体装置の一例を、図7を用いて説明する。
本実施の形態においては、実施の形態1に示すトランジスタ162を使用し、電力が供給されない状況でも記憶内容の保持が可能で、かつ、書き込み回数にも制限が無い半導体装置について、実施の形態4に示した構成と異なる構成について、図8および図9を用いて説明を行う。
本実施の形態では、酸化物半導体膜にチャネルが形成されるトランジスタの電界効果移動度について図19を参照して説明する。
本実施の形態では、先の実施の形態で示した半導体装置を携帯電話、スマートフォン、電子書籍などの携帯機器に応用した場合の例を図10乃至図13を用いて説明する。
106 素子分離絶縁層
108 絶縁層
110 ゲート電極層
116 チャネル形成領域
120 不純物領域
124 金属化合物領域
130 絶縁層
130a 第1の領域
130b 第2の領域
131 トレンチ
131a 上端コーナー部
140 レジストマスク
142a ソース電極層
142b ドレイン電極層
144 酸化物半導体膜
144a ソース領域
144b ドレイン領域
144c チャネル形成領域
146 ゲート絶縁層
148 ゲート電極層
152 絶縁層
153 導電層
156 配線
160 トランジスタ
162 トランジスタ
164 容量素子
172 トランジスタ
250 メモリセル
251 メモリセルアレイ
251a メモリセルアレイ
251b メモリセルアレイ
253 周辺回路
254 容量素子
260 配線
301 下地絶縁層
302 埋め込み絶縁層
303a 半導体領域
303b 半導体領域
303c 半導体領域
304 ゲート絶縁層
305 ゲート電極層
306a 側壁絶縁層
306b 側壁絶縁層
307 絶縁層
308a ソース電極層
308b ドレイン電極層
801 トランジスタ
802 トランジスタ
803 トランジスタ
804 トランジスタ
805 トランジスタ
806 トランジスタ
807 Xデコーダー
808 Yデコーダー
811 トランジスタ
812 保持容量
813 Xデコーダー
814 Yデコーダー
901 RF回路
902 アナログベースバンド回路
903 デジタルベースバンド回路
904 バッテリー
905 電源回路
906 アプリケーションプロセッサ
907 CPU
908 DSP
909 インターフェイス
910 フラッシュメモリ
911 ディスプレイコントローラ
912 メモリ回路
913 ディスプレイ
914 表示部
915 ソースドライバ
916 ゲートドライバ
917 音声回路
918 キーボード
919 タッチセンサ
950 メモリ回路
951 メモリコントローラ
952 メモリ
953 メモリ
954 スイッチ
955 スイッチ
956 ディスプレイコントローラ
957 ディスプレイ
1001 バッテリー
1002 電源回路
1003 マイクロプロセッサ
1004 フラッシュメモリ
1005 音声回路
1006 キーボード
1007 メモリ回路
1008 タッチパネル
1009 ディスプレイ
1010 ディスプレイコントローラ
Claims (13)
- 第1の膜厚を有する第1の領域と、第1の膜厚より薄い第2の膜厚を有する第2の領域を有し、かつ、側面と、前記第2の領域上に底面が形成されたトレンチ、が設けられた絶縁層と、
前記トレンチの底面および側面、前記第1の領域の上面に接して設けられた、ソース領域、ドレイン領域およびチャネル形成領域を含む酸化物半導体膜と、
前記ソース領域および前記ドレイン領域と電気的に接続して設けられたソース電極層およびドレイン電極層と、
前記酸化物半導体膜、前記ソース電極層および前記ドレイン電極層上に設けられたゲート絶縁層と、
前記ゲート絶縁層上に設けられ、前記トレンチ内を充填するゲート電極層と、を有し、
前記チャネル形成領域は、前記酸化物半導体膜の表面に、概略垂直なc軸を有する結晶を含み、前記トレンチの側面および底面と接して設けられ、
前記ソース領域および前記ドレイン領域は、前記チャネル形成領域よりも不純物濃度が高く、前記第1の領域の上面と前記トレンチの側面が交わる上端コーナー部および前記第1の領域の上面と接して設けられている半導体装置。 - 前記ソース電極層、前記ドレイン電極層および前記ゲート電極層と重畳しない前記酸化物半導体膜中に前記ソース領域および前記ドレイン領域よりも不純物濃度が高い領域を有する請求項1に記載の半導体装置。
- 前記トレンチは、底面と側面が交わる下端コーナー部に曲面が形成されており、
前記下端コーナー部の曲面は、20nm以上60nm以下の曲率半径を有する、請求項1または請求項2に記載の半導体装置。 - 前記ソース領域および前記ドレイン領域の一部は、前記ゲート電極層と重畳している請求項1乃至請求項3のいずれか一に記載の半導体装置。
- 第1の膜厚を有する第1の領域と、第1の膜厚より薄い第2の膜厚を有する第2の領域を有し、かつ、側面と、前記第2の領域上に底面が形成されたトレンチ、が設けられた絶縁層を形成する工程と、
加熱しながら前記トレンチの底面および側面、前記第1の領域の上面に接して酸化物半導体膜を形成し、少なくとも前記トレンチの側面および底面に接する領域に、前記酸化物半導体膜の表面に、概略垂直なc軸を有する結晶を含む酸化物半導体膜を形成する工程と、
不純物を前記第1の領域の上面の法線方向に対して斜めから添加して、前記第1の領域の上面と前記トレンチの側面が交わる上端コーナー部および前記第1の領域の上面に接してソース領域およびドレイン領域を、前記トレンチの側面および底面に接してチャネル形成領域をそれぞれ形成する工程と、
前記ソース領域および前記ドレイン領域と電気的に接続するソース電極層およびドレイン電極層を形成する工程と、
前記酸化物半導体膜、前記ソース電極層および前記ドレイン電極層上にゲート絶縁層を形成する工程と、
前記ゲート絶縁層上に前記トレンチ内を充填するゲート電極層を形成する工程と、を有し、
前記ソース領域および前記ドレイン領域は、前記チャネル形成領域よりも不純物濃度が高い半導体装置の作製方法。 - 第1の膜厚を有する第1の領域と、第1の膜厚より薄い第2の膜厚を有する第2の領域を有し、かつ、側面と、前記第2の領域上に底面が形成されたトレンチ、が設けられた絶縁層を形成する工程と、
前記トレンチの底面および側面、前記第1の領域の上面に接して非晶質である酸化物半導体膜を形成する工程と、
非晶質である前記酸化物半導体膜を加熱して、少なくとも前記トレンチの側面および底面に接する領域に、前記酸化物半導体膜の表面に、概略垂直なc軸を有する結晶を含む酸化物半導体膜を形成する工程と、
不純物を前記第1の領域の上面の法線方向に対して斜めから添加して、前記第1の領域の上面と前記トレンチの側面が交わる上端コーナー部および前記第1の領域の上面に接してソース領域およびドレイン領域を、前記トレンチの側面および底面に接してチャネル形成領域をそれぞれ形成する工程と、
前記ソース領域および前記ドレイン領域と電気的に接続するソース電極層およびドレイン電極層を形成する工程と、
前記酸化物半導体膜、前記ソース電極層および前記ドレイン電極層上にゲート絶縁層を形成する工程と、
前記ゲート絶縁層上に前記トレンチ内を充填するゲート電極層を形成する工程と、を有し、
前記ソース領域および前記ドレイン領域は、前記チャネル形成領域よりも不純物濃度が高い半導体装置の作製方法。 - 第1の膜厚を有する第1の領域と、第1の膜厚より薄い第2の膜厚を有する第2の領域を有し、かつ、側面と、前記第2の領域上に底面が形成されたトレンチ、が設けられた絶縁層を形成する工程と、
加熱しながら前記トレンチの底面および側面、前記第1の領域の上面に接して酸化物半導体膜を形成し、少なくとも前記トレンチの側面および底面に接する領域は、前記酸化物半導体膜の表面に、概略垂直なc軸を有する結晶を含む酸化物半導体膜を形成する工程と、
ソース電極層およびドレイン電極層を形成する工程と、
前記酸化物半導体膜、前記ソース電極層および前記ドレイン電極層上にゲート絶縁層を形成する工程と、
前記ゲート絶縁層上に前記トレンチと重畳するように前記トレンチ内を充填するゲート電極層を形成する工程と、
前記ゲート電極層の形成後に、前記ゲート電極層を通過するように不純物を添加し、前記第1の領域の上面と前記トレンチの側面が交わる上端コーナー部および前記第1の領域の上面に接してソース領域およびドレイン領域を、前記トレンチの側面および底面に接してチャネル形成領域をそれぞれ形成する工程と、を有し、
前記ソース領域および前記ドレイン領域は、前記チャネル形成領域よりも不純物濃度が高い半導体装置の作製方法。 - 第1の膜厚を有する第1の領域と、第1の膜厚より薄い第2の膜厚を有する第2の領域を有し、かつ、側面と、前記第2の領域上に底面が形成されたトレンチ、が設けられた絶縁層を形成する工程と、
前記トレンチの底面および側面、前記第1の領域の上面に接して非晶質である酸化物半導体膜を形成する工程と、
ソース電極層およびドレイン電極層を形成する工程と、
前記酸化物半導体膜、前記ソース電極層および前記ドレイン電極層上にゲート絶縁層を形成する工程と、
前記ゲート絶縁層上に前記トレンチと重畳するように前記トレンチ内を充填するゲート電極層を形成する工程と、
前記ゲート電極層の形成後に、前記ゲート電極層を通過するように不純物を添加し、前記第1の領域の上面と前記トレンチの側面が交わる上端コーナー部および前記第1の領域の上面に接してソース領域およびドレイン領域を、前記トレンチの側面および底面に接してチャネル形成領域をそれぞれ形成する工程と、
前記非晶質である酸化物半導体膜を形成する工程乃至前記ゲート電極層を形成する工程のいずれか一の工程後に、非晶質である前記酸化物半導体膜を加熱して、少なくとも前記トレンチの側面および底面に接する領域に、前記酸化物半導体膜の表面に、概略垂直なc軸を有する結晶を含む酸化物半導体膜を形成する工程と、を有し、
前記ソース領域および前記ドレイン領域は、前記チャネル形成領域よりも不純物濃度が高い半導体装置の作製方法。 - 第1の膜厚を有する第1の領域と、第1の膜厚より薄い第2の膜厚を有する第2の領域を有し、かつ、側面と、前記第2の領域上に底面が形成されたトレンチ、が設けられた絶縁層を形成する工程と、
加熱しながら前記トレンチの底面および側面、前記第1の領域の上面に接して酸化物半導体膜を形成し、少なくとも前記トレンチの側面および底面に接する領域は、前記酸化物半導体膜の表面に、概略垂直なc軸を有する結晶を含む酸化物半導体膜を形成する工程と、
前記トレンチの側面および底面を覆うレジストマスクを形成する工程と、
前記酸化物半導体膜に対して不純物を添加する工程と、
前記前記第1の領域の上面と前記トレンチの側面が交わる上端コーナー部および前記第1の領域の上面に接してソース領域およびドレイン領域を、前記トレンチの側面および底面に接してチャネル形成領域をそれぞれ形成する工程と、
前記レジストマスクを除去する工程と、
前記ソース領域および前記ドレイン領域と電気的に接続するソース電極層およびドレイン電極層を形成する工程と、
前記酸化物半導体膜、前記ソース電極層および前記ドレイン電極層上にゲート絶縁層を形成する工程と、
前記ゲート絶縁層上に前記トレンチ内を充填するゲート電極層を形成する工程と、を有し、
前記ソース領域および前記ドレイン領域は、前記チャネル形成領域よりも不純物濃度が高い半導体装置の作製方法。 - 第1の膜厚を有する第1の領域と、第1の膜厚より薄い第2の膜厚を有する第2の領域を有し、かつ、側面と、前記第2の領域上に底面が形成されたトレンチ、が設けられた絶縁層を形成する工程と、
前記トレンチの底面および側面、前記第1の領域の上面に接して非晶質である酸化物半導体膜を形成する工程と、
前記酸化物半導体膜上に接して前記トレンチの側面および底面を覆うレジストマスクを形成する工程と、
前記酸化物半導体膜に対して不純物を添加する工程と、
前記第1の領域の上面と前記トレンチの側面が交わる上端コーナー部および前記第1の領域の上面に接してソース領域およびドレイン領域を、前記トレンチの側面および底面に接してチャネル形成領域をそれぞれ形成する工程と、
前記レジストマスクを除去する工程と、
前記ソース領域および前記ドレイン領域と電気的に接続するソース電極層およびドレイン電極層を形成する工程と、
前記酸化物半導体膜、前記ソース電極層および前記ドレイン電極層上にゲート絶縁層を形成する工程と、
前記ゲート絶縁層上に前記トレンチ内を充填するゲート電極層を形成する工程と、
前記非晶質である酸化物半導体膜を形成する工程後または前記レジストマスクを形成する工程後に、非晶質である前記酸化物半導体膜を加熱して、少なくとも前記トレンチの側面および底面に接する領域は、前記酸化物半導体膜の表面に、概略垂直なc軸を有する結晶を含む酸化物半導体膜を形成する工程と、を有し、
前記ソース領域および前記ドレイン領域は、前記チャネル形成領域よりも不純物濃度が高い半導体装置の作製方法。 - 前記不純物の添加方法がプラズマ源改質イオンインプランテーション法またはプラズマベースイオンインプランテーション法である請求項9または請求項10に記載の半導体装置の作製方法。
- 前記ソース電極層、前記ドレイン電極層およびゲート電極層と重畳しない前記酸化物半導体膜中に前記ソース領域および前記ドレイン領域よりも不純物濃度が高い領域を形成する請求項5乃至請求項11のいずれか一に記載の半導体装置の作製方法。
- 前記トレンチは、底面と側面が交わる下端コーナー部に曲面が形成されており、
前記下端コーナー部の曲面は、20nm以上60nm以下の曲率半径を有する、請求項5乃至請求項12のいずれか一に記載の半導体装置の作製方法。
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JP6227079B2 (ja) | 2017-11-08 |
US20140370670A1 (en) | 2014-12-18 |
US9530852B2 (en) | 2016-12-27 |
US8847233B2 (en) | 2014-09-30 |
JP2017017332A (ja) | 2017-01-19 |
JP6013021B2 (ja) | 2016-10-25 |
US20120286270A1 (en) | 2012-11-15 |
US20150318368A1 (en) | 2015-11-05 |
US9087855B2 (en) | 2015-07-21 |
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