JP5022683B2 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
- Publication number
- JP5022683B2 JP5022683B2 JP2006323751A JP2006323751A JP5022683B2 JP 5022683 B2 JP5022683 B2 JP 5022683B2 JP 2006323751 A JP2006323751 A JP 2006323751A JP 2006323751 A JP2006323751 A JP 2006323751A JP 5022683 B2 JP5022683 B2 JP 5022683B2
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- Prior art keywords
- opening
- semi
- insulating substrate
- layer
- hole
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- 239000004065 semiconductor Substances 0.000 title claims description 11
- 238000004519 manufacturing process Methods 0.000 title claims description 8
- 239000000758 substrate Substances 0.000 claims description 48
- 238000005530 etching Methods 0.000 claims description 21
- 238000000034 method Methods 0.000 claims description 8
- 230000007423 decrease Effects 0.000 claims description 5
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 claims description 3
- 238000010438 heat treatment Methods 0.000 claims description 3
- 239000000463 material Substances 0.000 claims description 3
- 230000001678 irradiating effect Effects 0.000 claims description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical group [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims 1
- 229910052782 aluminium Inorganic materials 0.000 claims 1
- 239000002184 metal Substances 0.000 description 6
- 238000007740 vapor deposition Methods 0.000 description 5
- 238000001312 dry etching Methods 0.000 description 4
- 239000004020 conductor Substances 0.000 description 3
- 229910052736 halogen Inorganic materials 0.000 description 3
- 150000002367 halogens Chemical class 0.000 description 3
- 230000000149 penetrating effect Effects 0.000 description 3
- 238000007747 plating Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000009713 electroplating Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 229910003460 diamond Inorganic materials 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- 238000007599 discharging Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 230000009257 reactivity Effects 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
- H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/3086—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Drying Of Semiconductors (AREA)
Description
11a…半絶縁性基板の一方の面
11b…半絶縁性基板の他方の面
11c…貫通穴
11d…貫通穴のテーパ領域
12…電極
13…マスク層
14…レジスト層
15…マスクパターン
16…光源
17…導電層
D1、D2…貫通穴の内径
Claims (3)
- 一方の面に電極が形成された半絶縁性基板の他方の面に、前記半絶縁性基板よりもエッチング速度が小さい材料からなるマスク層を形成する第1工程と、前記マスク層上にレジスト層を形成する第2工程と、光が通る領域を設けたマスクパターンを通して前記レジスト層に光を照射し、前記レジスト層に第1開口を形成する第3工程と、第1開口を形成した前記レジスト層を加熱し、前記レジスト層の第1開口の周辺に第1開口側に向かって厚さが薄くなる第1テーパ領域を形成する第4工程と、この第4工程の後、前記レジスト層の第1開口を利用して前記マスク層をエッチングし、前記半絶縁性基板の他方の面の一部が露出する第2開口を形成すると共に、前記第2開口の周辺に第2開口側に向かって厚さが薄くなる第2テーパ領域を形成する第5工程と、この第5工程の後、前記マスク層上に残った前記レジスト層を除去する第6工程と、この第6工程の後、前記第2開口を利用して前記半絶縁性基板をエッチングし、前記半絶縁性基板の他方の面側に位置する部分の内径がこれよりも一方の面側に位置する部分の内径よりも大きい第3テーパ領域を有する貫通穴を形成する第7工程と、前記貫通穴の内面に導電層を形成する第8工程とからなる半導体装置の製造方法。
- マスク層の材料がアルミニウムである請求項1記載の半導体装置の製造方法。
- 半絶縁性基板がGaN基板またはSiC基板である請求項1記載の半導体装置の製造方法。
Priority Applications (8)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006323751A JP5022683B2 (ja) | 2006-11-30 | 2006-11-30 | 半導体装置の製造方法 |
US12/300,793 US7749901B2 (en) | 2006-11-30 | 2007-11-28 | Method for forming a tapered via of a semiconductor device |
EP07832621.2A EP2088619B1 (en) | 2006-11-30 | 2007-11-28 | Semiconductor device manufacturing method |
PCT/JP2007/072899 WO2008066059A1 (en) | 2006-11-30 | 2007-11-28 | Semiconductor device and semiconductor device manufacturing method |
KR1020117014974A KR101156837B1 (ko) | 2006-11-30 | 2007-11-28 | 반도체 장치 |
KR1020087027432A KR101069956B1 (ko) | 2006-11-30 | 2007-11-28 | 반도체 장치 및 반도체 장치의 제조 방법 |
TW096145409A TWI455202B (zh) | 2006-11-30 | 2007-11-29 | Semiconductor device and method for manufacturing semiconductor device |
US12/813,541 US20100244202A1 (en) | 2006-11-30 | 2010-06-11 | Semiconductor device and fabrication method of the semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006323751A JP5022683B2 (ja) | 2006-11-30 | 2006-11-30 | 半導体装置の製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2008140861A JP2008140861A (ja) | 2008-06-19 |
JP5022683B2 true JP5022683B2 (ja) | 2012-09-12 |
Family
ID=39467849
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2006323751A Active JP5022683B2 (ja) | 2006-11-30 | 2006-11-30 | 半導体装置の製造方法 |
Country Status (6)
Country | Link |
---|---|
US (2) | US7749901B2 (ja) |
EP (1) | EP2088619B1 (ja) |
JP (1) | JP5022683B2 (ja) |
KR (2) | KR101069956B1 (ja) |
TW (1) | TWI455202B (ja) |
WO (1) | WO2008066059A1 (ja) |
Families Citing this family (20)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2011060912A (ja) * | 2009-09-08 | 2011-03-24 | Toshiba Corp | 半導体装置 |
JP5649355B2 (ja) * | 2010-07-28 | 2015-01-07 | 住友電工デバイス・イノベーション株式会社 | 半導体装置及びその製造方法 |
JP5649356B2 (ja) * | 2010-07-28 | 2015-01-07 | 住友電工デバイス・イノベーション株式会社 | 半導体装置及びその製造方法 |
JP5589243B2 (ja) * | 2010-07-30 | 2014-09-17 | 住友電工デバイス・イノベーション株式会社 | 半導体装置の製造方法 |
US8410580B2 (en) | 2011-01-12 | 2013-04-02 | Freescale Semiconductor Inc. | Device having conductive substrate via with catch-pad etch-stop |
WO2012102314A1 (en) | 2011-01-28 | 2012-08-02 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing semiconductor device and semiconductor device |
EP2500938A1 (en) | 2011-03-17 | 2012-09-19 | Nxp B.V. | Package for a semiconductor device, and a method of manufacturing such package |
US8916868B2 (en) | 2011-04-22 | 2014-12-23 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for manufacturing semiconductor device |
US8809854B2 (en) | 2011-04-22 | 2014-08-19 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device |
US8932913B2 (en) * | 2011-04-22 | 2015-01-13 | Semiconductor Energy Laboratory Co., Ltd. | Manufacturing method of semiconductor device |
US8878288B2 (en) | 2011-04-22 | 2014-11-04 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device |
US8847233B2 (en) | 2011-05-12 | 2014-09-30 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device having a trenched insulating layer coated with an oxide semiconductor film |
US8653558B2 (en) | 2011-10-14 | 2014-02-18 | Freescale Semiconductor, Inc. | Semiconductor device and method of making |
KR20140104778A (ko) | 2013-02-21 | 2014-08-29 | 삼성전자주식회사 | 관통전극을 갖는 반도체 소자의 제조방법 |
JP5754452B2 (ja) * | 2013-03-08 | 2015-07-29 | 富士通株式会社 | 半導体装置の製造方法 |
CN105097496B (zh) * | 2014-05-16 | 2018-04-06 | 北京北方华创微电子装备有限公司 | 刻蚀的方法 |
KR102352237B1 (ko) | 2014-10-23 | 2022-01-18 | 삼성전자주식회사 | 팬 아웃 웨이퍼 레벨 패키지의 제조 방법 및 그의 구조 |
EP3333897B1 (en) * | 2016-12-06 | 2023-06-07 | Infineon Technologies AG | Method for manufacturing a iii-n semiconductor device with a through-substrate via |
KR101897653B1 (ko) | 2017-03-06 | 2018-09-12 | 엘비세미콘 주식회사 | 컴플라이언트 범프의 제조방법 |
JP6265307B1 (ja) * | 2017-03-24 | 2018-01-24 | 三菱電機株式会社 | 半導体装置の製造方法および半導体装置 |
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US3986196A (en) * | 1975-06-30 | 1976-10-12 | Varian Associates | Through-substrate source contact for microwave FET |
US3986912A (en) * | 1975-09-04 | 1976-10-19 | International Business Machines Corporation | Process for controlling the wall inclination of a plasma etched via hole |
JPS6150347A (ja) * | 1984-08-20 | 1986-03-12 | Sanyo Electric Co Ltd | コンタクトホ−ルの形成方法 |
JPS63207132A (ja) * | 1987-02-24 | 1988-08-26 | Oki Electric Ind Co Ltd | 半導体装置の製造方法 |
EP0286855A1 (de) * | 1987-04-15 | 1988-10-19 | BBC Brown Boveri AG | Verfahren zum Aetzen von Vertiefungen in ein Siliziumsubstrat |
US4807022A (en) * | 1987-05-01 | 1989-02-21 | Raytheon Company | Simultaneous formation of via hole and tub structures for GaAs monolithic microwave integrated circuits |
US4992764A (en) * | 1989-02-21 | 1991-02-12 | Hittite Microwave Corporation | High-power FET circuit |
JPH07118619B2 (ja) | 1989-04-27 | 1995-12-18 | 三菱電機株式会社 | 抵抗帰還型増幅器 |
JPH05102106A (ja) * | 1991-10-03 | 1993-04-23 | Oki Electric Ind Co Ltd | 半導体装置の製造方法 |
JP2616380B2 (ja) * | 1993-05-14 | 1997-06-04 | 日本電気株式会社 | 半導体装置の製造方法 |
AU4902897A (en) * | 1996-11-08 | 1998-05-29 | W.L. Gore & Associates, Inc. | Method for improving reliability of thin circuit substrates by increasing the T of the substrate |
US6081006A (en) * | 1998-08-13 | 2000-06-27 | Cisco Systems, Inc. | Reduced size field effect transistor |
JP2001028425A (ja) | 1999-07-15 | 2001-01-30 | Mitsubishi Electric Corp | 半導体装置及びその製造方法 |
JP3527496B2 (ja) * | 2000-03-03 | 2004-05-17 | 松下電器産業株式会社 | 半導体装置 |
US6475889B1 (en) * | 2000-04-11 | 2002-11-05 | Cree, Inc. | Method of forming vias in silicon carbide and resulting devices and circuits |
US6559048B1 (en) * | 2001-05-30 | 2003-05-06 | Lsi Logic Corporation | Method of making a sloped sidewall via for integrated circuit structure to suppress via poisoning |
CN100377353C (zh) * | 2004-01-26 | 2008-03-26 | 雅马哈株式会社 | 半导体衬底 |
US7081408B2 (en) * | 2004-10-28 | 2006-07-25 | Intel Corporation | Method of creating a tapered via using a receding mask and resulting structure |
DE102005042072A1 (de) * | 2005-06-01 | 2006-12-14 | Forschungsverbund Berlin E.V. | Verfahren zur Erzeugung von vertikalen elektrischen Kontaktverbindungen in Halbleiterwafern |
US7462891B2 (en) * | 2005-09-27 | 2008-12-09 | Coldwatt, Inc. | Semiconductor device having an interconnect with sloped walls and method of forming the same |
JP2008098581A (ja) * | 2006-10-16 | 2008-04-24 | Matsushita Electric Ind Co Ltd | 半導体装置及びその製造方法 |
-
2006
- 2006-11-30 JP JP2006323751A patent/JP5022683B2/ja active Active
-
2007
- 2007-11-28 WO PCT/JP2007/072899 patent/WO2008066059A1/ja active Application Filing
- 2007-11-28 KR KR1020087027432A patent/KR101069956B1/ko active IP Right Grant
- 2007-11-28 US US12/300,793 patent/US7749901B2/en active Active
- 2007-11-28 EP EP07832621.2A patent/EP2088619B1/en active Active
- 2007-11-28 KR KR1020117014974A patent/KR101156837B1/ko active IP Right Grant
- 2007-11-29 TW TW096145409A patent/TWI455202B/zh active
-
2010
- 2010-06-11 US US12/813,541 patent/US20100244202A1/en not_active Abandoned
Also Published As
Publication number | Publication date |
---|---|
US20090146261A1 (en) | 2009-06-11 |
EP2088619B1 (en) | 2013-05-15 |
EP2088619A4 (en) | 2011-10-26 |
TWI455202B (zh) | 2014-10-01 |
JP2008140861A (ja) | 2008-06-19 |
WO2008066059A1 (en) | 2008-06-05 |
KR20090028506A (ko) | 2009-03-18 |
KR101069956B1 (ko) | 2011-10-04 |
US7749901B2 (en) | 2010-07-06 |
TW200837829A (en) | 2008-09-16 |
KR20110088596A (ko) | 2011-08-03 |
EP2088619A1 (en) | 2009-08-12 |
US20100244202A1 (en) | 2010-09-30 |
KR101156837B1 (ko) | 2012-06-18 |
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