JP2005536877A - Cmosゲートの原子層堆積法 - Google Patents
Cmosゲートの原子層堆積法 Download PDFInfo
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- 238000000231 atomic layer deposition Methods 0.000 title claims abstract description 48
- 229910052751 metal Inorganic materials 0.000 claims abstract description 70
- 239000002184 metal Substances 0.000 claims abstract description 70
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- 238000000034 method Methods 0.000 claims abstract description 32
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- 239000004065 semiconductor Substances 0.000 claims description 13
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 claims description 13
- 239000003870 refractory metal Substances 0.000 claims description 11
- 239000010936 titanium Substances 0.000 claims description 10
- 229910052721 tungsten Inorganic materials 0.000 claims description 10
- 239000010937 tungsten Substances 0.000 claims description 9
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 7
- 229920005591 polysilicon Polymers 0.000 claims description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 6
- 229910052710 silicon Inorganic materials 0.000 claims description 6
- 239000010703 silicon Substances 0.000 claims description 6
- 229910052719 titanium Inorganic materials 0.000 claims description 6
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 5
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 5
- RVSGESPTHDDNTH-UHFFFAOYSA-N alumane;tantalum Chemical compound [AlH3].[Ta] RVSGESPTHDDNTH-UHFFFAOYSA-N 0.000 claims description 5
- UQZIWOQVLUASCR-UHFFFAOYSA-N alumane;titanium Chemical compound [AlH3].[Ti] UQZIWOQVLUASCR-UHFFFAOYSA-N 0.000 claims description 5
- UTSDGYKWHMMTDM-UHFFFAOYSA-N alumane;tungsten Chemical compound [AlH3].[W] UTSDGYKWHMMTDM-UHFFFAOYSA-N 0.000 claims description 5
- 229910052715 tantalum Inorganic materials 0.000 claims description 4
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 claims description 3
- UGACIEPFGXRWCH-UHFFFAOYSA-N [Si].[Ti] Chemical compound [Si].[Ti] UGACIEPFGXRWCH-UHFFFAOYSA-N 0.000 claims description 2
- 230000005540 biological transmission Effects 0.000 claims description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 2
- IVHJCRXBQPGLOV-UHFFFAOYSA-N azanylidynetungsten Chemical compound [W]#N IVHJCRXBQPGLOV-UHFFFAOYSA-N 0.000 claims 3
- 238000004519 manufacturing process Methods 0.000 abstract description 2
- 239000010409 thin film Substances 0.000 description 46
- 238000006243 chemical reaction Methods 0.000 description 26
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 16
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- -1 tungsten nitride Chemical class 0.000 description 9
- 229910021529 ammonia Inorganic materials 0.000 description 8
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- 239000000956 alloy Substances 0.000 description 4
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- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 3
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 3
- 238000005033 Fourier transform infrared spectroscopy Methods 0.000 description 3
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 3
- 229910007991 Si-N Inorganic materials 0.000 description 3
- 229910004298 SiO 2 Inorganic materials 0.000 description 3
- 229910006294 Si—N Inorganic materials 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 229910052799 carbon Inorganic materials 0.000 description 3
- 239000003638 chemical reducing agent Substances 0.000 description 3
- 229910052801 chlorine Inorganic materials 0.000 description 3
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- MTHYQSRWPDMAQO-UHFFFAOYSA-N diethylazanide;tantalum(5+) Chemical compound CCN(CC)[Ta](N(CC)CC)(N(CC)CC)(N(CC)CC)N(CC)CC MTHYQSRWPDMAQO-UHFFFAOYSA-N 0.000 description 2
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- 125000002496 methyl group Chemical group [H]C([H])([H])* 0.000 description 2
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- CMIQNFUKBYANIP-UHFFFAOYSA-N ruthenium tantalum Chemical compound [Ru].[Ta] CMIQNFUKBYANIP-UHFFFAOYSA-N 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
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- MNWRORMXBIWXCI-UHFFFAOYSA-N tetrakis(dimethylamido)titanium Chemical compound CN(C)[Ti](N(C)C)(N(C)C)N(C)C MNWRORMXBIWXCI-UHFFFAOYSA-N 0.000 description 2
- 229910018509 Al—N Inorganic materials 0.000 description 1
- 238000005481 NMR spectroscopy Methods 0.000 description 1
- FAPWRFPIFSIZLT-UHFFFAOYSA-M Sodium chloride Chemical group [Na+].[Cl-] FAPWRFPIFSIZLT-UHFFFAOYSA-M 0.000 description 1
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- 229910052784 alkaline earth metal Inorganic materials 0.000 description 1
- AZDRQVAHHNSJOQ-UHFFFAOYSA-N alumane Chemical group [AlH3] AZDRQVAHHNSJOQ-UHFFFAOYSA-N 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
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- 238000000576 coating method Methods 0.000 description 1
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- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 description 1
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- 125000004122 cyclic group Chemical group 0.000 description 1
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- 239000003989 dielectric material Substances 0.000 description 1
- TUTOKIOKAWTABR-UHFFFAOYSA-N dimethylalumane Chemical compound C[AlH]C TUTOKIOKAWTABR-UHFFFAOYSA-N 0.000 description 1
- 229910001873 dinitrogen Inorganic materials 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000000921 elemental analysis Methods 0.000 description 1
- LNKYFCABELSPAN-UHFFFAOYSA-N ethyl(methyl)azanide;titanium(4+) Chemical compound [Ti+4].CC[N-]C.CC[N-]C.CC[N-]C.CC[N-]C LNKYFCABELSPAN-UHFFFAOYSA-N 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
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- 230000002349 favourable effect Effects 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
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- NFHFRUOZVGFOOS-UHFFFAOYSA-N palladium;triphenylphosphane Chemical compound [Pd].C1=CC=CC=C1P(C=1C=CC=CC=1)C1=CC=CC=C1.C1=CC=CC=C1P(C=1C=CC=CC=1)C1=CC=CC=C1.C1=CC=CC=C1P(C=1C=CC=CC=1)C1=CC=CC=C1.C1=CC=CC=C1P(C=1C=CC=CC=1)C1=CC=CC=C1 NFHFRUOZVGFOOS-UHFFFAOYSA-N 0.000 description 1
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- 229910052701 rubidium Inorganic materials 0.000 description 1
- IGLNJRXAVVLDKE-UHFFFAOYSA-N rubidium atom Chemical compound [Rb] IGLNJRXAVVLDKE-UHFFFAOYSA-N 0.000 description 1
- 229920006395 saturated elastomer Polymers 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 125000005372 silanol group Chemical group 0.000 description 1
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- 238000000391 spectroscopic ellipsometry Methods 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
- 229910052984 zinc sulfide Inorganic materials 0.000 description 1
- DRDVZXDWVBGGMH-UHFFFAOYSA-N zinc;sulfide Chemical compound [S-2].[Zn+2] DRDVZXDWVBGGMH-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28088—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a composite, e.g. TiN
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
- H01L21/28562—Selective deposition
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4966—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2
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- Electrodes Of Semiconductors (AREA)
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Abstract
Description
L Qiang, Y. Yee Chia, et al., “Dual-metal gate technology for deep-submicron CMOS transistors,” VLSI Technology, 2000; Digest of Technical Papers. 2000 Symposium on, 2000, pp. 72-73.
H. Wakabayashi et al., “A dual-metal gate CMOS technology using nitrogen-concentration-controlled TiNx film.” Electron Devices, IEEE Transactions on, Volume: 48 Issue: 10, Oct. 2001, Page (s): 2363-2369.
H. Zhong et al., “Properties of Ru-Ta Alloys as gate electrodes for NMOS and PMOS silicon devices,” Digest of IEEE Int. Electron Devices Meeting, Washington D. C. , 2001, paper 20.05.
V. Misra, H. Zhonget al. , “Electrical properties of Ru-based alloy gate electrodes for dual metal gate Si-CMOS,” IEEE Electron Device Letters, Volume: 23 Issue: 6, Jun 2002 Page (s): 354-356.
H. Zhong et al., “Electrical properties of RuO/sub 2/gate electrodes for dual metal gate Si-CMOS,” IEEE Electron Device Letters, Volume: 21 Issue: 12, Dec. 2000 Page (s): 593-595.
H. Shimada et al., “Low resistivity bcc-Ta/TaN/sub x/metal gate MNSFETshaving plane gate structure featuring fully low-temperature processing below 450 degrees C,” 2001 Symposium on VLSI Technology, 12-14 June 2001, Kyoto, Japan Page: 67-68.
H. Shimada et al., “Tantalum nitride metal gate FD-SOI CMOS FETs using low resistivityself-grown bcc-tantalum, layer,” IEEE Trans. on Electron Devices, vol. 48, no. 8, pp. 1619-26, Aug. 2001.
B. Claflin et al., “Investigation of the growth and chemical stability of composite metal gates on ultra-thin gate dielectrics,” MRS Symposium on Silicon Front-End Technology-Materials Processing and Modelling, 13-15 April, 1998, San Francisco, CA, Page: 171-176.
A. Yagishita et al., “Dynamic threshold voltage damascene metal gate MOSFET (DT-DMG-MOS) with low threshold voltage, high drive current and uniform electrical characteristics,” Digest Technical Papers Int. Electron Devices Meeting, San Francisco, Dec. 2000, pp. 663-6.
B. Claflin et al., “Investigation of the growth and chemical stability of composite metal gates on ultra-thin gate dielectrics,” MRS Symposium on Silicon Front-End Technology-Materials Processing and Modelling, 13-15 April, 1998, San Francisco, CA, Page: 171-176.
M. Moriwaki et al., “Improved metal gate process by simultaneous gate-oxide nitridation during W/WN/sub x/gate formation,” Jpn. J. Appl. Phys., vol. 39. No. 4B, pp. 2177-80, 2000).
Dae-Gyu Park et al., “Robust ternary metal electrodes for dual gate CMOS devices,” Electron Devices Meeting, 2001. IEDM Technical Digest. International, 2001 Page (s): 30.6.1-30.6. 4.
Ofer Snehet al., “Thin film atomic layer deposition equipment for semiconductor processing”, Thin Solid Films, 402 (2002) 248-261.
Shunsuke Morishitaet al., “Atomic-Layer Chemical-Vapor-Deposition of SiO2 by Cyclic Exposure of CHOSi(NCO)3 and H2O2,” Jpn. J. Appl. Phys. Vol. 34 (1955) pp. 5738-5742.
Jin-Seong Park et al., “Plasma-Enhanced Atomic Layer Deposition of Tantalum Nitrides Using Hydrogen Radicals as a Reducing Agent”, Electrochemical and Solid-State LETT. , 4 (4) C17-C19, 2001.
Petra Alen et al., “Atomic Layer Deposition of Ta(AL)N(C) Thin Films Using Trimethylaluminum as a Reducing Agent”, Jour, of the Electrochemical Society, 148 (10), G566-G571 (2001).
J.-S. Min et al., “Atomic layer deposition of TiNfilms by alternate supply on Tetrakis (ethylmethyllamino)-titanium and ammonia,” Jpn. J. Appl. Phys., Vol. 37, Part 1, No. 9A, pp. 4999-5004, 15 Sept. 1998.
Jaehyong Kooet al., “Study on the characteristics of TiAlN thin film deposited by atomic layer deposition method,” J. Vac. Sci. Technol. A, 19 (6), 2831-2834 (2001).
Jae-Sik Min et al., “Metal-organic atomic-layer deposition of titanium-silicon-nitride films”, Appl. Phys, LETT. , Vol. 75, No. 11, 1521-1523 (1999).
J. W. Kraus et al., “Atomic Layer Deposition of Tungsten Nitride Films Using Sequential Surface Reactions”, 147 (3) 1175-1181 (2000).
R. L. Pruurunen et al., “Growth of aluminum nitride on porous silica by atomic layer chemical vapor deposition”, Applied Surface Science, 165,193-202 (2000).
70年代の初期に開発された原子層堆積法はCVDの変形であり、「交互パルス供給式CVD(alternately pulsed-CVD) 」と呼ぶこともできる。この方法は、原料ガスを基板表面に一度に1つずつ導入し、パルス供給の間に反応室を不活性ガスによりパージするか排気するものである。第1の反応ステップでは、原料を基板表面に飽和状態で化学吸着させ、それに続くパージング時に原料を反応室から除去する。第2のステップでは、他の原料ガスを基板上に導入し、所望の薄膜を成長させる反応を起こさせる。その後、反応副生成物及び余剰の原料ガスを反応室からパージする。原料の化学作用が好ましければ、即ち、原料が互いに激しく吸収し合って反応する場合、正しく設計されたフロータイプの反応室では1回のALDサイクルを1秒未満の間実行できる。
Ta−N:t−ブチルイミドトリス(ジエチルアミド)タンタルの還元剤として水素ラジカルを用いた堆積温度260℃における窒化タンタル(Ta−N)薄膜のプラズマ増速原子層堆積(PEALD)が記載されている。PEALDは、電気抵抗率が400μΩcmで空気に露出しても経年効果がない優れたTa−N薄膜を生成する。薄膜密度は、NH3が水素ラジカルに代わって用いられる典型的なALDにより形成されるTa−N薄膜よりも大きい。さらに、堆積されたままの薄膜は非晶質でなく、等軸晶TaNの多結晶構造である。薄膜の密度及び結晶化度は水素プラズマのパルス時間と共に増加する。薄膜はTaが豊富な組成を有し、約15原子パーセントの炭素不純物を含む。Ta−N薄膜のPEALDでは、水素ラジカルは、典型的なTa−NのALDの還元ガスとして用いられるNH3の代わりの還元剤として使用される。薄膜は、Taの原料として(Net2)3Ta=Nbut(t−ブチルイミドトリス(ジエチルアミド)タンタル、TBTDET)を用いるコールドウォール型反応器において堆積温度が260℃、堆積圧力が133PaでSiO2(100nm)/Siのウェーハ上に堆積される。液体原料は70℃に加熱された泡だて器に収容され、35sccmのアルゴンにより運ばれる。1つの堆積サイクルは、TBTDETの金属有機原料への露出、アルゴンによるパージ期間及び水素プラズマへの露出と、それに続くアルゴンによる別のパージ期間より成る。代わりに各反応剤ガスパルス間で15秒のアルゴンパージ期間を設けると、反応剤ガスがそれぞれ隔離される。堆積サイクルに同期して水素プラズマを点火し維持するには、上方の電極と下方の電極との間に矩形の電源を適用する。反応室内で反応剤ガスを均一に分布させるためのシャワーヘッドを100ワットの電力で作動されるRF(13.56MHz)プラズマ源と容量結合したものを、上方電極として用いる。ウェーハがその上に載る下方電極はアースにつなぐ。薄膜の厚さ及びその形態を電界放出走査型電子顕微鏡により分析した。
図4は本発明によるメモリデバイスを示す。このメモリデバイス440は、メモリアレイ442、行及び列デコーダ444、448及びセンス増幅器回路446を有する。メモリアレイ444は、三元金属ゲートが原子層堆積により形成された多数のトランジスタセル400より成り、それらのワードライン480及びビットライン460はそれぞれ行及び列の一般的構成になっている。メモリアレイ442のビットライン460はセンス増幅器回路446に接続され、一方、ワードライン480は行デコーダ444に接続されている。アドレス及び制御信号はアドレス/制御ライン461上でメモリデバイス440に入力され、列デコーダ448、センス増幅器回路446及び行デコーダ444に接続され、とりわけメモリアレイ442への読み出し及び書き込みアクセスに使用される。
Claims (33)
- 第1のソース/ドレイン領域と、
第2のソース/ドレイン領域と、
第1と第2のソース/ドレイン領域間のチャンネル領域と、
ゲート絶縁体によりチャンネル領域から分離されたゲートとより成り、ゲートは原子層堆積により形成された三元金属導体を含み、該三元金属導体は組成が所望のしきい電圧を与えるように調整されているトランジスタ。 - 三元金属導体は窒化タンタルアルミニウム(TaAlN)を含む請求項1のトランジスタ。
- 三元金属導体は窒化チタンアルミニウム(TiAlN)を含む請求項1のトランジスタ。
- 三元金属導体は窒化チタンシリコン(TiSiN)を含む請求項1のトランジスタ。
- 三元金属導体は窒化タングステンアルミニウム(WAlN)を含む請求項1のトランジスタ。
- ゲートはさらに、三元金属導体により形成された導電性ポリシリコン層を含む前記請求項のうち任意の請求項のトランジスタ。
- ゲートはさらに、三元金属導体の上に形成された高融点金属を含む前記請求項のうち任意の請求項のトランジスタ。
- 高融点金属はタングステン(W)を含む請求項7のトランジスタ。
- 高融点金属はタンタル(Ta)を含む請求項7のトランジスタ。
- 高融点金属はチタン(Ti)を含む請求項7のトランジスタ。
- ソース領域に結合されたソースラインと、ドレイン領域に結合された伝送ラインとをさらに備えた前記請求項のうち任意の請求項のトランジスタより成るメモリセル。
- 前記請求項のうち任意の請求項の多数のトランジスタを有するメモリアレイであって、
トランジスタアレイは、
各々が基板上に形成され、多数のトランジスタのうち少なくとも1つを有する多数のセルと、
トランジスタアレイの行に沿って各トランジスタのドレイン領域に結合された多数のビットラインと、
メモリアレイの列に沿って各トランジスタのゲートに結合された多数のワードラインより成るメモリアレイ。 - 多数のワードラインに結合されたワードラインアドレスデコーダと、
多数のビットラインに結合されたビットラインアドレスデコーダと、
多数のビットラインに結合されたセンス増幅器とより成る、請求項12によるメモリアレイを有する半導体デバイス。 - プロセッサと、
プロセッサに結合され、メモリアレイを有するメモリアレイとより成る、請求項12によるメモリアレイを含む電子システム。 - PMOSトランジスタ及びNMOSトランジスタより成るCMOSデバイスであって、
PMOSトランジスタ及びNMOSトランジスタのうちの少なくとも1つが請求項1−10のうち任意の請求項のトランジスタを含み、
NMOS及びPMOSトランジスタがそれぞれソース、ドレイン、ソースとドレイン間のチャンネル領域、及びゲート絶縁体によりチャンネル領域から分離されたゲートを有し、
NMOS及びPMOSトランジスタのゲートはほぼ同じ大きさの低いしきい電圧を実現するように調整された組成及び仕事関数を有するCMOSデバイス。 - ほぼ同じ大きさのしきい電圧は0.4ボルト未満の大きさのしきい電圧を含む請求項15のCMOSデバイス。
- ほぼ同じ大きさのしきい電圧はほぼ0.3ボルトの大きさのしきい電圧を含む請求項15のCMOSデバイス。
- NMOS及びPMOSトランジスタのゲートのうちの1つは二元金属導体を含み、それ以外のゲートは三元金属導体を含む請求項15のCMOSデバイス。
- 二元金属導体は、窒化タンタル(TaN)、窒化チタン(TiN)及び窒化タングステン(WN)の群から選択される二元金属導体を含む請求項18のCMOSデバイス。
- PMOSトランジスタ及びNMOSトランジスタより成るCMOSデバイスであって、
NMOS及びPMOSトランジスタがそれぞれソース、ドレイン、ソースとドレイン間のチャンネル領域、及びゲート絶縁体によりチャンネル領域から分離されたゲートを有し、
PMOSトランジスタ及びNMOSトランジスタのうちの少なくとも1つは請求項1によるトランジスタを含み、NMOS及びPMOSトランジスタのゲートのうちの1つは三元金属導体として窒化タンタルアルミニウム(TaAlN)を含み、NMOS及びPMOSの残りのゲートは窒化タンタル(TaN)より成る二元金属導体を含んで、ほぼ同じ大きさの低いしきい電圧が実現されるCMOSデバイス。 - PMOSトランジスタ及びNMOSトランジスタより成るCMOSデバイスであって、
NMOS及びPMOSトランジスタがそれぞれソース、ドレイン、ソースとドレイン間のチャンネル領域、及びゲート絶縁体によりチャンネル領域から分離されたゲートを有し、
PMOSトランジスタ及びNMOSトランジスタのうちの少なくとも1つは請求項1によるトランジスタを含み、NMOS及びPMOSトランジスタのゲートのうちの1つは三元金属導体として窒化チタンアルミニウム(TiAlN)を含み、NMOS及びPMOSの残りのゲートは窒化チタン(TiN)より成る二元金属導体を含んで、ほぼ同じ大きさの低いしきい電圧が実現されるCMOSデバイス。 - PMOSトランジスタ及びNMOSトランジスタより成るCMOSデバイスであって、
NMOS及びPMOSトランジスタがそれぞれソース、ドレイン、ソースとドレイン間のチャンネル領域、及びゲート絶縁体によりチャンネル領域から分離されたゲートを有し、
PMOSトランジスタ及びNMOSトランジスタのうちの少なくとも1つは請求項1によるトランジスタを含み、NMOS及びPMOSトランジスタのゲートのうちの1つは三元金属導体として窒化タングステンアルミニウム(WAlN)を含み、NMOS及びPMOSの残りのゲートは窒化タングステン(WN)より成る二元金属導体を含んで、ほぼ同じ大きさの低いしきい電圧が実現されるCMOSデバイス。 - トランジスタを形成する方法であって、
第1のソース/ドレイン領域、第2のソース/ドレイン領域及びそれら領域間のチャンネル領域を基板に形成し、
チャンネル領域に対向し第1のゲート絶縁体によりチャンネル領域から分離されたゲートを形成するステップより成り、
ゲートを形成するステップは、所望のしきい値が得られるように調整された組成を与えるように原子層堆積により三元金属導体を形成するステップを含むトランジスタの形成方法。 - 原子層堆積により三元金属導体を形成するステップは、窒化タンタルアルミニウム(TaAlN)層を形成するステップを含む請求項23の方法。
- 原子層堆積により三元金属導体を形成するステップは、窒化チタンアルミニウム(TiAlN)層を形成するステップを含む請求項23の方法。
- 原子層堆積により三元金属導体を形成するステップは、窒化チタンシリコン(TiSiN)層を形成するステップを含む請求項23の方法。
- 原子層堆積により三元金属導体を形成するステップは、窒化タングステンアルミニウム(WAlN)層を形成するステップを含む請求項23の方法。
- ゲートを形成するステップはさらに、三元金属導体の上に高融点金属層を形成するステップを含む請求項23−27のうち任意の請求項の方法。
- ゲートを形成するステップはさらに、三元金属導体の上に導電性ポリシリコン層を形成するステップを含む請求項23−27のうち任意の請求項の方法。
- CMOSデバイスを形成する方法であって、
PMOSトランジスタを形成し、
NMOSトランジスタを形成するステップより成り、
PMOSトランジスタ及びNMOSトランジスタのうち少なくとも1つを形成するステップは、請求項23−29のうち任意の請求項のトランジスタを形成するステップを含み、
NMOS及びPMOSトランジスタを形成するステップは、それぞれのトランジスタのしきい電圧をほぼ同じ大きさに制御するためにそれぞれのトランジスタに調整された仕事関数及び調整された組成を有するゲートを形成するステップを含むCMOSデバイスの形成方法。 - CMOSデバイスを形成する方法であって、
PMOSトランジスタを形成し、
NMOSトランジスタを形成するステップより成り、
PMOSトランジスタ及びNMOSトランジスタのうち少なくとも1つを形成するステップは、請求項24のトランジスタを形成するステップを含み、PMOSトランジスタ及びNMOSトランジスタのうちの残りのトランジスタを形成するステップは、原子層堆積により二元金属導体を有するトランジスタゲートを形成するステップを含み、二元金属導体は窒化タンタル(TaN)層を含むためNMOSトランジスタ及びPMOSトランジスタがほぼ同じ大きさのしきい電圧を有するCMOSトランジスタの形成方法。 - CMOSデバイスを形成する方法であって、
PMOSトランジスタを形成し、
NMOSトランジスタを形成するステップより成り、
PMOSトランジスタ及びNMOSトランジスタのうち少なくとも1つを形成するステップは、請求項24のトランジスタを形成するステップを含み、PMOSトランジスタ及びNMOSトランジスタのうちの残りのトランジスタを形成するステップは、原子層堆積により二元金属導体を有するトランジスタゲートを形成するステップを含み、二元金属導体は窒化チタン(TiN)層を含むためNMOSトランジスタ及びPMOSトランジスタがほぼ同じ大きさのしきい電圧を有するCMOSトランジスタの形成方法。 - CMOSデバイスを形成する方法であって、
PMOSトランジスタを形成し、
NMOSトランジスタを形成するステップより成り、
PMOSトランジスタ及びNMOSトランジスタのうち少なくとも1つを形成するステップは、請求項25のトランジスタを形成するステップを含み、PMOSトランジスタ及びNMOSトランジスタのうちの残りのトランジスタを形成するステップは、原子層堆積により二元金属導体を有するトランジスタゲートを形成するステップを含み、二元金属導体は窒化タングステン(WN)層を含むためNMOSトランジスタ及びPMOSトランジスタがほぼ同じ大きさのしきい電圧を有するCMOSトランジスタの形成方法。
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US7462538B2 (en) * | 2005-11-15 | 2008-12-09 | Infineon Technologies Ag | Methods of manufacturing multiple gate CMOS transistors having different gate dielectric materials |
US7897217B2 (en) * | 2005-11-18 | 2011-03-01 | Tokyo Electron Limited | Method and system for performing plasma enhanced atomic layer deposition |
US7510943B2 (en) * | 2005-12-16 | 2009-03-31 | Infineon Technologies Ag | Semiconductor devices and methods of manufacture thereof |
US20070164323A1 (en) * | 2006-01-18 | 2007-07-19 | Micron Technology, Inc. | CMOS gates with intermetallic compound tunable work functions |
US20070164367A1 (en) * | 2006-01-18 | 2007-07-19 | Micron Technology, Inc. | CMOS gates with solid-solution alloy tunable work functions |
-
2002
- 2002-08-22 US US10/225,605 patent/US20040036129A1/en not_active Abandoned
-
2003
- 2003-08-21 JP JP2004529930A patent/JP2005536877A/ja active Pending
- 2003-08-21 AU AU2003260042A patent/AU2003260042A1/en not_active Abandoned
- 2003-08-21 WO PCT/US2003/026487 patent/WO2004019394A1/en active Application Filing
- 2003-08-21 EP EP03793354A patent/EP1532669A1/en not_active Withdrawn
- 2003-08-21 CN CNB03824408XA patent/CN100359640C/zh not_active Expired - Fee Related
- 2003-08-21 KR KR1020057003033A patent/KR100701542B1/ko not_active IP Right Cessation
-
2004
- 2004-01-09 US US10/754,842 patent/US20040140513A1/en not_active Abandoned
- 2004-08-30 US US10/929,822 patent/US7351628B2/en not_active Expired - Fee Related
-
2005
- 2005-01-20 US US11/038,730 patent/US20050179097A1/en not_active Abandoned
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JP2007533156A (ja) * | 2004-04-19 | 2007-11-15 | フリースケール セミコンダクター インコーポレイテッド | 金属からなるゲート電極を形成するための方法 |
JP4757867B2 (ja) * | 2004-04-19 | 2011-08-24 | フリースケール セミコンダクター インコーポレイテッド | 金属からなるゲート電極を形成するための方法 |
JP2009540123A (ja) * | 2006-06-09 | 2009-11-19 | マイクロン テクノロジー, インク. | 原子層堆積法を用いる材料層の形成方法 |
TWI447784B (zh) * | 2006-06-09 | 2014-08-01 | Micron Technology Inc | 使用原子層沈積方法形成材料層之方法 |
WO2008072573A1 (ja) * | 2006-12-11 | 2008-06-19 | Sony Corporation | 半導体装置の製造方法および半導体装置 |
US8361850B2 (en) | 2006-12-11 | 2013-01-29 | Sony Corporation | Metal oxide semiconductor having epitaxial source drain regions and a method of manufacturing same using dummy gate process |
US11404573B2 (en) | 2006-12-11 | 2022-08-02 | Sony Group Corporation | Metal oxide semiconductor having epitaxial source drain regions and a method of manufacturing same using dummy gate process |
US11901454B2 (en) | 2006-12-11 | 2024-02-13 | Sony Group Corporation | Metal oxide semiconductor having epitaxial source drain regions and a method of manufacturing same using dummy gate process |
JP2011205057A (ja) * | 2010-03-01 | 2011-10-13 | Canon Anelva Corp | 金属窒化膜、該金属窒化膜を用いた半導体装置、および半導体装置の製造方法 |
US8786031B2 (en) | 2010-03-01 | 2014-07-22 | Canon Anelva Corporation | Metal nitride film, semiconductor device using the metal nitride film, and manufacturing method of semiconductor device |
JP2012119432A (ja) * | 2010-11-30 | 2012-06-21 | Hitachi Kokusai Electric Inc | 半導体デバイスの製造方法、基板処理装置および半導体デバイス |
Also Published As
Publication number | Publication date |
---|---|
KR100701542B1 (ko) | 2007-03-30 |
US7351628B2 (en) | 2008-04-01 |
US20040036129A1 (en) | 2004-02-26 |
CN1689143A (zh) | 2005-10-26 |
US20040140513A1 (en) | 2004-07-22 |
US20050179097A1 (en) | 2005-08-18 |
EP1532669A1 (en) | 2005-05-25 |
AU2003260042A1 (en) | 2004-03-11 |
WO2004019394A1 (en) | 2004-03-04 |
CN100359640C (zh) | 2008-01-02 |
KR20050038630A (ko) | 2005-04-27 |
US20050032342A1 (en) | 2005-02-10 |
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