JP2005536070A5 - - Google Patents

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Publication number
JP2005536070A5
JP2005536070A5 JP2004539828A JP2004539828A JP2005536070A5 JP 2005536070 A5 JP2005536070 A5 JP 2005536070A5 JP 2004539828 A JP2004539828 A JP 2004539828A JP 2004539828 A JP2004539828 A JP 2004539828A JP 2005536070 A5 JP2005536070 A5 JP 2005536070A5
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electrical device
less
semiconductor
contact resistance
specific contact
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JP2004539828A
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JP2005536070A (ja
JP4847699B2 (ja
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Priority claimed from US10/217,758 external-priority patent/US7084423B2/en
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JP2004539828A 2002-08-12 2003-08-08 電気接合における半導体のフェルミ準位をピン止め解除する方法および同接合を組み入れたデバイス Expired - Fee Related JP4847699B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US10/217,758 US7084423B2 (en) 2002-08-12 2002-08-12 Method for depinning the Fermi level of a semiconductor at an electrical junction and devices incorporating such junctions
US10/217,758 2002-08-12
PCT/US2003/025054 WO2004030104A1 (en) 2002-08-12 2003-08-08 Method for depinning the fermi level of a semiconductor at an electrical junction and devices incorporating such junctions

Publications (3)

Publication Number Publication Date
JP2005536070A JP2005536070A (ja) 2005-11-24
JP2005536070A5 true JP2005536070A5 (enExample) 2006-10-12
JP4847699B2 JP4847699B2 (ja) 2011-12-28

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JP2004539828A Expired - Fee Related JP4847699B2 (ja) 2002-08-12 2003-08-08 電気接合における半導体のフェルミ準位をピン止め解除する方法および同接合を組み入れたデバイス

Country Status (7)

Country Link
US (18) US7084423B2 (enExample)
EP (3) EP3038158B1 (enExample)
JP (1) JP4847699B2 (enExample)
KR (1) KR101025378B1 (enExample)
CN (1) CN100530682C (enExample)
AU (1) AU2003255256A1 (enExample)
WO (1) WO2004030104A1 (enExample)

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