CN102222687B - 一种锗基nmos器件及其制备方法 - Google Patents
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Abstract
本发明提供一种锗基NMOS器件及其制备方法，属于超大规模集成电路(ULSI)工艺制造技术领域。该锗基NMOS器件的金属源、漏和衬底之间插入两层绝缘介质材料，底层介质采用氧化铪、氮化硅或铪硅氧等高钉扎系数S介质材料；而上层介质采用二氧化钛、氧化镓或锶钛氧等低导带偏移量ΔEC介质材料。本发明可以减弱费米能级钉扎效应，降低电子势垒，进而改善锗基肖特基NMOS器件的性能。与现有的采用单层绝缘介质材料如氧化铝(Al2O3)等相比，本发明能够有效降低肖特基势垒并能保持较低的源漏电阻，在很大程度上改善了器件性能。
Description
技术领域
本发明属于超大规模集成电路(ULSI)工艺制造技术领域，具体涉及一种锗基NMOS器件结构及其制备方法。
背景技术
随着CMOS器件尺寸不断缩小，传统硅基MOS器件遇到了诸多挑战，其中迁移率退化成为影响器件性能进一步提升的关键因素之一。相比硅材料，锗材料具有更高、更加对称的低场载流子迁移率，而且锗沟道器件的制备工艺与传统CMOS工艺兼容，因此，锗基器件成为目前研究热点之一。
锗基肖特基MOS晶体管是一种非常有潜力的器件结构。它与传统MOS晶体管的主要区别就是用金属或者金属锗化物源漏替代了传统的高掺杂源漏，源漏和沟道的接触由PN结变成了金属和半导体接触的肖特基结，这样不仅避免了锗材料中杂质固溶度低和扩散快的问题，而且还能保证低电阻率和获得突变源漏结。但锗基肖特基MOS晶体管也存在亟待解决的问题：大量的界面态使费米能级被钉扎在价带附近，导致电子势垒较大进而限制了锗基肖特基NMOS晶体管性能的提升。这些界面态一般有两个来源：一方面，金属(或金属锗化物)的电子波函数在锗中的不完全衰减导致在锗禁带当中产生大量的金属诱导带隙态(MIGS)；另一方面，锗表面存在大量的悬挂键，这些不饱和的悬挂键也会导致界面态的产生。
发明内容
本发明的目的是提供一种锗基NMOS器件及其制备方法，可减弱费米能级钉扎效应、调节肖特基势垒高度。
本发明提供的锗基NMOS器件是在金属源漏和衬底之间插入了绝缘介质层，可以阻挡金属或金属锗化物在锗禁带中产生金属诱导带隙态(MIGS)，进而达到减弱费米能级钉扎效应、调节肖特基势垒高度的目的。为了有效抑制费米能级钉扎效应，要求绝缘介质层的钉扎系数高以及导带偏移量小。但能同时满足这两个参数要求的介质材料很少，因此本发明提出采用双层绝缘介质的结构来达到此要求：底层材料采用高钉扎系数(S＞0.55)的绝缘介质，如氮化硅(Si3N4)、氧化铪(HfO2)、铪硅氧(HfSiO4)等；上层材料采用低导带偏移量(ΔEC＜1.0eV)的绝缘介质，如二氧化钛(TiO2)、氧化镓(Ga2O3)、锶钛氧(SrTiO3)等。通过在源漏区和衬底间淀积两层绝缘介质薄膜，可以降低源漏的电子势垒，改善锗基肖特基NMOS晶体管的性能。
下面简述此发明的锗基肖特基NMOS晶体管的一种制备方法，步骤如下：
1-1)在锗基衬底上制作MOS结构；
1-2)淀积源漏区域的两层绝缘介质材料，具体是，在衬底上淀积底层绝缘介质材料，该绝缘介质材料的高钉扎系数S＞0.55，在底层绝缘介质材料上淀积一层上层绝缘介质材料，该上层绝缘介质材料的低导带偏移量ΔEC＜1.0eV；
1-3)溅射低功函数金属薄膜，刻蚀形成金属源漏；
1-4)形成接触孔、金属连线。
步骤1-1)具体包括：
2-1)在衬底上制备隔离区；
2-2)淀积栅介质层以及栅；
2-3)形成栅结构；
2-4)形成侧墙结构。
所述步骤1-1)的锗基衬底包括体锗衬底、锗覆绝缘衬底(GOI)或外延锗衬底等。
所述步骤1-2)的底层介质采用氮化硅(Si3N4)、氧化铪(HfO2)、铪硅氧(HfSiO4)等高钉扎系数S介质材料；而上层介质采用二氧化钛(TiO2)、氧化镓(Ga2O3)、锶钛氧(SrTiO3)等低导带偏移量ΔEC介质材料。
所述步骤1-3)的金属薄膜为铝膜或其他低功函数金属膜。
与现有技术相比，本发明的有益效果是：
通过在金属源漏和衬底之间插入两层绝缘介质薄层，能有效调节源/漏与沟道接触的肖特基势垒，提升器件的开关电流比，降低亚阈值斜率。一方面，由于底层介质材料有较大的钉扎系数S，能较好地抑制费米能级钉扎效应，使肖特基势垒高度在一定程度上随金属的功函数变化而变化；另一方面，由于上层介质材料的导带偏移量ΔEC较小，能够进一步阻挡金属中的电子波函数在半导体禁带中引入的MIGS界面态，同时又保证了较小遂穿电阻。
为了有效抑制费米能级钉扎效应，一般要求下层绝缘介质层钉扎系数S＞0.55如氮化硅(Si3N4)、氧化铪(HfO2)、铪硅氧(HfSiO4)等高钉扎系数S介质材料；而要求上层材料的导带偏移量ΔEC＜1.0eV如二氧化钛(TiO2)、氧化镓(Ga2O3)、锶钛氧(SrTiO3)等低导带偏移量ΔEC介质材料。此方法可以减弱费米能级钉扎效应，降低电子势垒，进而改善锗基肖特基NMOS器件的性能。与现有的采用单层绝缘介质材料如氧化铝(Al2O3)等相比，本发明能够有效降低肖特基势垒并能保持较低的源漏电阻，可以显著提升器件性能。
附图说明
图1(a)-图1(j)为本发明提出的制备锗基肖特基晶体管的流程图。
其中，1-锗衬底；2-P阱区域；3-隔离区；4-栅极介质层；5-金属栅；6-侧墙；7-底层绝缘介质；8-上层绝缘介质；9-金属源、漏；10-金属连线层。
具体实施方式
下面结合附图和具体实施方式对本发明作进一步详细描述：
图1为本发明一优选实施例制作锗基肖特基晶体管的方法流程图。本发明制作锗基肖特基晶体管的方法包括如下步骤：
步骤1：提供一块锗基衬底。如图1(a)所示，一块N型半导体锗衬底1，其中衬底1可采用体锗、锗覆绝缘(GOI)或外延锗衬底等。
步骤2：制作P阱区域。在锗衬底上淀积氧化硅和氮化硅层，首先通过光刻定义P阱区域并反应离子刻蚀掉P阱区域的氮化硅，然后离子注入P型杂质如硼等，再退火驱入制作P阱2，最后去掉注入掩蔽层，完成后如图1(b)所示。
步骤3：实现沟槽隔离。如图1(c)中隔离区3，首先在锗片上淀积氧化硅和氮化硅层，然后通过光刻定义并利用反应离子刻蚀技术刻蚀氮化硅、氧化硅以及锗形成沟槽，再利用化学气相淀积(CVD)方法淀积氧化硅回填隔离槽，最后采用化学机械抛光技术(CMP)将表面磨平，实现器件间的隔离。器件隔离不局限于浅槽隔离(STI)，也可以采用场氧隔离等技术。
步骤4：在所述有源区上形成栅极介质层。栅介质层可以采用高K介质、二氧化锗、氮氧化锗等材料。在淀积栅介质之前，一般需要用PH3、NH3以及F等离子体等进行表面钝化处理，或淀积一层界面层如硅(Si)、氮化铝(AlN)、氧化钇(Y2O3)等。本优选实施例先在锗衬底上制作一薄层氧化钇(Y2O3)作为界面层，然后采用原子层淀积(ALD)方法得到氧化铪(HfO2)栅介质层4，如图1(d)所示。
步骤5：在所述栅极介质层上形成栅极。栅可采用多晶硅栅、金属栅、FUSI栅或全锗化物栅等，本实施例采用淀积氮化钛(TiN)制备金属栅，然后光刻定义并刻蚀形成栅结构，如图1(e)所示。
步骤6：在栅极两侧制备侧墙。可以通过淀积SiO2或Si3N4并刻蚀的方式制备侧墙，也可依次淀积Si3N4和SiO2形成双侧墙结构。如图1(f)所示，本实施例采用淀积SiO2加干法刻蚀的方法，在栅的两侧形成侧墙结构6。
步骤7：淀积源漏区域的底层绝缘介质。要求此层介质材料的费米能级钉扎系数S＞0.55，如采用氮化硅(Si3N4)、氧化铪(HfO2)、铪硅氧(HfSiO4)等，本优选实施例采用氮化硅(Si3N4)。此层材料可以通过ALD淀积的方式得到，其厚度约为0.5～2nm，如图1(g)所示。
步骤8：淀积源漏区域的上层绝缘介质。要求此层介质材料的导带偏移量ΔEC＜1.0eV，如二氧化钛(TiO2)、氧化镓(Ga2O3)、锶钛氧(SrTiO3)等，本实施优选例采用二氧化钛(TiO2)。此层材料同样可以通过ALD淀积的方式得到，其厚度范围在0.5～4nm之间，如图1(h)所示。
步骤9：制备金属源漏。可以采用物理气相淀积方式如蒸镀或溅射，在半导体衬底上淀积一层低功函数金属薄膜如铝(Al)、钛(Ti)、钇(Y)等。本优选实施例为铝，其厚度范围在100nm～1μm，通过光刻定义并刻蚀得到金属源漏，如图1(i)所示。
步骤10：形成接触孔、金属连线。首先用CVD方式淀积氧化层，光刻定义出开孔位置并刻蚀二氧化硅，形成接触孔；然后溅射金属层如Al、Al-Ti等，再光刻定义出连线图形并刻蚀形成金属连线图形，最后进行金属化处理，获得金属连线层10，如图1(j)所示。
本发明提出了一种锗基NMOS器件结构及其制备方法。此方法不但可以降低锗基肖特基NMOS源漏处电子的势垒高度，提升锗基肖特基晶体管的电流开关比，改善锗基肖特基NMOS晶体管的性能，而且制作工艺与硅CMOS技术完全兼容，保持了工艺简单的优势。相对于现有技术，所述半导体器件结构及制备方法能简单有效地提升锗基肖特基NMOS晶体管的性能。
以上通过优选实施例详细描述了本发明所提出的一种锗基肖特基晶体管的制备方法，本领域的技术人员应当理解，以上所述仅为本发明的优选实施例，在不脱离本发明实质的范围内，可以对本发明的器件结构做一定的变形或修改，例如源漏结构也可采用提升、凹陷源漏结构，或其他新结构如双栅、FinFET、Ω栅、三栅和围栅等；其制备方法也不限于实施例中所公开的内容，凡依本发明权利要求所做的均等变化与修饰，皆应属本发明的涵盖范围。
Claims (9)
1.一种锗基NMOS器件，其特征在于，在金属源、漏和衬底之间插入两层绝缘介质材料，具体是，在衬底上淀积底层绝缘介质材料，该绝缘介质材料的高钉扎系数S>0.55，在底层绝缘介质材料上淀积一层上层绝缘介质材料，该上层绝缘介质材料的低导带偏移量ΔEc<1.0eV，在上层绝缘介质材料上淀积金属源、漏。
2.如权利要求1所述的锗基NMOS器件，其特征在于，底层绝缘介质材料选用氮化硅、氧化铪或铪硅氧。
3.如权利要求1所述的锗基NMOS器件，其特征在于，上层绝缘介质材料选用二氧化钛、氧化镓或锶钛氧。
4.如权利要求1所述的锗基NMOS器件，其特征在于，底层绝缘介质材料层的厚度为0.5~2nm。
5.如权利要求1所述的锗基NMOS器件，其特征在于，上层绝缘介质材料层的厚度为0.5~4nm。
6.一种锗基肖特基NMOS晶体管的制备方法，步骤如下：
1—1）在锗基衬底上制作MOS结构；
1—2）淀积源漏区域的两层绝缘介质材料，具体是，在衬底上淀积底层绝缘介质材料，该绝缘介质材料的高钉扎系数S>0.55，在底层绝缘介质材料上淀积一层上层绝缘介质材料，该上层绝缘介质材料的低导带偏移量ΔEc<1.0eV；
1—3）溅射金属薄膜，刻蚀形成金属源漏，所述金属薄膜为铝膜、钛膜或钇膜；
1-4）形成接触孔、金属连线。
7.如权利要求6所述的方法，其特征在于，步骤1—1)具体包括：
2—1)在衬底上制备隔离区；
2—2)淀积栅介质层以及栅；
2—3)形成栅结构；
2—4)形成侧墙结构。
8.如权利要求6所述的方法，其特征在于，所述步骤1—1）的锗基衬底包括体锗衬底、锗覆绝缘衬底(GOI)或外延锗衬底。
9.如权利要求6所述的方法，其特征在于，所述步骤1—2）的底层绝缘介质采用氮化硅、氧化铪或铪硅氧；而上层绝缘介质采用二氧化钛、氧化镓或锶钛氧。
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| CN102769016B (zh) * | 2012-08-14 | 2015-01-14 | 北京大学 | 一种抗辐射的cmos器件及其制备方法 |
| CN104051511B (zh) * | 2013-03-14 | 2017-03-01 | 台湾积体电路制造股份有限公司 | 半导体器件及其制造方法 |
| CN104051530B (zh) * | 2013-03-14 | 2016-12-28 | 台湾积体电路制造股份有限公司 | 金属氧化物半导体场效应晶体管 |
| US9240480B2 (en) | 2013-03-14 | 2016-01-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Metal-oxide-semiconductor field-effect transistor with metal-insulator semiconductor contact structure to reduce Schottky barrier |
| CN103151254A (zh) * | 2013-03-18 | 2013-06-12 | 北京大学 | 一种锗基肖特基结的制备方法 |
| US9722026B2 (en) * | 2013-08-30 | 2017-08-01 | Japan Science And Technology Agency | Semiconductor structure in which film including germanium oxide is provided on germanium layer, and method for manufacturing semiconductor structure |
| CN103474340A (zh) * | 2013-09-28 | 2013-12-25 | 复旦大学 | 一种利用双层绝缘层释放费米能级钉扎的方法 |
| US9716176B2 (en) | 2013-11-26 | 2017-07-25 | Samsung Electronics Co., Ltd. | FinFET semiconductor devices including recessed source-drain regions on a bottom semiconductor layer and methods of fabricating the same |
| FR3033447B1 (fr) * | 2015-03-03 | 2017-03-24 | Commissariat Energie Atomique | Transistor a connexions mis et procede de fabrication |
| CN109390394B (zh) * | 2017-08-03 | 2022-08-02 | 联华电子股份有限公司 | 穿隧场效晶体管及其制作方法 |
| CN110634868B (zh) * | 2019-09-16 | 2021-09-14 | 中国科学院微电子研究所 | 一种Ge基CMOS晶体管制备方法 |
| CN111463133B (zh) * | 2020-04-17 | 2023-01-17 | 中国科学院微电子研究所 | Ge基NMOS晶体管及其制作方法 |
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