CN102769016B - 一种抗辐射的cmos器件及其制备方法 - Google Patents

一种抗辐射的cmos器件及其制备方法 Download PDF

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CN102769016B
CN102769016B CN201210289276.7A CN201210289276A CN102769016B CN 102769016 B CN102769016 B CN 102769016B CN 201210289276 A CN201210289276 A CN 201210289276A CN 102769016 B CN102769016 B CN 102769016B
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silicon dioxide
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CN102769016A (zh
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黄如
谭斐
安霞
武唯康
黄良喜
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Peking University
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Abstract

本发明公开了一种抗辐射的CMOS器件及其制备方法，属于CMOS集成电路技术领域。该CMOS器件包括衬底、源区、漏区以及位于衬底上的垂直沟道，在垂直沟道内增加一介质保护区一，该介质保护区一位于垂直沟道中央，将垂直沟道分为两部分，所述介质保护区一的高度等于垂直沟道长度，以有源硅台中轴线为中心，介质保护区一的边缘距离沟道外侧为20～100nm；同时在衬底上的源区或漏区的下方设有介质保护区二，该介质保护区二的长度与源区或漏区的长度相等，所述介质保护区二的高度为10～50nm。本发明由于增加介质保护区，可有效隔断器件源区和漏区收集电荷的路径，改善了器件的单粒子特性。

Description

一种抗辐射的CMOS器件及其制备方法
技术领域
本发明属于CMOS集成电路技术领域，具体涉及一种抗辐射的CMOS器件及其制备方法。
背景技术
信息技术的高速发展和广泛应用改变了传统的生产、经营、管理和生活方式，对人类社会的各方面都带来了深刻的影响。随着科学技术的发展，特别是空间技术、核动力及核武器的发展，核辐射环境与电子技术的关系越来越密切。为了满足航天技术的发展对集成电路抗辐照性能的要求，卫星和宇宙飞船的某些关键核心集成电路需要使用抗辐照加固器件。因此航天事业的发展和宇宙探索的进步，促使研究者们深入研究空间自然辐射环境对集成电路性能的影响，并寻找可行的加固方法。
目前关于CMOS集成电路辐照效应的研究，主要集中在总剂量效应、单粒子效应的研究上。目前，主流的CMOS集成电路是由传统体硅器件构成。在传统体硅器件中，随着栅氧化层的进一步减薄，辐照源在栅氧化层中产生的电荷对器件性能的影响可以忽略不计，但是STI区陷入的电荷会引起寄生晶体管的打开，影响器件的正常工作。另外由于硅衬底中电荷收集区较大，离子入射传统体硅器件的敏感节点时会引发比较严重的单粒子效应，造成器件逻辑状态的非正常改变或器件损坏。另外，随着器件尺寸的不断缩小，传统体硅器件间的间距不断变小，一个高能离子的入射会引起多个平面体硅器件能同时收集电荷，即出现电荷共享效应，电荷共享效应会造成集成电路多个节点同时发生翻转，增大翻转横截面，降低发生翻转所需要的能量阈值。此外，电荷共享效应会造成如保护环等器件级和电路级的抗辐射加固技术的失效。
为了改善传统体硅器件的抗辐射性能，一些新的器件结构逐渐被提出和发展。但是这些新型器件结构往往只能完成单一的抗辐射指标，不能同时兼顾满足即抗总剂量辐射又抗单粒子辐射的要求，同时也没有考虑小尺寸引起的电荷共享效应。因此，研究即抗总剂量辐射又抗单粒子辐射同时抑制电荷共享效应的新弄抗辐射器件结构就显得十分有价值。
发明内容
本发明的目的在于克服现有技术中存在的问题，提出一种新型垂直沟道CMOS器件，使之在辐射环境中能够即抗单粒子辐射又能抗总剂量辐射，同时还要以抑制器件间距缩小引起的电荷共享效应。
本发明的CMOS器件包括衬底、源区、漏区以及位于衬底上的垂直沟道，在垂直沟道的上方设有源区，所述漏区设置在衬底上位于垂直沟道的两侧；或者在垂直沟道的上方设有漏区，所述源区设置在衬底上位于垂直沟道的两侧，在垂直沟道的两侧设有栅介质和栅侧墙，其特征在于，在垂直沟道内增加一介质保护区一，该介质保护区一位于垂直沟道中央，将垂直沟道分为两部分，所述介质保护区一的高度等于垂直沟道长度，以有源硅台中轴线为中心，介质保护区一的边缘距离沟道外侧为20～100nm；同时在衬底上的源区或漏区的下方设有介质保护区二，该介质保护区二的长度与源区或漏区的长度相等，所述介质保护区二的高度为10～50nm。
对于NMOS器件，介质保护区使用的材料为易陷入电子的材料，如氮化硅等。对于PMOS器件，介质保护区使用的材料为易陷入空穴的材料，如二氧化硅等。
本发明制备基于体硅衬底的新型垂直沟道CMOS器件的方法包括以下步骤：
1)准备半导体衬底；
2)在衬底热氧化一薄层二氧化硅，再淀积一层氮化硅和一层二氧化硅。光刻，刻蚀掉二氧化硅和氮化硅，再腐蚀二氧化硅，刻蚀后使第一层的二氧化硅与氮化硅存在微小的台阶；刻蚀半导体衬底，形成半导体台阶；
3)再次热氧化一薄层二氧化硅，淀积一层氮化硅和一层二氧化硅，刻蚀后，局部场区氧化形成器件隔离区；
4)淀积二氧化硅作为缓冲层，多次多能量进行离子注入，使沟道中离子浓度分布均匀；
5)淀积氮化硅层和二氧化硅层后，以氮化硅和二氧化硅为硬掩膜，第二次刻蚀有源区半导体台阶；
6)淀积介质保护区材料，对于NMOS器件，介质保护区使用的材料为易陷入电子的材料，如氮化硅等。对于PMOS器件，介质保护区使用的材料为易陷入空穴的材料，如二氧化硅等平坦化后刻蚀，形成介质保护区；
7)清洗，淀积一层多晶硅，平坦化；
8)第三次刻蚀有源区半导体平台，离子注入形成器件的源漏区；
9)热氧化一层二氧化硅，淀积一层多晶硅，离子注入光刻栅线条，刻蚀后形成多晶硅栅电极和栅侧墙。
本发明的优越性如下：
1)在辐射环境中，如果高能离子入射顶部的源区（或漏区）或底部的漏区（或源区），半导体平台中存在介质保护区有效隔断了器件源区和漏区收集电荷的路径，因此改善了器件的单粒子特性。
2)由于器件的沟道和器件隔离氧化层隔离，即使隔离氧化层陷入足够的电荷，但仍不能在垂直沟道中产生寄生的晶体管，因此改善了器件的总剂量特性。
3)器件的源区和漏区下方存在的绝缘层可以有效阻挡高能离子电离产生电子和空穴的扩散。另外，如果器件顶部为漏区，底部用作源区时，器件正常工作时，高能带电粒子穿过漏区（器件正常工作时的敏感节点）产生的电子和空穴如果被临近器件的漏区收集，需要经过一个STI区和两个源区的距离，在扩散过程中电子和空穴大量复合，因此改善了单粒子作用下的电荷共享效应。
附图说明
图1为本发明提出的CMOS器件的剖面图；
图2（a）至图2（q）为本发明CMOS器件的制备方法的流程示意图。
具体实施方式
下面结合附图以NMOS为例详细说明本发明的实施方式，其中介质保护区材料采用氮化硅。
1)备片：准备P型（100）硅衬底1；
2)刻蚀有源区硅台：先在衬底热氧化一薄层二氧化硅2a，再低压化学气相淀积（LPCVD）一层氮化硅3a，然后LPCVD一层二氧化硅4a，如图2（a）；光刻，反应离子刻蚀（RIE）二氧化硅4a，RIE刻蚀氮化硅3a，氢氟酸腐蚀二氧化硅2a，使刻蚀后的二氧化硅4a与氮化硅3a间存在微小的台阶；电感耦合等离子体（ICP）刻蚀硅衬底1，形成有源区硅台，如图2（b）；
3)形成器件隔离区：再次热氧化一薄层二氧化硅2b，再LPCVD一层氮化硅3b，然后LPCVD一层二氧化硅4b，如图2（c）；RIE二氧化硅4b，RIE场区的氮化硅3b，如图2（d）；腐蚀淀积的二氧化硅4a，4b，2b，有源区硅台的台面和侧壁都完全被氮化硅保护，如图2（e）所示；局部场区氧化形成隔离区5，如图2（f）；腐蚀掉氮化硅3a，3b，二氧化硅2a，2b，如图2（g）；
4)沟道杂质注入：LPCVD二氧化硅6作为缓冲层，注入p型杂质离子，如图2（h）；
5)有源区硅台第二次刻蚀：LPCVD氮化硅8，光刻出硅台图形，RIE刻蚀二氧化硅6和氮化硅8，如图2（i）；以氮化硅8和二氧化硅6为硬掩膜，ICP刻蚀硅1和7，如图2（j）；
6)形成阻挡层：LPCVD氮化硅9，化学机械抛光（CMP），如图（k）；光刻出底部源（或漏）区图形，RIE刻蚀氮化硅9，如图2（l）；
7)形成源漏多晶硅：清洗，LPCVD一层多晶硅10，化学机械抛光（CMP），如图2（m）；
8)源漏区形成：有源区硅台第三次刻蚀，LPCVD一层二氧化硅11，LPCVD一层氮化硅12，光刻出硅台图形，RIE刻蚀二氧化硅11和氮化硅12，以二氧化硅11和氮化硅12为阻挡层，ICP刻蚀多晶硅10和氮化硅9，如图2（n）；注入n型杂质离子;
9)栅氧及栅侧墙的形成：热氧化一层二氧化硅13，LPCVD一层多晶硅14，如图2（o）；光刻栅线条，刻蚀多晶硅14，二氧化硅13，形成多晶硅栅电极14和栅侧墙13，如图2（p）；平坦化，去除硅台顶层源漏区上方的二氧化硅11，氮化硅12，二氧化硅13，如图2（q）。
最后需要注意的是，公布实施方式的目的在于帮助进一步理解本发明，但是本领域的技术人员可以理解：在不脱离本发明及所附的权利要求的精神和范围内，各种替换和修改都是可能的。因此，本发明不应局限于实施例所公开的内容，本发明要求保护的范围以权利要求书界定的范围为准。

Claims (2)

1.一种CMOS器件，包括衬底、源区、漏区以及位于衬底上的垂直沟道，在垂直沟道的上方设有源区，所述漏区设置在衬底上位于垂直沟道的两侧；或者在垂直沟道的上方设有漏区，所述源区设置在衬底上位于垂直沟道的两侧；在垂直沟道的两侧设有栅介质和栅侧墙，其特征在于，在垂直沟道内增加一介质保护区一，该介质保护区一位于垂直沟道中央，将垂直沟道分为两部分，所述介质保护区一的高度等于垂直沟道长度，以有源硅台中轴线为中心，介质保护区一的边缘距离沟道外侧为20～100nm；同时在衬底上的源区或漏区的下方设有介质保护区二，该介质保护区二的长度与源区或漏区的长度相等，所述介质保护区二的厚度为10～50nm，对于NMOS器件，介质保护区使用的材料为易陷入电子的材料；对于PMOS器件，介质保护区使用的材料为易陷入空穴的材料。
2.如权利要求1所述的CMOS器件的制备方法，包括以下步骤：
1)准备半导体衬底；
2)在衬底热氧化形成第一二氧化硅层，再淀积第一氮化硅层和第二二氧化硅层；光刻、刻蚀掉第二二氧化硅层和第一氮化硅层，再腐蚀第一二氧化硅层，刻蚀后使第一二氧化硅层与第一氮化硅层存在微小的台阶；刻蚀半导体衬底，形成有源区半导体台阶；
3)再次热氧化形成第三二氧化硅层，淀积形成第二氮化硅层和第四二氧化硅层，刻蚀、局部场区氧化，形成器件隔离区；
4)淀积第五二氧化硅层作为缓冲层，进行离子注入，使沟道中离子浓度分布均匀；
5)淀积第三氮化硅层和第六二氧化硅层后，以第三氮化硅层和第六二氧化硅层为硬掩膜，第二次刻蚀有源区半导体台阶；
6)淀积介质保护区材料并刻蚀；
7)淀积第一多晶硅层，平坦化；
8)第三次刻蚀有源区半导体台阶，离子注入，形成器件的源漏区；
9)热氧化第七二氧化硅层，淀积第二多晶硅层，离子注入，光刻栅线条，刻蚀后形成多晶硅栅电极和栅侧墙。
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