CN103681343B - 一种半导体结构的制造方法 - Google Patents

一种半导体结构的制造方法 Download PDF

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CN103681343B
CN103681343B CN201210362926.6A CN201210362926A CN103681343B CN 103681343 B CN103681343 B CN 103681343B CN 201210362926 A CN201210362926 A CN 201210362926A CN 103681343 B CN103681343 B CN 103681343B
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shallow trench
heavily doped
active area
doped layer
semiconductor device
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CN103681343A (zh
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尹海洲
朱慧珑
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Institute of Microelectronics of CAS
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Abstract

本发明提供了一种半导体结构的制造方法，该方法包括以下步骤：a）提供SOI衬底，在所述SOI衬底上形成浅沟槽，所述浅沟槽限定的区域对应有源区；b）在浅沟槽靠近所述有源区的侧壁上形成重掺杂层；c）填充浅沟槽形成浅沟槽隔离结构；d）在所述有源区内形成半导体器件。本发明通过在SOI的源极和体区形成pn结，为体区积累的电荷提供泄放通道，减小浮体效应的影响，提高器件的可靠性。

Description

一种半导体结构的制造方法
技术领域
本发明涉及半导体制造领域，尤其涉及一种半导体结构的制造方法。
背景技术
为了提高集成电路芯片的性能和集成度，器件特征尺寸按照摩尔定律不断缩小，目前已经进入纳米尺度。随着器件体积的缩小，功耗与漏电流成为最关注的问题。采用绝缘体上硅SOI（SilicononInsulator）制备的CMOS器件具有高速、低功耗、高集成度、抗辐照和无自锁效应等许多优点，已成为深亚微米及纳米级MOS器件的优选结构。
根据体区是否耗尽，SOI器件分为部分耗尽和全耗尽两种类型。一般来说，全耗尽SOI器件的顶层硅膜比较薄，而且阈值电压不容易控制。因此，目前部分耗尽SOI器件依然是普遍采用的经济有效的解决方案。部分耗尽SOI器件由于体区未完全耗尽，体区处于悬空状态，碰撞电离产生的电荷无法迅速移走，导致出现浮体效应。对于SOINMOS器件，沟道电子在漏端碰撞电离产生的电子空穴对，空穴流向体区，在体区积累，抬高体区电势，使得NMOS的阈值电压降低而增加漏电流，导致器件的输出特性曲线出现翘曲，对器件和电路性能以及可靠性产生不利影响。对于PMOS器件，空穴电离率较低，碰撞电离产生的电子-空穴对远低于NMOS，浮体效应的影响弱一些。
为了解决浮体效应，通常采用体接触的方法，在体区制作电学引出，连接到固定电位（源端或地），从而为体区积累的电荷提供泄放通道，降低体区电势。但是，这样会导致工艺流程更加复杂，增加器件制作成本，降低了部分电学性能并增大了器件面积。
发明内容
本发明旨在至少解决上述技术缺陷，提供一种方法，减小SOI器件的浮体效应，提高半导体器件的性能和可靠性。
为达上述目的，本发明提供了一种半导体结构的制造方法，该方法包括以下步骤：
a）提供SOI衬底，在所述SOI衬底上形成浅沟槽，所述浅沟槽限定的区域对应有源区；
b）在浅沟槽靠近所述有源区的侧壁上形成重掺杂层；
c）填充浅沟槽形成浅沟槽隔离结构；
d）在所述有源区内形成半导体器件。
其中，所述侧壁相邻的有源区对应源区。
步骤（b）中，形成重掺杂的方法为大角度倾斜离子注入。对于NMOS器件，所述重掺杂层的掺杂类型为p型，注入离子为B或BF2；对于PMOS器件，所述重掺杂层的掺杂类型为n型，注入离子为P或As。
根据本发明提供的制造方法，可以在SOI的源极和体区形成pn结，为体区积累的电荷提供泄放通道，减小浮体效应的影响，提高器件的可靠性。同时，由于只是在浅沟槽隔离结构制作时增加了一步工艺，并未影响标准的半导体工艺流程，而且也不必在体区制作电学引出，不会增大器件面积。
附图说明
本发明上述的和/或附加的方面和优点从下面结合附图对实施例的描述中将变得明显和容易理解，其中：
图1是根据本发明的半导体结构的制造方法的一个具体实施方式的流程图；
图2至图11为根据图1示出的方法制造半导体结构过程中该半导体结构在各个制造阶段的剖面、平面俯视结构示意图。
具体实施方式
下面详细描述本发明的实施例，所述实施例的示例在附图中示出，其中自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。下面通过参考附图描述的实施例是示例性的，仅用于解释本发明，而不能解释为对本发明的限制。下文的公开提供了许多不同的实施例或例子用来实现本发明的不同结构。为了简化本发明的公开，下文中对特定例子的部件和设置进行描述。当然，它们仅仅为示例，并且目的不在于限制本发明。此外，本发明可以在不同例子中重复参考数字和/或字母。这种重复是为了简化和清楚的目的，其本身不指示所讨论各种实施例和/或设置之间的关系。此外，本发明提供了的各种特定的工艺和材料的例子，但是本领域普通技术人员可以意识到其他工艺的可应用于性和/或其他材料的使用。另外，以下描述的第一特征在第二特征之“上”的结构可以包括第一和第二特征形成为直接接触的实施例，也可以包括另外的特征形成在第一和第二特征之间的实施例，这样第一和第二特征可能不是直接接触。
图1为根据本发明的半导体结构制造方法的流程图，图2至图11为根据本发明的一个实施例按照图1所示流程制造半导体结构的各个阶段的剖面示意图。下面将结合图2至图11对图1中形成半导体结构的方法进行具体地描述。需要说明的是，本发明实施例的附图仅是为了示意的目的，因此没有必要按比例绘制。
参考图2至图5，在步骤S101中，提供SOI衬底100，在所述SOI衬底100上形成浅沟槽210。
首先，如图2所示，所述SOI衬底100包括基底层101、位于所述基底层101之上的绝缘层102以及位于所述绝缘层102之上的器件层103。
在本实施例中，所述基底层101为单晶硅。在其他实施例中，所述基底层101还可以包括其他基本半导体例如锗，或其他化合物半导体，例如，碳化硅、砷化镓、砷化铟或者磷化铟。典型地，所述基底层101的厚度可以约为但不限于几百微米，例如0.2mm-1mm的厚度范围。所述绝缘层102可以为SiO2、氮化硅、Al2O3或者其他任何合适的绝缘材料，典型地，所述绝缘层102的厚度范围为10nm~300nm。
所述器件层103可以为所述基底层101包括的半导体中的任何一种。在本实施例中，所述器件层103为单晶硅。在其他实施例中，所述器件层103还可以包括其他基本半导体或者化合物半导体。典型地，所述器件层103的厚度范围是10nm~100nm。
随后，如图3所示，在所述SOI衬底100表面上形成掩膜层，进行图形化，定义浅沟槽的图形。所述掩膜层可以具有多层结构，在本实施例中，所述掩膜层是双层结构200和201。所述掩膜层200的材料是氧化硅，掩膜层201的材料是氮化硅。
然后，刻蚀露出的器件层103，形成浅沟槽210。刻蚀的方法包括湿法腐蚀或RIE干法刻蚀，如图4所示。图5是图4所示结构的平面俯视图，所述浅沟槽210呈矩形，所包围的器件层103区域对应有源区，用于制作半导体器件。
执行步骤S102，光刻，露出部分所述浅沟槽，在裸露的浅沟槽210靠近有源区的侧壁上形成重掺杂层310。其中，所述形成重掺杂层310的侧壁相邻的有源区优选为对应源区。优选地，所述侧壁垂直于所述半导体器件对应的沟道的长度方向，也就是，所述形成重掺杂层310的侧壁位于所述有源区中在沟道的长度方向上的其中一端面。首先，在形成重掺杂层之前，采用掩蔽层覆盖所述半导体结构中对应所述半导体器件漏区的部分。具体来说，在所述SOI衬底表面涂覆一层掩蔽层，优选为光刻胶300，进行图形化，露出部分所述浅沟槽，如图6所示。图7是图6所示结构的平面俯视图。其中，靠近裸露浅沟槽210的器件区域用于制作半导体器件的源区，此时未被除去的光刻胶300覆盖所述浅沟槽中靠近将形成半导体器件的漏区的侧壁。随后，在裸露的浅沟槽210靠近源区的侧壁上形成重掺杂层310。形成重掺杂层310的方法为大角度倾斜离子注入，离子注入角度为10°~45°，其中注入能量小于1keV，注入剂量大于5×1014cm-2，掺杂峰值大于7×1019cm-3。对于SOINMOS器件，所述重掺杂层310的掺杂类型为p型，注入离子为B或BF2；对于PMOS器件，所述重掺杂层310的掺杂类型为n型，注入离子为P或As。最后形成的重掺杂层310如图6所示，将要形成的晶体管沟道的长度方向对应为图6中的左右方向，从图中可见重掺杂层310所在浅沟槽210的侧壁基本垂直于该沟道的长度方向。需要说明的是，“基本垂直”意为半导体制造工艺上可以允许的误差内的垂直。由于将形成半导体器件的漏区的侧壁被光刻胶300所保护，因此在漏区侧壁不会形成重掺杂层。
随后，执行步骤S103，填充浅沟槽210形成浅沟槽隔离结构220。具体地，先去除部分填充所述浅沟槽的光刻胶300，然后在所述浅沟槽210中填充氧化硅，最后进行化学机械抛光并去除表面的掩膜层200和201，形成浅沟槽隔离结构220，用于电隔离连续的半导体器件。所述浅沟槽隔离结构220的制作可以遵循标准的半导体工艺完成。图8是形成浅沟槽隔离结构220后的剖面结构图，图9是相应的平面俯视图。所述重掺杂层310夹在所述浅沟槽隔离结构220和用于形成半导体器件的器件层区域之间。
步骤S104中，继续后续标准半导体工艺，形成半导体器件。如图10和11所示，包括形成栅极堆叠、源区400、漏区410、侧墙420以及后续的电学接触和钝化等工艺步骤。所述栅堆叠形成于所述SOI衬底100之上，其包括栅介质层440、栅极430，特别地，还包括栅极覆盖层450。所述栅极堆叠、源区400、漏区410、侧墙420以及后续的电学接触和钝化等工艺步骤，可以通过标准半导体工艺实现，在此，不再赘述。如图10所示，所述重掺杂层310位于所述源区400的下方，与源区形成p+/n+结，为体区积累电荷提供泄放通道，减小了SOI器件的浮体效应，提高了器件性能和可靠性，而且，通过重掺杂层形成pn结，将体区电学连接到源极上，不必单独为体区制作电学引出节省了器件面积。
虽然关于示例实施例及其优点已经详细说明，应当理解在不脱离本发明的精神和所附权利要求限定的保护范围的情况下，可以对这些实施例进行各种变化、替换和修改。对于其他例子，本领域的普通技术人员应当容易理解在保持本发明保护范围内的同时，工艺步骤的次序可以变化。
此外，本发明的应用范围不局限于说明书中描述的特定实施例的工艺、机构、制造、物质组成、手段、方法及步骤。从本发明的公开内容，作为本领域的普通技术人员将容易地理解，对于目前已存在或者以后即将开发出的工艺、机构、制造、物质组成、手段、方法或步骤，其中它们执行与本发明描述的对应实施例大体相同的功能或者获得大体相同的结果，依照本发明可以对它们进行应用。因此，本发明所附权利要求旨在将这些工艺、机构、制造、物质组成、手段、方法或步骤包含在其保护范围内。

Claims (7)

1.一种半导体结构的制造方法，该方法包括以下步骤：
a)提供SOI衬底，在所述SOI衬底上形成浅沟槽，所述浅沟槽限定的区域对应有源区；
b)在浅沟槽靠近所述有源区的侧壁上形成重掺杂层；其中，对于NMOS器件，所述重掺杂层的掺杂类型为p型，注入离子为B或BF2；对于PMOS器件，所述重掺杂层的掺杂类型为n型，注入离子为P或As；
c)填充浅沟槽形成浅沟槽隔离结构；
d)在所述有源区内形成半导体器件。
2.根据权利要求1所述的方法，步骤b)中，所述侧壁相邻的有源区对应源区。
3.根据权利要求2所述的方法，所述侧壁垂直于所述半导体器件对应的沟道的长度方向。
4.根据权利要求1所述的方法，步骤b)中，形成重掺杂的方法为大角度倾斜离子注入。
5.根据权利要求4所述的方法，所述大角度倾斜离子注入的角度为10°～45°。
6.根据权利要求4所述的方法，其中注入能量小于1keV，注入剂量大于5×1014cm-2，掺杂峰值大于7×1019cm-3。
7.根据权利要求1所述的方法，步骤b)中，在形成重掺杂层之前，采用掩蔽层覆盖所述半导体结构中对应所述半导体器件漏区的部分。
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