CN111987152B - 一种抗辐照双栅ldmos器件结构 - Google Patents
一种抗辐照双栅ldmos器件结构 Download PDFInfo
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Abstract
本发明提供一种抗辐照双栅LDMOS器件结构,包括P型衬底、P阱、N型漂移区;源区P+注入、右侧源区N+注入、N+注入、薄栅氧化层、NMOS多晶硅、LDMOS厚栅氧化层、LDMOS多晶硅、LDMOS场氧化层、漏极N+注入,本发明和传统的BCD工艺相兼容,不需要添加任何特殊的工艺步骤;本发明提出的结构,在不改变器件宽长比的情况下,采用了薄栅NMOS作为控制常规LDMOS漏电流从漏极流向源极的开关,能够降低总剂量辐照后产生的泄漏电流,提高总剂量的抗辐照能力。
Description
技术领域
本发明涉及一种功率管,特别涉及一种能降低总剂量辐照后阈值电压漂移量的功率管器件结构。
背景技术
LDMOS(Lateral Double-diffused Metal-Oxide-Semiconductor),相比于VDMOS(Vertical Double-diffused Metal-Oxide-Semiconductor),其更容易与CMOS(Complementary Metal-Oxide-Semiconductor)工艺相兼容。因此LDMOS在集成电路中的也被广泛应用于各种功率转换的集成电路中,如开关电源电路、LDO电路、充电电路等。
当LDMOS器件运用在航天器的开关电源、LDO、充电电路上时,必然受扰辐照的影响。宇宙空间中存在大量的带电粒子和宇宙射线,这些带电粒子和高能射线会导致LDMOS器件的电性参数发生退化,称之为总剂量效应,主要表现有阈值电压降低、跨导降低、亚阈值电流增大、1/f噪声增加,严重的甚至导致元器件完全失效,大幅降低了器件的可靠性。
如图1所示为常规的N型LDMOS的俯视图,图2为图1在C1位置的剖面图。图2包括了位于最下方的P型衬底1,P型存底左上方的P阱2,位于P+注入的右侧的源区N+注入3,位于P阱左上方的源区P+注入4,位于P阱和N漂移区上方的LDMOS厚栅氧化层8,位于栅氧化层上方的LDMOS多晶硅9,位于N漂移区上方的LDMOS场氧化层10,位于N漂移区右上方的漏极N+注入11以及N型漂移区12;常规LDMOS器件边缘处截面图C2如图3所示,在总剂量的作用下,LDMOS边沿的LOCAS部分和场氧化层中俘获了大量空穴,在空穴的作用下,使得Si表面发生反型,形成了漏到源的泄漏电流,致使LDMOS关态电流增加,阈值电压减小,甚至变为负值,这会导致电路功能紊乱,造成灾难性的后果。
目前针对上述问题,提供一种具有双栅结构的抗总剂量阈值电压漂移的LDMOS器件。
发明内容
本发明的目的,是针对LDMOS的LOCAS和场氧中俘获的大量空穴电荷,导致LDMOS边缘出现漏电的问题,提出一种可行的不同于现行LDMOS结构,用于减小总剂量辐照后阈值电压漂移的新结构。
为了达到上述目的,本发明技术方案如下:
一种抗辐照双栅LDMOS器件结构,包括位于底部的P型衬底1;P衬底1左上方的P阱2;P衬底1右上方的N型漂移区12;P阱内左上方的源区P+注入4;位于源区P+注入4的右侧源区N+注入3;位于源区N+注入3的右侧的N+注入5;位于P阱2上方,N+注入3和N+注入5之间的薄栅氧化层6;位于薄栅氧化层6上方的NMOS多晶硅7;位于P阱2和N型漂移区12之上的LDMOS厚栅氧化层8;位于LDMOS厚栅氧化层8上方的LDMOS多晶硅9;位于N型漂移区12上方的LDMOS场氧化层10;位于N型漂移区12右上方的漏极N+注入11,LDMOS厚栅氧化层8的厚度大于薄栅氧化层6。
作为优选方式,器件结构的电路包括NMOS管13、LDMOS管14、分压电阻R1以及R2,电路连接为NMOS13的源极S1和电阻R1的左端共同连接到地,NMOS13的栅极G1连接到电阻R1的右端,同时连接到电阻R2的左端;LDMOS14的源极S2连接NMOS的漏极D1,漏极D2连接到电源电压VDD,栅极G2连接电阻R2的右端同时连接到输入端口VG2。
作为优选方式,在源区N+注入的上方添加一层二氧化硅以及多晶硅,在源区形成的NMOS构成本发明的LDMOS,在辐照后,关态时虽然LDMOS是开启的,但在源区形成的NMOS是关态的,保证了在辐照后产生的泄漏电流不会直接从漏极流向源极,此外为了保证结构能够正常工作,采用poly电阻来作为NMOS栅极和LDMOS栅极的偏置电压,保证器件的正常开关特性以及电学特性。
本发明的工作原理为:本发明在常规LDMOS源极N注入处增加一条薄栅氧化层及多晶硅作为掩膜版,使得常规的LDMOS源极的N+注入被分为两半,形成薄栅NMOS。薄栅氧化层的左侧为NMOS的源极,在NMOS源极的左侧还有作为P阱连接的bulk端,通常将它和NMOS的源极连接在一起,等电位。在NMOS多晶硅的右侧的N+注入作为NMOS的漏极和LDMOS的源极;结构中部为LDMOS的多晶硅栅极,多晶硅下为LDMOS的上氧化层,该栅氧化层较NMOS的栅氧化层厚;对于总剂量辐照,SiO2中俘获的电荷量将随着厚度的减小而大大减小,薄栅NMOS的栅氧化层中,俘获电荷几乎可以忽略不计,同时NMOS还可以作为控制LDMOS从漏极流向源极的开关,从而达到减小关态漏电流的目的。
本发明的有益效果为:与现有的LDMOS相比,本发明和传统的BCD工艺相兼容,不需要添加任何特殊的工艺步骤;本发明提出的结构,在不改变器件宽长比的情况下,采用了薄栅NMOS作为控制常规LDMOS漏电流从漏极流向源极的开关,能够降低总剂量辐照后产生的泄漏电流,提高总剂量的抗辐照能力。
附图说明
图1为常规LDMOS器件的俯视结构图;
图2位常规LDMOS器件在C1位置的剖面图;
图3为常规LDMOS器件在C2位置,总剂量辐照后产生的边缘漏电流剖面示意图;
图4为本发明LDMOS器件的俯视图;
图5为本发明LDMOS器件在C1位置的剖面图;
图6为本发明LDMOS器件在C2位置,总剂量辐照后产生的边缘漏电流剖面示意图;
图7为本发明LDMOS器件在实际运用中的电路图。
其中,1为P型衬底,2为P阱;3为位于源区N+注入;4为源区P+注入;5为N+漏区注入;6为薄栅氧化层;7为NMOS多晶硅;8为LDMOS厚栅氧化层;9为LDMOS多晶硅;10为LDMOS场氧化层;11为漏极N+注入,12为N型漂移区,13为NMOS管,14为LDMOS管。
具体实施方式
以下通过特定的具体实例说明本发明的实施方式,本领域技术人员可由本说明书所揭露的内容轻易地了解本发明的其他优点与功效。本发明还可以通过另外不同的具体实施方式加以实施或应用,本说明书中的各项细节也可以基于不同观点与应用,在没有背离本发明的精神下进行各种修饰或改变。
如图4所示,一种抗辐照双栅LDMOS器件结构,包括位于底部的P型衬底1;P衬底1左上方的P阱2;P衬底1右上方的N型漂移区12;P阱内左上方的源区P+注入4;位于源区P+注入4的右侧源区N+注入3;位于源区N+注入3的右侧的N+注入5;位于P阱2上方,N+注入3和N+注入5之间的薄栅氧化层6;位于薄栅氧化层6上方的NMOS多晶硅7;位于P阱2和N型漂移区12之上的LDMOS厚栅氧化层8;位于LDMOS厚栅氧化层8上方的LDMOS多晶硅9;位于N型漂移区12上方的LDMOS场氧化层10;位于N型漂移区12右上方的漏极N+注入11,LDMOS厚栅氧化层8的厚度大于薄栅氧化层6。
本发明器件结构的电路包括NMOS管13、LDMOS管14、分压电阻R1以及R2,电路连接为NMOS管13的源极S1和电阻R1的左端共同连接到地,NMOS管13的栅极G1连接到电阻R1的右端,同时连接到电阻R2的左端;LDMOS管14的源极S2连接NMOS的漏极D1,漏极D2连接到电源电压VDD,栅极G2连接电阻R2的右端同时连接到输入端口VG2。
本发明能形成关态下总剂量阈值电压漂移,源极的源区形成的NMOS和LDMOS构成本发明的LDMOS,在辐照后,关态时虽然原始LDMOS是开启的,但NMOS是关闭的,开态时,NMOS和LDMOS是同时打开的。
本发明如图5所示,和图2所示常规结构的LDMOS相比,在源极的N+注入上增加了一层薄氧化层,将原来的N+注入分成NMOS的源和漏,由于SiO2的厚度较薄,在总剂量的作用下,SiO2中积累的电荷几乎可以忽略不计,与此同时,NMOS管还作为LDMOS电流从漏极流向源极的开关,在辐照之后,关态条件下从漏极流向源极,在开态条件下与LDMOS同开保证LDMOS的正常开通。
值得注意的是,由于该LDMOS存在两个栅极,在实际应用的时候应该保证NMOS和LDMOS同开和同关,要保证与一个栅极的输出特性相同,不影响器件的正常开关。这里提供一种可以实施的方案,如图7所示,为本发明器件结构应用的电路级示意图。包括NMOS管13,LDMOS管14,分压电阻R1以及R2,电路连接为NMOS管13的源极S1和电阻R1的左端共同连接到地,NMOS管13的栅极G1连接到电阻R1的右端,同时连接到电阻R2的左端;LDMOS管14的源极S2连接NMOS管的漏极D1,漏极D2连接到电源电压VDD,栅极G2连接电阻R2的右端同时连接到输入端口VG2,通过上述连接,形成本发明的电路应用设计,13是本发明的LDMOS的源区NMOS管,14是等效的LDMOS管,NMOS和LDMOS的沟道长度均为L,长度均为W。首先需要保证的是LDMOS和NMOS在开态下的导通电流一致,假设NMOS的开通电流为ID1,LDMOS的开通电流为ID2,则有
对于一个确定的工艺,LDMOS的栅氧化层和NMOS的薄栅氧化层是确定的已知值,而对于已知电路,W/L为确定值,令ID1=ID2,可以知道,要使得本发明的LDMOS同开通同关断需满足VG1-Vth1≤VB≤VG2-Vth2。这里采用电阻分压结构来实现双栅LDMOS晶体管栅极电压的分配,并将电路的导通电流作为考察电路性能的依据,因此通过调节电阻R1和R2的比值可以精准调节电压值VG1来满足同开同关的条件是可以实现的。
BCD工艺中存在由于方块电阻值存在阻值准确性和散热性等方面的差异,在分压电阻的选择上,由于阻值要求比较精确,所以需要选择精度比较高的poly电阻,在poly电阻的制作方法上,与BCD工艺完全相兼容,不会对成本造成很大的影响。
以上通过详细实施步描述了本发明提供的基于常规LDMOS的抗辐照器件结构及实施要求。本发明对器件结构进行了改善,采用了双栅控制LDMOS的开关,在总剂量辐照后的关态情况下,泄漏电流只有在NMOS开通也就是本发明提出的LDMOS在开通的时候才会从漏极流向源极,所以从根本上减小了泄漏电流,降低了阈值漂移的可能性。
上述实施例仅例示性说明本发明的原理及其功效,而非用于限制本发明。任何熟悉此技术的人士皆可在不违背本发明的精神及范畴下,对上述实施例进行修饰或改变。因此,凡所属技术领域中具有通常知识者在未脱离本发明所揭示的精神与技术思想下所完成的一切等效修饰或改变,仍应由本发明的权利要求所涵盖。
Claims (3)
1.一种抗辐照双栅LDMOS器件结构,其特征在于:包括位于底部的P型衬底(1);P衬底(1)左上方的P阱(2);P衬底(1)右上方的N型漂移区(12);P阱内左上方的源区P+注入(4);位于源区P+注入(4)的右侧且与源区P+注入(4)的右侧壁接触的源区N+注入(3);位于源区N+注入(3)右侧的N+漏区注入(5);位于P阱(2)上方,源区N+注入(3)和N+漏区注入(5)之间的薄栅氧化层(6);位于薄栅氧化层(6)上方的NMOS多晶硅(7);位于P阱(2)和N型漂移区(12)之上的LDMOS厚栅氧化层(8);位于LDMOS厚栅氧化层(8)上方的LDMOS多晶硅(9);位于N型漂移区(12)上方的LDMOS场氧化层(10);位于N型漂移区(12)右上方的漏极N+注入(11),LDMOS厚栅氧化层(8)的厚度大于薄栅氧化层(6)。
2.根据权利要求1所述的抗辐照双栅LDMOS器件结构,其特征在于:器件结构的电路包括NMOS管(13)、LDMOS管(14)、分压电阻R1以及R2,电路连接为NMOS(13)的源极S1和电阻R1的左端共同连接到地,NMOS(13)的栅极G1连接到电阻R1的右端,同时连接到电阻R2的左端;LDMOS(14)的源极S2连接NMOS的漏极D1,漏极D2连接到电源电压VDD,栅极G2连接电阻R2的右端同时连接到输入端口VG2。
3.根据权利要求1或2所述的抗辐照双栅LDMOS器件结构,其特征在于:在源区N+注入的上方添加一层二氧化硅以及多晶硅,在源区形成的NMOS构成LDMOS,在辐照后,关态时虽然LDMOS是开启的,但在源区形成的NMOS是关态的,保证了在辐照后产生的泄漏电流不会直接从漏极流向源极,采用poly电阻来作为NMOS栅极和LDMOS栅极的偏置电压,保证器件的正常开关特性以及电学特性。
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