JP2009536449A - ハイサイド動作のパフォーマンスを向上させた高電圧トランジスタ - Google Patents
ハイサイド動作のパフォーマンスを向上させた高電圧トランジスタ Download PDFInfo
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- JP2009536449A JP2009536449A JP2009508156A JP2009508156A JP2009536449A JP 2009536449 A JP2009536449 A JP 2009536449A JP 2009508156 A JP2009508156 A JP 2009508156A JP 2009508156 A JP2009508156 A JP 2009508156A JP 2009536449 A JP2009536449 A JP 2009536449A
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- 239000000758 substrate Substances 0.000 claims abstract description 35
- 230000015556 catabolic process Effects 0.000 claims description 13
- 230000001965 increasing effect Effects 0.000 claims description 7
- 238000002955 isolation Methods 0.000 claims description 4
- 238000001465 metallisation Methods 0.000 claims description 4
- 241000293849 Cordylanthus Species 0.000 description 8
- 238000002513 implantation Methods 0.000 description 7
- 230000005684 electric field Effects 0.000 description 6
- 230000003071 parasitic effect Effects 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 239000008186 active pharmaceutical agent Substances 0.000 description 4
- 238000009413 insulation Methods 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 230000000903 blocking effect Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000002019 doping agent Substances 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 230000007704 transition Effects 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000005401 electroluminescence Methods 0.000 description 1
- 230000001747 exhibiting effect Effects 0.000 description 1
- 230000001939 inductive effect Effects 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 230000032258 transport Effects 0.000 description 1
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- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
- H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
- H01L29/0873—Drain regions
- H01L29/0886—Shape
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
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- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
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- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
- H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
- H01L29/0873—Drain regions
- H01L29/0878—Impurity concentration or distribution
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
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- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
- H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform
Abstract
Description
Claims (13)
- 基板、該基板の表面近傍に形成されたディープnウェル(DN)、該ディープnウェル内に配置された高濃度にnドープされたソース(SO)およびドレイン(DR)、該ソースと該ドレインとのあいだの前記ディープnウェルの表面に配置されフィールド酸化物領域(FO)またはシャロウトレンチ領域、該フィールド酸化物領域または該シャロウトレンチ領域と前記ソースとのあいだに配置されたpドープチャネル領域(CH)、前記フィールド酸化物領域または前記シャロウトレンチ領域および前記チャネル領域を部分的にカバーするゲート(G)、ならびに、前記ディープnウェルを介して前記基板から絶縁されたボディを有しており、前記ディープnウェルは前記フィールド酸化物領域の中央下方にピンチオフ領域(PO)を有しており、前記ディープnウェルは該ピンチオフ領域に最小深さを有しており、前記ゲートは前記ディープnウェルの最小深さのピンチオフポイントの上方に延在している
ことを特徴とする高電圧NMOS型トランジスタ。 - 前記ディープnウェルは2つの部分に分割されており、第1の部分は前記ソースの領域に配置されており、第2の部分は前記ドレインの領域に配置されており、該2つの部分は前記ピンチオフ領域に重なっており、重なっている領域での前記ディープnウェルの深さは前記ボディおよび前記ドレインでのそれぞれの深さよりも小さい、請求項1記載のトランジスタ。
- 平坦なシャロウnウェル(SN)が前記基板の表面近傍の前記ピンチオフ領域内に配置されており、これにより前記ディープnウェル(DN)のnドープ濃度が高められる、請求項1または2記載のトランジスタ。
- ディープpウェル(DP)が前記ソースの下方、前記フィールド酸化物領域の縁または前記シャロウトレンチ領域(シャロウトレンチアイソレーション)の縁から離れたところに配置されている、請求項1から3までのいずれか1項記載のトランジスタ。
- シャロウpウェル(SP)が前記ディープpウェル(DP)内に配置されており、これにより表面から前記シャロウpウェル(SP)へ向かって増大するpドープ濃度の勾配が形成される、請求項4記載のトランジスタ。
- ディープpバッファウェル領域(BW)が前記ディープpウェル(DP)と前記フィールド酸化物領域(FO)の縁または前記シャロウトレンチ領域の縁とのあいだに配置されており、該ディープpバッファウェル領域は前記基板の表面から離れた中央の位置に高いpドープ濃度を有する、請求項4または5記載のトランジスタ。
- 前記ソース(SO)は前記シャロウpウェル(SP)内に配置されている、請求項3から6までのいずれか1項記載のトランジスタ。
- 第1のメタライゼーション層にパターニングされたフィールドプレート(FP)は前記基板表面および前記ゲートから絶縁層を介して絶縁されておりかつスルーコンタクトを介して前記ゲートに電気的に接続されており、前記フィールドプレートは前記フィールド酸化物領域(FO)の中央または前記シャロウトレンチ領域の中央から前記フィールド酸化物領域のうち前記ドレイン(DR)に向かう縁まで延在して前記ゲートに重なっている、請求項1から7までのいずれか1項記載のトランジスタ。
- 当該のトランジスタは少なくとも150Vのブレークダウン電圧を有する、請求項1から8までのいずれか1項記載のトランジスタ。
- 当該のトランジスタは0V〜200Vのブレークダウン電圧を有する、請求項1から8までのいずれか1項記載のトランジスタ。
- 前記ゲート(G)および前記フィールド酸化物領域(FO)はそれぞれ前記ドレイン(DR)ヘ向かう縁を有しており、前記ゲートの縁は前記フィールド酸化物領域の縁と前記ディープnウェル(DN)が最小深さを有する前記ピンチオフ領域(PO)の上方のポイントとのあいだに位置する、請求項1から10までのいずれか1項記載のトランジスタ。
- 請求項1から11までのいずれか1項記載のトランジスタを200Vまでの高いドレイン‐ソース電圧での電流切り換えに用いることを特徴とするトランジスタの使用。
- 請求項1から11までのいずれか1項記載のトランジスタを0V〜200Vまでの高いソース‐基板電圧を有する集積回路内で用いることを特徴とするトランジスタの使用。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP06009366.3 | 2006-05-05 | ||
EP06009366A EP1852916A1 (en) | 2006-05-05 | 2006-05-05 | High voltage transistor |
PCT/EP2007/003338 WO2007128383A1 (en) | 2006-05-05 | 2007-04-16 | High voltage transistor with improved high side performance |
Publications (2)
Publication Number | Publication Date |
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JP2009536449A true JP2009536449A (ja) | 2009-10-08 |
JP5175271B2 JP5175271B2 (ja) | 2013-04-03 |
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Application Number | Title | Priority Date | Filing Date |
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JP2009508156A Expired - Fee Related JP5175271B2 (ja) | 2006-05-05 | 2007-04-16 | ハイサイド動作のパフォーマンスを向上させた高電圧トランジスタ |
Country Status (5)
Country | Link |
---|---|
US (1) | US8212318B2 (ja) |
EP (2) | EP1852916A1 (ja) |
JP (1) | JP5175271B2 (ja) |
KR (1) | KR100927065B1 (ja) |
WO (1) | WO2007128383A1 (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2008066508A (ja) * | 2006-09-07 | 2008-03-21 | New Japan Radio Co Ltd | 半導体装置 |
Families Citing this family (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7968950B2 (en) * | 2007-06-27 | 2011-06-28 | Texas Instruments Incorporated | Semiconductor device having improved gate electrode placement and decreased area design |
DE102009021241A1 (de) * | 2009-05-14 | 2010-11-18 | Austriamicrosystems Ag | Hochvolt-Transistor mit vergrabener Driftstrecke und Herstellungsverfahren |
DE102010014370B4 (de) * | 2010-04-09 | 2021-12-02 | X-Fab Semiconductor Foundries Ag | LDMOS-Transistor und LDMOS - Bauteil |
WO2012139633A1 (en) * | 2011-04-12 | 2012-10-18 | X-Fab Semiconductor Foundries Ag | Bipolar transistor with gate electrode over the emitter base junction |
DE102011108651B4 (de) * | 2011-07-26 | 2019-10-17 | Austriamicrosystems Ag | Hochvolttransistorbauelement und Herstellungsverfahren |
DE102011056412B4 (de) | 2011-12-14 | 2013-10-31 | Austriamicrosystems Ag | Hochvolttransistorbauelement und Herstellungsverfahren |
US9245997B2 (en) * | 2013-08-09 | 2016-01-26 | Magnachip Semiconductor, Ltd. | Method of fabricating a LDMOS device having a first well depth less than a second well depth |
KR102389294B1 (ko) * | 2015-06-16 | 2022-04-20 | 삼성전자주식회사 | 반도체 장치 및 그 제조 방법 |
CN107492497A (zh) * | 2016-06-12 | 2017-12-19 | 中芯国际集成电路制造(上海)有限公司 | 晶体管的形成方法 |
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2006
- 2006-05-05 EP EP06009366A patent/EP1852916A1/en not_active Withdrawn
-
2007
- 2007-04-16 JP JP2009508156A patent/JP5175271B2/ja not_active Expired - Fee Related
- 2007-04-16 KR KR1020087003034A patent/KR100927065B1/ko active IP Right Grant
- 2007-04-16 US US12/299,741 patent/US8212318B2/en active Active
- 2007-04-16 EP EP07724276.6A patent/EP2016623B1/en not_active Expired - Fee Related
- 2007-04-16 WO PCT/EP2007/003338 patent/WO2007128383A1/en active Application Filing
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JP2001210823A (ja) * | 2000-01-21 | 2001-08-03 | Denso Corp | 半導体装置 |
JP2001250947A (ja) * | 2000-03-06 | 2001-09-14 | Toshiba Corp | 電力用半導体素子およびその製造方法 |
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Cited By (1)
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JP2008066508A (ja) * | 2006-09-07 | 2008-03-21 | New Japan Radio Co Ltd | 半導体装置 |
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Publication number | Publication date |
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US8212318B2 (en) | 2012-07-03 |
EP2016623B1 (en) | 2014-03-12 |
WO2007128383A1 (en) | 2007-11-15 |
KR100927065B1 (ko) | 2009-11-13 |
EP1852916A1 (en) | 2007-11-07 |
KR20080033361A (ko) | 2008-04-16 |
US20090321822A1 (en) | 2009-12-31 |
EP2016623A1 (en) | 2009-01-21 |
JP5175271B2 (ja) | 2013-04-03 |
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