JP5175271B2 - ハイサイド動作のパフォーマンスを向上させた高電圧トランジスタ - Google Patents
ハイサイド動作のパフォーマンスを向上させた高電圧トランジスタ Download PDFInfo
- Publication number
- JP5175271B2 JP5175271B2 JP2009508156A JP2009508156A JP5175271B2 JP 5175271 B2 JP5175271 B2 JP 5175271B2 JP 2009508156 A JP2009508156 A JP 2009508156A JP 2009508156 A JP2009508156 A JP 2009508156A JP 5175271 B2 JP5175271 B2 JP 5175271B2
- Authority
- JP
- Japan
- Prior art keywords
- well
- region
- deep
- source
- field oxide
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000000758 substrate Substances 0.000 claims description 32
- 238000002513 implantation Methods 0.000 claims description 10
- 230000001965 increasing effect Effects 0.000 claims description 7
- 238000000034 method Methods 0.000 claims description 6
- 239000002019 doping agent Substances 0.000 claims description 4
- 238000001465 metallisation Methods 0.000 claims description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 2
- 229920005591 polysilicon Polymers 0.000 claims description 2
- 238000004519 manufacturing process Methods 0.000 claims 1
- 230000015556 catabolic process Effects 0.000 description 10
- 241000293849 Cordylanthus Species 0.000 description 8
- 230000005684 electric field Effects 0.000 description 6
- 230000003071 parasitic effect Effects 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 239000008186 active pharmaceutical agent Substances 0.000 description 4
- 238000009413 insulation Methods 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 238000002955 isolation Methods 0.000 description 3
- 230000000903 blocking effect Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 230000007704 transition Effects 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000005401 electroluminescence Methods 0.000 description 1
- 230000001747 exhibiting effect Effects 0.000 description 1
- 230000001939 inductive effect Effects 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 230000032258 transport Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
- H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
- H01L29/0873—Drain regions
- H01L29/0886—Shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
- H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
- H01L29/0873—Drain regions
- H01L29/0878—Impurity concentration or distribution
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
- H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- High Energy & Nuclear Physics (AREA)
- Health & Medical Sciences (AREA)
- Toxicology (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Description
Claims (5)
- 高電圧NMOS型トランジスタを製造する方法において、
該高電圧NMOS型トランジスタは、
基板、
該基板の表面近傍に形成されたディープnウェル(DN)、
該ディープnウェル内に配置された高濃度にnドープされたソース(SO)およびドレイン(DR)、
該ソースと該ドレインとのあいだの前記ディープnウェルの表面に配置されたフィールド酸化物領域(FO)またはシャロウトレンチ領域、
該フィールド酸化物領域または該シャロウトレンチ領域と前記ソースとのあいだに配置されたpドープチャネル領域(CH)、
前記フィールド酸化物領域または前記シャロウトレンチ領域および前記チャネル領域を部分的にカバーするゲート(G)、ならびに、
前記フィールド酸化物領域またはシャロウトレンチの中央下方に配置されたピンチオフ領域(PO)を含むディープnウェルを有しており、ただし前記ディープnウェルは最小深さを有しており、
前記方法は、
前記ピンチオフ領域(PO)を上回る長さ(D)を有するインプランテーションレジストエリアを有するインプランテーションマスクを介して、nドーパントをインプランテーション(NI)することによって前記ディープnウェル(DN)を製造するステップと、
nドーパントの専用のインプランテーションにより、前記ピンチオフ領域(PO)の基板の(SU)の表面の近くにシャロウnウェル(SN)を形成して、当該シャロウnウェルによって前記ディープnウェル(DN)のnドーピング濃度を高めるステップとを有する、ことを特徴とする高電圧NMOS型トランジスタを製造する方法。 - さらに前記ソース(SO)の下方において、前記フィールド酸化物領域(FO)の縁から離してディープpウェル(DP)を配置するステップを有する、
請求項1に記載の方法。 - 前記ディープpウェル(DP)と前記フィールド酸化物領域(FO)のソース側の縁とのあいだにディープpバッファウェル(BW)をインプランテーションし、
ただし当該ディープpバッファウェル(BW)を前記ディープnウェル(DN)に対して反対にドーピングし、前記基板(SU)の表面から離れている中央において最も高いpドーピングノードを有するようにする、
請求項2に記載の方法。 - ゲート(G)は、ポリシリコンからなり、前記ソース(SO)から前記フィールド酸化物領域(FO)の中央部まで延在している、
請求項1から3までのいずれか1項に記載の方法。 - 前記ゲート(G)の上方の第1メタライゼーション面にフィールドプレート(FP)を配置する、
請求項1から4までのいずれか1項に記載の方法。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP06009366.3 | 2006-05-05 | ||
EP06009366A EP1852916A1 (en) | 2006-05-05 | 2006-05-05 | High voltage transistor |
PCT/EP2007/003338 WO2007128383A1 (en) | 2006-05-05 | 2007-04-16 | High voltage transistor with improved high side performance |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2009536449A JP2009536449A (ja) | 2009-10-08 |
JP5175271B2 true JP5175271B2 (ja) | 2013-04-03 |
Family
ID=37075934
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2009508156A Expired - Fee Related JP5175271B2 (ja) | 2006-05-05 | 2007-04-16 | ハイサイド動作のパフォーマンスを向上させた高電圧トランジスタ |
Country Status (5)
Country | Link |
---|---|
US (1) | US8212318B2 (ja) |
EP (2) | EP1852916A1 (ja) |
JP (1) | JP5175271B2 (ja) |
KR (1) | KR100927065B1 (ja) |
WO (1) | WO2007128383A1 (ja) |
Families Citing this family (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5148852B2 (ja) * | 2006-09-07 | 2013-02-20 | 新日本無線株式会社 | 半導体装置 |
US7968950B2 (en) * | 2007-06-27 | 2011-06-28 | Texas Instruments Incorporated | Semiconductor device having improved gate electrode placement and decreased area design |
DE102009021241A1 (de) * | 2009-05-14 | 2010-11-18 | Austriamicrosystems Ag | Hochvolt-Transistor mit vergrabener Driftstrecke und Herstellungsverfahren |
DE102010014370B4 (de) * | 2010-04-09 | 2021-12-02 | X-Fab Semiconductor Foundries Ag | LDMOS-Transistor und LDMOS - Bauteil |
WO2012139633A1 (en) * | 2011-04-12 | 2012-10-18 | X-Fab Semiconductor Foundries Ag | Bipolar transistor with gate electrode over the emitter base junction |
DE102011108651B4 (de) | 2011-07-26 | 2019-10-17 | Austriamicrosystems Ag | Hochvolttransistorbauelement und Herstellungsverfahren |
DE102011056412B4 (de) | 2011-12-14 | 2013-10-31 | Austriamicrosystems Ag | Hochvolttransistorbauelement und Herstellungsverfahren |
US9245997B2 (en) * | 2013-08-09 | 2016-01-26 | Magnachip Semiconductor, Ltd. | Method of fabricating a LDMOS device having a first well depth less than a second well depth |
KR102389294B1 (ko) * | 2015-06-16 | 2022-04-20 | 삼성전자주식회사 | 반도체 장치 및 그 제조 방법 |
CN107492497A (zh) * | 2016-06-12 | 2017-12-19 | 中芯国际集成电路制造(上海)有限公司 | 晶体管的形成方法 |
Family Cites Families (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS57180164A (en) * | 1981-04-30 | 1982-11-06 | Nec Corp | Semiconductor device |
US4626879A (en) * | 1982-12-21 | 1986-12-02 | North American Philips Corporation | Lateral double-diffused MOS transistor devices suitable for source-follower applications |
JPH05121738A (ja) * | 1991-10-24 | 1993-05-18 | Fuji Electric Co Ltd | Misfetを有する半導体装置 |
EP0613186B1 (en) * | 1993-02-24 | 1997-01-02 | STMicroelectronics S.r.l. | Fully depleted lateral transistor |
US6639277B2 (en) * | 1996-11-05 | 2003-10-28 | Power Integrations, Inc. | High-voltage transistor with multi-layer conduction region |
JP2001210823A (ja) * | 2000-01-21 | 2001-08-03 | Denso Corp | 半導体装置 |
JP4371521B2 (ja) * | 2000-03-06 | 2009-11-25 | 株式会社東芝 | 電力用半導体素子およびその製造方法 |
JP4460741B2 (ja) * | 2000-09-27 | 2010-05-12 | 株式会社東芝 | 電力用半導体素子及びその製造方法 |
US20040108544A1 (en) * | 2002-12-09 | 2004-06-10 | Semiconductor Components Industries, Llc | High voltage mosfet with laterally varying drain doping and method |
US6903421B1 (en) * | 2004-01-16 | 2005-06-07 | System General Corp. | Isolated high-voltage LDMOS transistor having a split well structure |
US6995428B2 (en) * | 2004-02-24 | 2006-02-07 | System General Corp. | High voltage LDMOS transistor having an isolated structure |
DE102004009521B4 (de) * | 2004-02-27 | 2020-06-10 | Austriamicrosystems Ag | Hochvolt-PMOS-Transistor, Maske zur Herstellung einer Wanne und Verfahren zur Herstellung eines Hochvolt-PMOS-Transistors |
DE102004014928B4 (de) * | 2004-03-26 | 2018-07-12 | Austriamicrosystems Ag | Hochvolttransistor und Verfahren zu seiner Herstellung |
DE102004038369B4 (de) * | 2004-08-06 | 2018-04-05 | Austriamicrosystems Ag | Hochvolt-NMOS-Transistor und Herstellungsverfahren |
JP4863665B2 (ja) * | 2005-07-15 | 2012-01-25 | 三菱電機株式会社 | 半導体装置およびその製造方法 |
-
2006
- 2006-05-05 EP EP06009366A patent/EP1852916A1/en not_active Withdrawn
-
2007
- 2007-04-16 US US12/299,741 patent/US8212318B2/en active Active
- 2007-04-16 JP JP2009508156A patent/JP5175271B2/ja not_active Expired - Fee Related
- 2007-04-16 WO PCT/EP2007/003338 patent/WO2007128383A1/en active Application Filing
- 2007-04-16 KR KR1020087003034A patent/KR100927065B1/ko active IP Right Grant
- 2007-04-16 EP EP07724276.6A patent/EP2016623B1/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
KR20080033361A (ko) | 2008-04-16 |
EP1852916A1 (en) | 2007-11-07 |
JP2009536449A (ja) | 2009-10-08 |
EP2016623A1 (en) | 2009-01-21 |
KR100927065B1 (ko) | 2009-11-13 |
US8212318B2 (en) | 2012-07-03 |
US20090321822A1 (en) | 2009-12-31 |
EP2016623B1 (en) | 2014-03-12 |
WO2007128383A1 (en) | 2007-11-15 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP5175271B2 (ja) | ハイサイド動作のパフォーマンスを向上させた高電圧トランジスタ | |
US8652930B2 (en) | Semiconductor device with self-biased isolation | |
US20180138312A1 (en) | Lateral DMOS Device with Dummy Gate | |
TWI438898B (zh) | 自我對準之互補雙擴散金氧半導體 | |
US9082846B2 (en) | Integrated circuits with laterally diffused metal oxide semiconductor structures | |
US8278710B2 (en) | Guard ring integrated LDMOS | |
CN110828571B (zh) | 半导体器件及其制备方法 | |
US9537000B2 (en) | Semiconductor device with increased safe operating area | |
US7898030B2 (en) | High-voltage NMOS-transistor and associated production method | |
KR20190008463A (ko) | 반도체 소자 및 그 제조 방법 | |
CN103178097A (zh) | 用于高电压晶体管器件的伪栅极 | |
EP2924723B1 (en) | Integrated circuit | |
US20100163990A1 (en) | Lateral Double Diffused Metal Oxide Semiconductor Device | |
US7851883B2 (en) | Semiconductor device and method of manufacture thereof | |
JP2009059949A (ja) | 半導体装置、および、半導体装置の製造方法 | |
KR101781220B1 (ko) | 디프레션형 mos 트랜지스터를 갖는 반도체 장치 | |
JP5280142B2 (ja) | 半導体装置およびその製造方法 | |
KR20110078621A (ko) | 반도체 소자 및 그 제조 방법 | |
US9653459B2 (en) | MOSFET having source region formed in a double wells region | |
KR102256226B1 (ko) | 낮은 소스-드레인 저항을 갖는 반도체 소자 및 그 제조 방법 | |
JP4190311B2 (ja) | 半導体装置 | |
JP5463698B2 (ja) | 半導体素子、半導体装置および半導体素子の製造方法 | |
US9608109B1 (en) | N-channel demos device | |
US20100224933A1 (en) | Semiconductor device | |
US11367788B2 (en) | Semiconductor device structure |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
RD04 | Notification of resignation of power of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7424 Effective date: 20101227 Free format text: JAPANESE INTERMEDIATE CODE: A7424 Effective date: 20101228 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20120314 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20120614 |
|
A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 20120711 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20121112 |
|
A911 | Transfer to examiner for re-examination before appeal (zenchi) |
Free format text: JAPANESE INTERMEDIATE CODE: A911 Effective date: 20121119 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20121207 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20130104 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 5175271 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
LAPS | Cancellation because of no payment of annual fees |