CN102522424B - 一种减小电荷共享效应的cmos器件及其制备方法 - Google Patents

一种减小电荷共享效应的cmos器件及其制备方法 Download PDF

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CN102522424B
CN102522424B CN201110436842.8A CN201110436842A CN102522424B CN 102522424 B CN102522424 B CN 102522424B CN 201110436842 A CN201110436842 A CN 201110436842A CN 102522424 B CN102522424 B CN 102522424B
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黄如
谭斐
安霞
黄芊芊
杨东
张兴
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Abstract

本发明公开了一种减小电荷共享效应的CMOS器件及其制备方法。本发明的CMOS器件在隔离区的正下方设置俘获载流子的附加隔离区。该附加隔离区的材料为多孔硅等，由于多孔硅是一种通过电化学阳极氧化单晶硅片形成的海绵状结构的功能材料，多孔硅的表面层内存在大量的微孔和悬挂键。这些缺陷会在多孔硅的禁带中央形成缺陷态，缺陷态可俘获载流子，导致电阻增大，且随着腐蚀电流密度的增大，孔隙率增大，多孔硅中的缺陷增多。本发明中利用多孔硅中缺陷态俘获载流子的特性可减小重离子引起的电荷共享效应，浅沟道隔离STI区和下方隔离区的形成只需要一次光刻，工艺简单，且可以极大地提高集成电路的抗辐射性能。

Description

一种减小电荷共享效应的CMOS器件及其制备方法
技术领域
本发明涉及COMS器件，具体涉及一种减小辐射环境下电荷共享效应的CMOS器件及其制备方法。
背景技术
随着半导体技术的不断发展，集成电路元器件的尺寸已经远远小于100纳米。宇宙空间中或者地面上高能带电离子在穿过集成电路元器件时，径迹中沉积的大量电子空穴对会被集成电路元器件的敏感节点(反偏pn结)所收集，造成器件逻辑状态的非正常改变或器件损坏。对于传统的集成电路中元器件，器件间距离较大，一个带电离子径迹上的电子空穴对通常只能被一个元器件的敏感节点所收集。但是为了提高集成电路的集成度，器件间距离不断缩小，一个带电离子径迹上的电子空穴对在复合前会通过扩散运动到达其他元器件，在更多的敏感节点附近被收集，这一现象即称为电荷共享效应。电荷共享效应会造成集成电路多个节点同时发生翻转，增大翻转横截面，降低发生翻转所需要的能量阈值。此外，电荷共享效应会造成如保护环等器件级和电路级的抗辐射加固技术的失效。
如图1所示，当重离子入射到小尺寸的传统CMOS器件时，由重离子电离作用，在重离子入射轨迹05的附近生成的电子空穴对04从入射主器件02通过扩散运动到达入射临近器件03，传统的CMOS器件的隔离区01不能抑制重离子辐射下的电荷共享效应。
发明内容
为了克服器件间距离变小产生多节点翻转以及加固技术失效等问题，本发明提出一种可以减小单粒子入射一个器件时多个器件共同收集电荷的CMOS器件。
本发明的一个目的在于提出一种减小辐射环境下电荷共享效应的CMOS器件。
本发明的器件包括衬底、隔离区、有源区、栅区、LDD区、栅侧墙、源区和漏区，其中，在隔离区的正下方设置俘获载流子的附加隔离区。
该附加隔离区的材料为具有多孔和悬挂键的材料，如多孔硅等。
本发明的另一个目的是提供一种减小辐射环境下电荷共享效应的CMOS器件的制备方法。
本发明的CMOS器件的制备方法包括以下步骤：
1)提供一个硅片作为衬底，将其正面化学抛光为镜面，经常规清洗工艺，在背面蒸铝形成铝膜作为欧姆接触，同时在铝膜上涂上一层防酸保护层；
2)将硅片放入氢氟酸和酒精的混合溶液中，将衬底的背面的铝膜作为阳极，铂片作为阴极，通以恒定电流进行腐蚀，腐蚀结束后取出硅片，进行清洗，刻蚀掉硅片背面的铝，生成成硅-多孔硅形成附加隔离区；
3)在附加隔离区上热氧化生成一层二氧化硅，光刻后刻蚀，留出器件的隔离区；
4)外延一层半导体材料，如硅，将其平坦化，形成器件的有源区；
5)热氧化一薄层栅介质的材料，如二氧化硅或者高K材料，光刻刻蚀后形成器件的栅介质；
6)生长屏蔽氧化层并淀积栅的材料，如多晶硅或金属，光刻后形成栅图形，刻蚀栅材料，形成器件的栅区；
7)进行注入形成LDD区；
8)淀积栅侧墙的材料，如二氧化硅或者氮化硅等，各向异性刻蚀形成栅侧墙；
9)进行源漏注入形成源区和漏区，退火以进行杂质激活。
本发明的有益效果：
本发明的器件在隔离区的正下方设置具有多孔和悬挂键的材料，如多孔硅的附加隔离区，由于多孔硅是一种通过电化学阳极氧化单晶硅片形成的海绵状结构的功能材料，多孔硅的表面层内存在大量的微孔和悬挂键。这些缺陷会在多孔硅的禁带中央形成缺陷态，缺陷态可俘获载流子，导致电阻增大，且随着腐蚀电流密度的增大，孔隙率增大，多孔硅中的缺陷增多。本发明中利用多孔硅中缺陷态俘获载流子的特性可减小重离子引起的电荷共享效应，浅沟道隔离STI区和下方隔离区的形成只需要一次光刻，工艺简单，且可以极大地提高集成电路的抗辐射性能。
附图说明
图1表示当重离子入射到小尺寸的传统的CMOS器件时，传统的隔离区不能抑制重离子辐射下的电荷共享效应的示意图；
图2表示在传统CMOS器件隔离区下方加入多孔硅构成的附加隔离区后，重离子在入射器件中电离出的电子空穴对在扩散到临近器件时，被多孔硅构成的附加隔离区的缺陷所俘获的示意图；
图3表示本发明的减小辐射环境下电荷共享效应的CMOS器件的剖面图；
图4(a)至(f)表示根据本发明的一个实施例的CMOS器件的制备方法的流程图。
具体实施方式
下面结合说明书附图详描述本发明的实施方式。
如图2所示，以NMOS器件为例，当被重离子打击后，重离子径迹方向上会电离出大量的电子空穴对，空穴向衬底方向移动，一部分电子会被该被重离子入射器件的敏感节点所收集，另一部分电子则通过扩散作用从器件的隔离区(如STI区)下方扩散到周围器件的敏感节点而被收集。因此在器件隔离区下方设置多孔硅材料的附加隔离区3，则可使电子或者空穴向周围器件扩散时被俘获，减小到达周围器件敏感节点的电子空穴数目，从而能够有效抑制电荷共享效应的发生。
如图3所示，本发明的CMOS器件包括衬底1、隔离区4、有源区5、栅区6、LDD区7、栅侧墙8、源区和漏区9，其中，在隔离区的正下方设置附加隔离区3，该附加隔离区的材料为多孔硅。
以NMOS器件为例，进一步阐述本发明的器件的制备方法，具体包括以下步骤：
1)提供晶向为(100)的P型硅片作为衬底1，将其正面a化学抛光为镜面，经常规清洗工艺，在背面b蒸铝形成铝膜2作为欧姆接触，同时在铝膜上涂上一层防酸保护层，如图4(a)所示；
2)将硅片放入氢氟酸和酒精的混合溶液中，将硅片的背面b的铝膜作为阳极，铂片作为阴极，通以恒定电流100mA/cm2，腐蚀时间为20～25min，腐蚀结束后取出硅片，进行清洗，刻蚀掉硅片背面的铝，形成硅-多孔硅3，如图4(b)所示；
3)在多孔硅3上淀积一层二氧化硅，光刻出STI区图形后刻蚀，留出器件的隔离区4，如图4(c)所示；
4外延一层硅，将其平坦化，形成器件的有源区5，如图4(d)；
5)热氧化一薄层二氧化硅，光刻刻蚀后形成器件的栅介质10，如图4(e)所示；
6)生长屏蔽氧化层并沉积多晶硅，光刻后形成栅图形，刻蚀多晶硅，形成器件的栅区6，如图4(f)所示；
7)采用磷或者砷进行注入形成LDD区7，如图4(g)所示；
8)淀积二氧化硅，各向异性刻蚀形成栅侧墙8，如图4(h)所示；
9)采用磷或者砷进行源漏注入形成源区和漏区9，退火以进行杂质激活，如图4(i)所示。
最后需要注意的是，公布实施方式的目的在于帮助进一步理解本发明，但是本领域的技术人员可以理解：在不脱离本发明及所附的权利要求的精神和范围内，各种替换和修改都是可能的。因此，本发明不应局限于实施例所公开的内容，本发明要求保护的范围以权利要求书界定的范围为准。

Claims (6)

1.一种减小辐射环境下电荷共享效应的CMOS器件的制备方法，其特征在于，包括以下步骤：
1）提供一个硅片作为衬底，将其正面化学抛光为镜面，经常规清洗工艺，在背面蒸铝形成铝膜作为欧姆接触，同时在铝膜上涂上一层防酸保护层；
2）将硅片放入氢氟酸和酒精的混合溶液中，将衬底的背面的铝膜作为阳极，铂片作为阴极，通以恒定电流进行腐蚀，腐蚀结束后取出硅片，进行清洗，刻蚀掉硅片背面的铝，生成硅-多孔硅形成附加隔离区；
3）在附加隔离区上热氧化生成一层二氧化硅，光刻后刻蚀，留出器件的隔离区；
4）外延一层半导体材料，将其平坦化，形成器件的有源区；
5）热氧化一薄层栅介质的材料，光刻刻蚀后形成器件的栅介质；
6）生长屏蔽氧化层并淀积栅的材料，光刻后形成栅图形，刻蚀栅材料，形成器件的栅区；
7）进行注入形成LDD区；
8）淀积栅侧墙的材料，各向异性刻蚀形成栅侧墙；
9）进行源漏注入形成源区和漏区，退火以进行杂质激活。
2.如权利要求1所述的制备方法，其特征在于，在步骤4）中所述半导体材料为硅。
3.如权利要求1所述的制备方法，其特征在于，在步骤5）中所述栅介质的材料为二氧化硅或者高K材料。
4.如权利要求1所述的制备方法，其特征在于，在步骤6）中所述栅的材料为多晶硅或者金属。
5.如权利要求1所述的制备方法，其特征在于，在步骤8）中所述栅侧墙的材料为二氧化硅或者氮化硅。
6.如权利要求1所述的制备方法，其特征在于，在步骤2）中恒定电流为100mA/cm2，腐蚀时间为20～25min。
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