WO2013091331A1 - 一种减小电荷共享效应的cmos器件及其制备方法 - Google Patents
一种减小电荷共享效应的cmos器件及其制备方法 Download PDFInfo
- Publication number
- WO2013091331A1 WO2013091331A1 PCT/CN2012/074076 CN2012074076W WO2013091331A1 WO 2013091331 A1 WO2013091331 A1 WO 2013091331A1 CN 2012074076 W CN2012074076 W CN 2012074076W WO 2013091331 A1 WO2013091331 A1 WO 2013091331A1
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- Prior art keywords
- gate
- region
- silicon
- isolation region
- cmos device
- Prior art date
Links
- 230000000694 effects Effects 0.000 title claims abstract description 17
- 238000002360 preparation method Methods 0.000 title claims abstract description 4
- 238000002955 isolation Methods 0.000 claims abstract description 35
- 239000000463 material Substances 0.000 claims abstract description 21
- 229910021426 porous silicon Inorganic materials 0.000 claims abstract description 17
- 239000000758 substrate Substances 0.000 claims abstract description 10
- 238000004519 manufacturing process Methods 0.000 claims abstract description 6
- 239000000969 carrier Substances 0.000 claims abstract description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 18
- 238000005530 etching Methods 0.000 claims description 18
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 16
- 229910052782 aluminium Inorganic materials 0.000 claims description 16
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 16
- 229910052710 silicon Inorganic materials 0.000 claims description 16
- 239000010703 silicon Substances 0.000 claims description 16
- 238000000034 method Methods 0.000 claims description 11
- 239000010410 layer Substances 0.000 claims description 10
- 230000005855 radiation Effects 0.000 claims description 10
- 239000000377 silicon dioxide Substances 0.000 claims description 9
- 238000000206 photolithography Methods 0.000 claims description 8
- 235000012239 silicon dioxide Nutrition 0.000 claims description 8
- 125000006850 spacer group Chemical group 0.000 claims description 8
- 238000000151 deposition Methods 0.000 claims description 7
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims description 6
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 claims description 6
- 230000001590 oxidative effect Effects 0.000 claims description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 4
- 229920005591 polysilicon Polymers 0.000 claims description 4
- 239000004065 semiconductor Substances 0.000 claims description 4
- LFQSCWFLJHTTHZ-UHFFFAOYSA-N Ethanol Chemical compound CCO LFQSCWFLJHTTHZ-UHFFFAOYSA-N 0.000 claims description 3
- 230000004913 activation Effects 0.000 claims description 3
- 238000004140 cleaning Methods 0.000 claims description 3
- 238000002513 implantation Methods 0.000 claims description 3
- 239000012535 impurity Substances 0.000 claims description 3
- 239000011259 mixed solution Substances 0.000 claims description 3
- 229910052697 platinum Inorganic materials 0.000 claims description 3
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 2
- 239000003989 dielectric material Substances 0.000 claims description 2
- 238000002347 injection Methods 0.000 claims description 2
- 239000007924 injection Substances 0.000 claims description 2
- 229910052751 metal Inorganic materials 0.000 claims description 2
- 239000002184 metal Substances 0.000 claims description 2
- 238000005498 polishing Methods 0.000 claims description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 2
- 230000001458 anti-acid effect Effects 0.000 claims 1
- 230000003647 oxidation Effects 0.000 claims 1
- 238000007254 oxidation reaction Methods 0.000 claims 1
- 239000011241 protective layer Substances 0.000 claims 1
- 150000002500 ions Chemical class 0.000 abstract description 14
- 230000007547 defect Effects 0.000 description 6
- 238000009792 diffusion process Methods 0.000 description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- 230000033001 locomotion Effects 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 230000002787 reinforcement Effects 0.000 description 2
- 208000033999 Device damage Diseases 0.000 description 1
- 230000002159 abnormal effect Effects 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 238000002048 anodisation reaction Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 230000006798 recombination Effects 0.000 description 1
- 238000005215 recombination Methods 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823878—Complementary field-effect transistors, e.g. CMOS isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/30—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by physical imperfections; having polished or roughened surface
- H01L29/32—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by physical imperfections; having polished or roughened surface the imperfections being within the semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
- H01L27/0921—Means for preventing a bipolar, e.g. thyristor, action between the different transistor regions, e.g. Latchup prevention
Definitions
- the present invention relates to a COMS device, and in particular to a CMOS device for reducing charge sharing effects in a radiation environment and a method of fabricating the same.
- the electron-hole pairs on a charged ion track will reach other components through diffusion movement before recombination, and are collected near more sensitive nodes.
- the phenomenon is called the charge sharing effect.
- the charge sharing effect causes multiple nodes of the integrated circuit to flip at the same time, increasing the flip cross section and reducing the energy threshold required for flipping.
- charge sharing effects can cause failures in radiation-resistant reinforcement techniques such as device-level and circuit-level protection loops.
- the present invention proposes a CMOS device capable of reducing the collective collection of charges by a plurality of devices when a single particle is incident on one device.
- the device of the present invention includes a substrate, an isolation region, an active region, a gate region, an LDD region, a gate spacer, a source region, and a drain region, wherein an additional isolation region for trapping carriers is disposed directly under the isolation region.
- the material of the additional isolation region is a material having porous and dangling bonds, such as porous silicon or the like.
- Another object of the present invention is to provide a method of fabricating a CMOS device that reduces the charge sharing effect in a radiation environment.
- the method of fabricating the CMOS device of the present invention comprises the following steps:
- the silicon wafer is placed in a mixed solution of hydrofluoric acid and alcohol, and the aluminum film on the back side of the substrate is used as an anode, and the platinum sheet is used as a cathode, and is etched by a constant current. After the etching is completed, the silicon wafer is taken out and cleaned. Etching the aluminum on the back side of the silicon wafer to form silicon-porous silicon to form an additional isolation region;
- gate dielectric material such as silicon dioxide or a high-k material
- the device of the present invention is provided with a material having porous and dangling bonds directly under the isolation region, such as an additional isolation region of porous silicon, since porous silicon is a functional material of a sponge-like structure formed by electrochemical anodization of a single crystal silicon wafer.
- porous silicon is a functional material of a sponge-like structure formed by electrochemical anodization of a single crystal silicon wafer.
- the characteristics of trapping carriers in the defect state of the porous silicon can be utilized to reduce the charge sharing effect caused by the heavy ions.
- the formation of the shallow trench isolation STI region and the lower isolation region requires only one photolithography, and the process is simple and can
- Figure 1 is a diagram showing the conventional isolation region cannot suppress the charge sharing effect under heavy ion radiation when heavy ions are incident on a small-sized conventional CMOS device
- Figure 2 shows the defect of an additional isolation region made of porous silicon when electrons are separated from the incident device by the addition of additional isolation regions made of porous silicon under the isolation region of the conventional CMOS device. Captured schematic;
- Fig. 3 is a cross-sectional view showing a CMOS device of the present invention for reducing the charge sharing effect in a radiation environment; and Figs. 4(a) to (f) are flow charts showing a method of fabricating a CMOS device according to an embodiment of the present invention.
- NMOS device when struck by heavy ions, a large number of electron-hole pairs are ionized in the direction of the heavy ion track, and the holes move toward the substrate, and a part of the electrons are heavily weighted.
- the ions are collected by the sensitive nodes of the device, and the other electrons are collected by diffusion from the isolation region of the device (such as the STI region) to the sensitive nodes of the surrounding devices. Therefore, by providing an additional isolation region 3 of porous silicon material under the device isolation region, electrons or holes can be trapped when diffused to surrounding devices, and the number of electron holes reaching the sensitive nodes of the surrounding devices can be reduced, thereby effectively suppressing charge sharing. The occurrence of an effect.
- the CMOS device of the present invention includes a substrate 1, an isolation region 4, an active region 5, a gate region 6, an LDD region 7, a gate spacer 8, a source region and a drain region 9, wherein, in the isolation region An additional isolation region 3 is provided directly below, and the material of the additional isolation region is porous silicon.
- the method for preparing the device of the present invention is further illustrated, which specifically includes the following steps:
- a P-type silicon wafer having a crystal orientation of (100) is provided as the substrate 1, and the front surface a thereof is chemically polished into a mirror surface. After a conventional cleaning process, aluminum film 2 is formed on the back surface b to form an aluminum film 2 as an ohmic contact, and at the same time in the aluminum film. Apply an acid protection layer as shown in Figure 4 (a);
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Description
Claims
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US13/582,034 US8652929B2 (en) | 2011-12-23 | 2012-04-16 | CMOS device for reducing charge sharing effect and fabrication method thereof |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201110436842.8 | 2011-12-23 | ||
CN201110436842.8A CN102522424B (zh) | 2011-12-23 | 2011-12-23 | 一种减小电荷共享效应的cmos器件及其制备方法 |
Publications (1)
Publication Number | Publication Date |
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WO2013091331A1 true WO2013091331A1 (zh) | 2013-06-27 |
Family
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Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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PCT/CN2012/074076 WO2013091331A1 (zh) | 2011-12-23 | 2012-04-16 | 一种减小电荷共享效应的cmos器件及其制备方法 |
Country Status (2)
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CN (1) | CN102522424B (zh) |
WO (1) | WO2013091331A1 (zh) |
Families Citing this family (2)
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CN102874746B (zh) * | 2012-10-11 | 2015-05-20 | 湖南文理学院 | 能提高多孔硅薄膜物理微结构及光学特性均匀性的方法 |
CN112530798A (zh) * | 2020-12-04 | 2021-03-19 | 广东省科学院半导体研究所 | 一种半导体结构及其制作、减薄方法 |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7091536B2 (en) * | 2002-11-14 | 2006-08-15 | Micron Technology, Inc. | Isolation process and structure for CMOS imagers |
CN102130058A (zh) * | 2010-01-19 | 2011-07-20 | 中芯国际集成电路制造(上海)有限公司 | Cmos晶体管及其制作方法 |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4282648A (en) * | 1980-03-24 | 1981-08-11 | Intel Corporation | CMOS process |
JP2778550B2 (ja) * | 1995-09-08 | 1998-07-23 | 日本電気株式会社 | 半導体集積回路の製造方法 |
US20050090073A1 (en) * | 2000-12-20 | 2005-04-28 | Actel Corporation, A California Corporation | MOS transistor having improved total radiation-induced leakage current |
CN101667576A (zh) * | 2009-09-30 | 2010-03-10 | 北京大学 | 一种新型抗nmos器件总剂量辐照的集成电路 |
CN101752376A (zh) * | 2009-12-18 | 2010-06-23 | 北京大学 | 一种新型的抗总剂量辐照的集成电路 |
-
2011
- 2011-12-23 CN CN201110436842.8A patent/CN102522424B/zh active Active
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2012
- 2012-04-16 WO PCT/CN2012/074076 patent/WO2013091331A1/zh active Application Filing
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7091536B2 (en) * | 2002-11-14 | 2006-08-15 | Micron Technology, Inc. | Isolation process and structure for CMOS imagers |
CN102130058A (zh) * | 2010-01-19 | 2011-07-20 | 中芯国际集成电路制造(上海)有限公司 | Cmos晶体管及其制作方法 |
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Publication number | Publication date |
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CN102522424B (zh) | 2014-04-30 |
CN102522424A (zh) | 2012-06-27 |
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