WO2011091656A1 - 一种抑制soi浮体效应的mos结构 - Google Patents

一种抑制soi浮体效应的mos结构 Download PDF

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WO2011091656A1
WO2011091656A1 PCT/CN2010/075141 CN2010075141W WO2011091656A1 WO 2011091656 A1 WO2011091656 A1 WO 2011091656A1 CN 2010075141 W CN2010075141 W CN 2010075141W WO 2011091656 A1 WO2011091656 A1 WO 2011091656A1
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Prior art keywords
region
floating body
suppressing
soi
heavily doped
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PCT/CN2010/075141
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English (en)
French (fr)
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陈静
罗杰馨
伍青青
黄晓橹
王曦
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中国科学院上海微系统与信息技术研究所
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Priority to US12/937,360 priority Critical patent/US20110291191A1/en
Publication of WO2011091656A1 publication Critical patent/WO2011091656A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78612—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device for preventing the kink- or the snapback effect, e.g. discharging the minority carriers of the channel region for preventing bipolar effect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/107—Substrate region of field-effect devices
    • H01L29/1075—Substrate region of field-effect devices of field-effect transistors
    • H01L29/1079—Substrate region of field-effect devices of field-effect transistors with insulated gate
    • H01L29/1087—Substrate region of field-effect devices of field-effect transistors with insulated gate characterised by the contact structure of the substrate region, e.g. for controlling or preventing bipolar effect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/66772—Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
    • H01L29/78621—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile
    • H01L29/78624—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile the source and the drain regions being asymmetrical

Definitions

  • the present invention relates to a MOS (Meta-Oxide Semiconductor) structure and a method of fabricating the same, and more particularly to a MOS structure capable of effectively suppressing a floating body effect of a SOI, and a method of fabricating the same, belonging to semiconductor manufacturing Technical field.
  • MOS Metal-Oxide Semiconductor
  • SOI Silicon l icon On Insulator
  • SOI Si l icon On Insulator
  • the device is only fabricated in a thin silicon film, and the device is separated from the substrate by a layer of buried oxide. This structure makes the S0I technology have advantages that are not comparable to bulk silicon.
  • the small parasitic capacitance makes the S0I device high speed and low power consumption.
  • the all-media isolation of SOI CMOS devices completely eliminates the parasitic latch-up effect of bulk silicon CMOS devices.
  • S0I full-medium isolation makes S0I technology highly integrated and resistant to radiation.
  • S0I technology is widely used in radio frequency, high voltage, anti-irradiation and other fields. As device sizes continue to shrink, S0I technology is likely to replace bulk silicon as the first choice for S0I technology.
  • the SOI M0S is divided into a partially depleted SOI MOS (PDS0I) and a fully depleted SOI MOS (FDS0I) depending on whether the active body region is depleted.
  • PDS0I partially depleted SOI MOS
  • FDS0I fully depleted SOI MOS
  • the fully depleted SO I M0S top silicon film will be thinner, and the thin film S0I silicon wafer is costly.
  • the fully depleted SOI M0S threshold voltage is not easy to control. Therefore, it is still generally used to partially exhaust SOI M0S.
  • the active body region of the partially depleted SOI MOS is not completely depleted, so that the body region is in a floating state, and the charge generated by the impact ionization cannot be quickly removed, which leads to the unique floating body effect of the SOI MOS.
  • the hole flows to the body region, and the SOI MOS floating body effect causes the holes to accumulate in the body region, thereby raising the body potential, making the SOI ⁇ OS
  • the decrease in the threshold voltage and the increase in the leakage current cause the device's output characteristic curve I d Vd to warp. This phenomenon is called the Kink effect.
  • the Kink effect has many adverse effects on device and circuit performance and reliability, and should be suppressed as much as possible during device design.
  • SOI PM0S due to the ionization rate comparison of holes Low, the electron-hole pair generated by impact ionization is much lower than SOI NM0S, so the Kink effect in SOI PM0S is not obvious.
  • the body is usually connected to a fixed potential (source or ground) by means of body contact, as shown in Figure la-lb, for the traditional T-gate structure.
  • the P + implant region formed at one end of the T-gate is connected to the P-type body region under the gate.
  • the carriers accumulated in the body region are vented through the P + channel to reduce the potential of the body region.
  • the negative effect is to complicate the process, increase the parasitic effect, reduce part of the electrical performance and increase the device area.
  • the present invention proposes a novel MOS structure in order to suppress the floating body effect in the SOI MOS device.
  • the technical problem to be solved by the present invention is to provide a MOS structure that effectively suppresses the S0I floating body effect and a related manufacturing method.
  • the present invention uses the following technical solutions:
  • a MOS structure for suppressing a SOI floating body effect comprising: a substrate, a buried insulating layer over the substrate, an active region above the buried insulating layer; the active region including a body region a first conductive type source region and a first conductive type drain region respectively located at two ends of the body region; a gate region is disposed above the body region, wherein: the active region further includes the first region a heavily doped second conductive type region between the conductive type source region and the buried insulating layer, the heavily doped second conductive type region and the first conductive type source region and the buried insulating layer respectively And the body regions are in contact.
  • the present invention also provides a method of forming the heavily doped second conductivity type region: performing ion implantation to a position of the first conductivity type source region by using a mask provided with an opening, so that the first conductivity type The lower portion of the source region and the region above the buried insulating layer form a heavily doped second conductivity type region.
  • the structure is characterized in that there is a heavily doped P-type region below the source region, and the heavily doped P region under the source region forms a tunnel junction with the heavily doped N-type source region, thereby pushing the voltage of the Kink of the SOI MOS to After the operating voltage, the floating body effect does not affect the operation of the device and does not increase the gate capacitance.
  • the invention not only increases the chip area, but also has the advantages that the manufacturing process is compatible with the conventional CMOS process while effectively suppressing the floating body effect.
  • FIG. 1a is a top plan view of a MOS structure for suppressing a floating body effect by a body contact method in the background art
  • Figure lb is a schematic cross-sectional view of the MOS structure for suppressing the floating body effect by the body contact method in the background art
  • FIG. 2 is a schematic cross-sectional view showing a MOSFET structure for suppressing a floating body effect according to the present invention
  • FIG. 3 is a schematic view showing a manufacturing method of a MOS structure for suppressing a floating body effect in the first embodiment
  • FIG. 4 is a schematic view showing a manufacturing method of a MOS structure for suppressing a floating body effect in the second embodiment
  • FIG. 5 is a schematic view of a MOS structure for suppressing a floating body effect in the third embodiment
  • Fig. 6 is an output characteristic curve I d Vd of the MOS structure of the present invention which effectively suppresses the floating body effect and the general MOS structure.
  • a MOS structure for suppressing a floating body effect includes: a substrate 100, a buried insulating layer 200 over the substrate 100, and an active layer over the buried insulating layer 200.
  • a shallow trench isolation (STI) structure 300 is disposed around the active region to isolate it.
  • the active region includes a body region 400, a first conductive type source region 401 and a first conductive type drain region 402 respectively located at the two ends of the body region 400; a gate region is disposed above the body region 400;
  • the active region further includes a heavily doped second conductive type region 403 between the first conductive type source region 401 and the buried insulating layer 200.
  • the heavily doped second conductive type region 403 is in contact with the first conductive type source region 401, the buried insulating layer 200, and the body region 400, respectively.
  • the gate region includes a gate dielectric layer 501 and a gate electrode 500 on the gate dielectric layer 501.
  • An insulator dielectric spacer isolation structure 502 is also disposed around the gate region.
  • the first conductivity type source region 401 is doped with a heavily doped N-type (N + ) semiconductor material; the first conductivity type drain region 402 is also doped with a heavily doped N-type (N + ) semiconductor material.
  • the heavily doped second conductivity type region 403 is heavily doped with a P-type (P + ) semiconductor material.
  • the body region 400 is made of a P-type semiconductor material.
  • the semiconductor material of the active region may be a material such as Si or Ge.
  • the buried insulating layer 200 is a buried oxide layer (BOX), that is, a silicon dioxide layer.
  • the method of forming the heavily doped second conductive type region 403 may be: opening a position of the first conductive type source region 401 through a mask (Ma sk ) to the first conductive type source region 401 The position is ion-implanted such that a region above the source region 401 and over the buried insulating layer 200 forms a heavily doped second conductivity type region 403.
  • a mask Mo sk
  • P-type ion implantation is used, and in the embodiment, boron ion implantation is performed, the implantation energy is 9Kev, and the dose is 3E15/cm 2 .
  • the N0 source region of the MOSFET structure for suppressing floating body effect disclosed in the present invention forms a PN junction with the P-type region below, the PN junction is heavily doped on both sides, the impurity concentration is large, and the barrier region is thin due to quantum mechanics. Tunneling, the PN junction is easy to form a tunnel junction.
  • the tunnel junction is different from the ordinary PN junction in that: the forward current of the tunnel junction rises rapidly with the increase of the forward voltage to a maximum value. The current at this time is mainly the tunnel current; then the voltage increases, and the current decreases. The reduction reaches a minimum value; then, in accordance with the normal PN junction, the forward current increases as the voltage increases.
  • the initial tunnel current can derive a portion of the charge accumulated by the SO I M0S floating body effect.
  • the body region of the SOI M0S still accumulates charges. Therefore, the structure can cause the voltage of the K ink to be pushed back by the SOI M0S. As long as the adjustment process can push the voltage of the K ink to the operating voltage of the SOI M0S, the floating body effect will not affect the operation of the device.
  • Embodiment 1 provides a method for fabricating a MOS structure that suppresses a floating body effect. As shown in FIG. 3, the method includes the following steps:
  • a shallow trench isolation structure 300 is formed on the semiconductor material having the buried insulating layer 200 (S0I or G0I, etc.), the active region is isolated, and P ion implantation is performed in the active region; then, a mask is added. The mask is opened at the position of the first conductivity type source region 401, and heavily doped P ion implantation is performed vertically through the mask to form a heavily doped P-type region; then the gate dielectric layer 501 and the gate electrode 500 are formed.
  • LDS source region light doping
  • LDD drain region light doping
  • N ion implantation Source region and drain region N ion implantation to form a first conductivity type source region 401 and a first conductivity type drain region 402, in which Forming the body region 400, the heavily doped P-type region between the first conductivity type source region 401 and the buried insulating layer 200 forms a heavily doped second conductivity type region 403.
  • An insulator dielectric spacer isolation structure 502 is also formed around the gate region.
  • This embodiment provides another method for fabricating a MIMO structure that suppresses the floating body effect. As shown in FIG. 4, the method includes the following steps:
  • a shallow trench isolation structure 300 is formed on the semiconductor material having the buried insulating layer 200 (S0I or G0I, etc.), the active region is isolated, and P ion implantation is performed in the active region; then the gate dielectric layer 501 is formed, The gate electrode 500 is light-doped (LDS) in the source region and lightly doped (LDD) in the drain region; then, a mask is added, and the mask is opened at the position of the source region 401 of the first conductivity type, via the mask The heavily doped P ion implantation is performed vertically to form a heavily doped P-type region under the lightly doped source region (LDS); finally, the source region and the drain region N ion implantation are performed to form the first conductivity type source region 401 and a first conductive type drain region 402, forming a body region 400 therebetween, and the heavily doped P-type region between the first conductive type source region 401 and the buried insulating layer 200 forms a heavily doped second conductive type region 4
  • This embodiment provides a third method of fabricating a MOSFET structure for suppressing a floating body effect.
  • the method forms a body region 400 on a semiconductor material having a buried insulating layer 200 (S0I or G0I, etc.), respectively.
  • the first conductive type source region 401 and the first conductive type drain at both ends of the body region 400
  • a mask is added, and the first layer is added via a mask.
  • the conductive type source region 401 is vertically ion-implanted such that a region above the source region 401 and a region above the buried insulating layer 200 forms a heavily doped second conductive type region 403.
  • FIG. 6 is a comparison chart of the I d -V d characteristic curve of the 0.1 ⁇ m device.
  • the dotted line in the figure shows the characteristic curve of the M0S device on the conventional SOI, and the obvious Kink effect can be seen, and the solid line indicates the present invention.
  • the characteristic curve of the M0S device on the S0I shows that the voltage at which the curve is warped is pushed to the operating voltage, that is, at the operating voltage of the device, the warpage is significantly reduced and the Kink effect is suppressed.

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Description

一种抑制 SOI浮体效应的 MOS结构 技术领域 本发明涉及一种 MOS ( Meta l Oxide Semiconductor )结构及其制作方法， 尤其是一种可以有效抑制 S0I浮体效应的 M0S结构及其制作方法， 属于半导 体制造技术领域。
背景技术
SOI (Si l icon On Insulator)是指绝缘体上硅技术。 在 S0I技术中， 器件 仅制造于表层很薄的硅膜中， 器件与衬底之间由一层隐埋氧化层隔开， 正是 这种结构使得 S0I 技术具有了体硅无法比拟的优点。 寄生电容电容小， 使得 S0I 器件拥有高速度和低功耗。 SOI CMOS 器件的全介质隔离彻底消除了体硅 CMOS器件的寄生闩锁效应， S0I全介质隔离使得 S0I技术集成密度高以及抗 辐照特性好。 S0I技术广泛应用于射频、 高压、 抗辐照等领域。 随着器件尺寸 的不断缩小， S0I技术极有可能替代体硅成为 S0I技术的首选。
SOI M0S根据有源体区是否耗尽分为部分耗尽 SOI MOS ( PDS0I )和全耗 尽 SOI MOS ( FDS0I ) 。 一般来说全耗尽 SO I M0S顶层硅膜会比较薄， 薄膜 S0I 硅片成本高， 另一方面全耗尽 SOI M0S 阔值电压不易控制。 因此目前普遍釆 用的还是部分耗尽 SOI M0S。
部分耗尽 SOI M0S 的有源体区并未完全耗尽， 使得体区处于悬空状态， 碰撞电离的产生的电荷无法迅速移走， 这会导致 SOI M0S特有的浮体效应。 对于 S0I 丽 OS沟道电子在漏端碰撞电离产生的电子-空穴对， 空穴流向体区， SOI M0S浮体效应导致空穴在体区积累， 从而抬高体区电势， 使得 S0I 丽 OS 的阔值电压降低继而漏电流增加， 导致器件的输出特性曲线 IdVd有翘曲现象， 这一现象称为 Kink效应。 Kink效应对器件和电路性能以及可靠性产生诸多不 利的影响， 在器件设计时应尽量抑制。 对 SOI PM0S , 由于空穴的电离率比较 低， 碰撞电离产生的电子-空穴对远低于 SOI NM0S , 因此 SOI PM0S中的 Kink 效应不明显。
为了解决部分耗尽 S0I 丽 OS, 通常釆用体接触（body contact)的方法将 "体" 接固定电位（源端或地） ， 如图 la-lb所示， 为传统 T型栅结构体接 触， 在 T型栅的一端形成的 P+注入区与栅下面的 P型体区相连， M0S器件工作 时， 体区积累的载流子通过 P+通道泄放， 达到降低体区电势的目的， 负面作 用是造成工艺流程复杂化， 寄生效应增加， 降低了部分电学性能并且增大了 器件面积。
鉴于此， 本发明为了抑制 SOI M0S 器件中的浮体效应， 提出一种新型的 M0S结构。
发明内容 本发明要解决的技术问题在于提供一种有效抑制 S0I浮体效应的 M0S结 构以及相关制作方法。
为了解决上述技术问题， 本发明釆用如下技术方案：
一种抑制 S0I浮体效应的 M0S结构， 包括： 衬底、 位于所述衬底之上的 埋层绝缘层、 位于所述埋层绝缘层之上的有源区； 所述有源区包括体区、 分 别位于所述体区两端的第一导电类型源区和第一导电类型漏区； 所述体区之 上设有栅区， 其特征在于： 所述有源区还包括位于所述第一导电类型源区与 所述埋层绝缘层之间的重掺杂第二导电类型区， 所述重掺杂第二导电类型区 分别与所述第一导电类型源区、 所述埋层绝缘层以及所述体区相接触。
本发明还提供一种形成所述重掺杂第二导电类型区的方法： 通过设有开 口的掩膜版向所述第一导电类型源区的位置进行离子注入， 使所述第一导电 类型源区下部、 埋层绝缘层之上的区域形成重掺杂第二导电类型区。
本结构的特点是在源区下方存在重掺杂的 P 型区， 源区下方的重掺杂 P 区与重掺杂的 N型源区形成隧道结， 从而使得 SOI M0S发生 Kink的电压推至 工作电压之后， 这样浮体效应不会影响器件的工作， 并且不会增加栅电容。 本发明在有效抑制浮体效应的同时， 还具有不会增加芯片面积， 制造工艺与 常规 CMOS工艺相兼容等优点。
附图说明 图 la 为背景技术中釆用体接触方法抑制浮体效应的 M0S 结构俯视示意 图；
图 lb 为背景技术中釆用体接触方法抑制浮体效应的 M0S 结构剖面示意 图；
图 2为本发明的抑制浮体效应的 M0S结构剖面示意图；
图 3为实施例一中抑制浮体效应的 M0S结构的制作方法示意图； 图 4为实施例二中抑制浮体效应的 M0S结构的制作方法示意图； 图 5为实施例三中抑制浮体效应的 M0S结构的制作方法示意图； 图 6为本发明的有效抑制浮体效应的 M0S结构以及普通 M0S结构的输出 特性曲线 IdVd。
具体实施方式 下面结合附图进一步说明本发明， 为了示出的方便附图并未按照比例绘 制。
如图 2所示， 一种抑制浮体效应的 M0S结构， 包括： 衬底 1 00、 位于所述 衬底 100之上的埋层绝缘层 200、位于所述埋层绝缘层 200之上的有源区； 所 述有源区周围设有浅沟槽隔离 （STI )结构 300将其隔离。 所述有源区包括体 区 400、分别位于所述体区 400两端的第一导电类型源区 401和第一导电类型 漏区 402 ; 在所述体区 400之上设有栅区； 所述有源区还包括位于所述第一导 电类型源区 401与所述埋层绝缘层 200之间的重掺杂第二导电类型区 403 ,所 述重掺杂第二导电类型区 403分别与所述第一导电类型源区 401、所述埋层绝 缘层 200以及所述体区 400接触。 所述栅区包括栅介质层 501和位于所述栅 介质层 501上的栅电极 500。在所述栅区周围还设有绝缘体介质侧墙隔离结构 502。
所述第一导电类型源区 401釆用重掺杂的 N型（N+ )半导体材料； 所述第 一导电类型漏区 402也釆用重掺杂的 N型（N+ )半导体材料。 所述重掺杂第二 导电类型区 403釆用重掺杂的 P型（P+ )半导体材料。 所述体区 400釆用 P型 半导体材料。 有源区的半导体材料可以是 S i或 Ge等材料。 所述埋层绝缘层 200为埋层氧化层（BOX ) , 即二氧化硅层。
形成所述重掺杂第二导电类型区 403 的方法可为： 通过掩膜版（Ma sk ) 在所述第一导电类型源区 401 的位置开口， 对所述第一导电类型源区 401 的 位置进行离子注入， 使源区 401下部、 埋层绝缘层 200之上的区域形成重掺 杂第二导电类型区 403。 对于丽 OS结构 （第一导电类型为 N型， 第二导电类 型为 P型），釆用 P型离子注入，实施例中釆用硼离子注入，注入能量为 9Kev , 剂量为 3E15/cm2。
本发明公开的这种抑制浮体效应的 M0S结构 N型源区与其下面的 P型区 形成 PN结， 该 PN结两边均为重掺杂， 杂质浓度大， 势垒区很薄， 由于量子 力学的隧道效应， PN结容易形成隧道结。隧道结与普通 PN结不同的地方在于： 隧道结的正向电流一开始就随正向电压的增加而迅速上升达到一个极大值， 这个时候的电流主要是隧道电流； 随后电压增加， 电流反而减小达到一个极 小值； 随后与普通 PN结一致正向电流随着电压的增加而增加。 对于本发明中 的隧道结， 一开始的隧道电流可以把 SO I M0S浮体效应积累的电荷导出去一 部分， 当隧道结的特性进入到普通 PN结区时， SOI M0S的体区还是会积累电 荷， 所以该结构可以使 SOI M0S发生 K ink的电压推后， 只要调节工艺可以使 SOI M0S发生 K ink的电压推至工作电压之后， 这样浮体效应就不会影响器件 的工作。
实施例一 本实施例提供一种制作抑制浮体效应的 M0S结构的方法， 如图 3所示， 包括如下步骤：
首先， 在具有埋层绝缘层 200的半导体材料上（ S0I或 G0I等）制作浅沟 槽隔离结构 300 , 隔离出有源区， 并在有源区进行 P离子注入； 然后， 增加一 道掩膜版， 掩膜版在第一导电类型源区 401 的位置开口， 经由掩膜版垂直地 进行重掺杂 P离子注入， 形成重掺杂的 P型区； 之后制作栅介质层 501、 栅电 极 500 , 进行源区轻掺杂（LDS ) 、 漏区轻掺杂（LDD ) , 最后进行源区、 漏区 N离子注入， 形成第一导电类型源区 401和第一导电类型漏区 402 , 在他们之 间形成体区 400 ,在第一导电类型源区 401和埋层绝缘层 200之间的重掺杂的 P型区形成重掺杂第二导电类型区 403。 在栅区周围还制作有绝缘体介质侧墙 隔离结构 502。
实施例二
本实施例提供另一种制作抑制浮体效应的 M0S结构的方法， 如图 4所示， 包括如下步骤：
首先， 在具有埋层绝缘层 200的半导体材料上（ S0I或 G0I等）制作浅沟 槽隔离结构 300 , 隔离出有源区， 并在有源区进行 P离子注入； 之后制作栅介 质层 501、 栅电极 500 , 进行源区轻掺杂（LDS )、 漏区轻掺杂（LDD )； 然后， 增加一道掩膜版， 掩膜版在第一导电类型源区 401 的位置开口， 经由掩膜版 垂直地进行重掺杂 P离子注入， 在轻掺杂的源区 （LDS ) 下方形成重掺杂的 P 型区； 最后进行源区、 漏区 N离子注入， 形成第一导电类型源区 401和第一 导电类型漏区 402 , 在他们之间形成体区 400 , 在第一导电类型源区 401和埋 层绝缘层 200之间的重掺杂的 P型区形成重掺杂第二导电类型区 403。在栅区 周围还制作有绝缘体介质侧墙隔离结构 502。
实施例三
本实施例提供第三种制作抑制浮体效应的 M0S结构的方法， 如图 5所示， 该方法在具有埋层绝缘层 200的半导体材料上（S0I或 G0I等）形成了体区 400、 分别位于所述体区 400两端的第一导电类型源区 401和第一导电类型漏 区 402、 以及位于所述体区 400之上的栅区 （栅介质层 501、 栅电极 500、 绝 缘体介质侧墙隔离结构 502 )之后， 增加一道掩膜版， 经由掩膜版对所述第一 导电类型源区 401垂直地进行离子注入， 使源区 401 下部， 埋层绝缘层 200 之上的区域形成重掺杂第二导电类型区 403。
为了分析本发明 M0S 结构的性能， 对该结构进行了仿真模拟， 模拟结果 显示本发明能有效抑制 S0I上 M0S结构的浮体效应。 图 6为 0. 13微米器件的 Id-Vd特性曲线对比图， 图中虚线表示的是传统 S0I上 M0S器件的特性曲线， 可以看到明显的 Kink效应， 而实线表示的是本发明 S0I上 M0S器件的特性曲 线， 可见曲线发生翘曲的电压推至工作电压之后， 也就是说在器件的工作电 压处， 翘曲度明显减小， Kink效应得到抑制。
本发明中涉及的其他技术属于本领域技术人员熟悉的范畴， 在此不再赘 精神和范围的技术方案均应涵盖在本发明的专利申请范围当中。

Claims

权利 要 求书
1. 一种抑制 SOI浮体效应的 MOS结构， 包括： 衬底、 位于所述衬底之上 的埋层绝缘层、 位于所述埋层绝缘层之上的有源区； 所述有源区包括 体区、 分别位于所述体区两端的第一导电类型源区和第一导电类型漏 区； 所述体区之上设有栅区， 其特征在于：
所述有源区还包括位于所述第一导电类型源区与所述埋层绝缘层 之间的重掺杂第二导电类型区， 所述重掺杂第二导电类型区分别与所 述第一导电类型源区、 所述埋层绝缘层以及所述体区相接触。
2. 根据权利要求 1所述一种抑制 S0I浮体效应的 M0S结构，其特征在于： 所述有源区周围设有浅沟槽隔离结构。
3. 根据权利要求 1所述一种抑制 S0I浮体效应的 M0S结构，其特征在于： 所述栅区包括栅介质层和位于所述栅介质层上的栅电极。
4. 根据权利要求 1所述一种抑制 S0I浮体效应的 M0S结构，其特征在于： 在所述栅区周围还设有绝缘体介质侧墙隔离结构。
5. 根据权利要求 1所述一种抑制 S0I浮体效应的 M0S结构，其特征在于： 所述第一导电类型源区釆用重掺杂的 N型半导体材料。
6. 根据权利要求 1所述一种抑制 S0I浮体效应的 M0S结构，其特征在于： 所述第一导电类型漏区釆用重掺杂的 N型半导体材料。
7. 根据权利要求 1所述一种抑制 S0I浮体效应的 M0S结构，其特征在于: 所述重掺杂第二导电类型区釆用重掺杂的 P型半导体材料。
8. 根据权利要求 1所述一种抑制 S0I浮体效应的 M0S结构，其特征在于: 所述体区釆用 P型半导体材料。 根据权利要求 1所述一种抑制 S0I浮体效应的 M0S结构，其特征在于 所述埋层绝缘层为埋层氧化层。
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