WO2013071650A1 - 一种减小辐射产生电荷收集的cmos器件及其制备方法 - Google Patents
一种减小辐射产生电荷收集的cmos器件及其制备方法 Download PDFInfo
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- WO2013071650A1 WO2013071650A1 PCT/CN2011/083244 CN2011083244W WO2013071650A1 WO 2013071650 A1 WO2013071650 A1 WO 2013071650A1 CN 2011083244 W CN2011083244 W CN 2011083244W WO 2013071650 A1 WO2013071650 A1 WO 2013071650A1
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- 230000005855 radiation Effects 0.000 title claims abstract description 15
- 238000002360 preparation method Methods 0.000 title abstract description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 28
- 230000004888 barrier function Effects 0.000 claims description 14
- 238000002513 implantation Methods 0.000 claims description 14
- 238000000034 method Methods 0.000 claims description 14
- 235000012239 silicon dioxide Nutrition 0.000 claims description 14
- 239000000377 silicon dioxide Substances 0.000 claims description 14
- 238000005530 etching Methods 0.000 claims description 12
- 239000000758 substrate Substances 0.000 claims description 12
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 11
- 238000000151 deposition Methods 0.000 claims description 11
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 11
- 239000012535 impurity Substances 0.000 claims description 10
- 238000002955 isolation Methods 0.000 claims description 9
- 230000001629 suppression Effects 0.000 claims description 9
- 239000000463 material Substances 0.000 claims description 8
- 125000006850 spacer group Chemical group 0.000 claims description 8
- 230000000694 effects Effects 0.000 claims description 6
- 238000000137 annealing Methods 0.000 claims description 5
- 238000004519 manufacturing process Methods 0.000 claims description 5
- 238000000206 photolithography Methods 0.000 claims description 5
- 239000004065 semiconductor Substances 0.000 claims description 4
- 230000004913 activation Effects 0.000 claims description 3
- 238000004140 cleaning Methods 0.000 claims description 3
- 239000003989 dielectric material Substances 0.000 claims description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 3
- 229920005591 polysilicon Polymers 0.000 claims description 3
- 238000005468 ion implantation Methods 0.000 claims description 2
- 239000002184 metal Substances 0.000 claims description 2
- 239000002245 particle Substances 0.000 abstract description 12
- 230000001052 transient effect Effects 0.000 abstract description 7
- 230000005684 electric field Effects 0.000 abstract description 6
- 230000009471 action Effects 0.000 abstract description 5
- 230000003247 decreasing effect Effects 0.000 abstract 1
- 150000002500 ions Chemical class 0.000 description 7
- 230000015572 biosynthetic process Effects 0.000 description 5
- 230000008569 process Effects 0.000 description 5
- 238000009792 diffusion process Methods 0.000 description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 238000003860 storage Methods 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 208000033999 Device damage Diseases 0.000 description 1
- 230000002159 abnormal effect Effects 0.000 description 1
- 230000003471 anti-radiation Effects 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 230000005764 inhibitory process Effects 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 230000000191 radiation effect Effects 0.000 description 1
- 238000005215 recombination Methods 0.000 description 1
- 230000006798 recombination Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000005728 strengthening Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/6653—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using the removal of at least part of spacer, e.g. disposable spacer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/107—Substrate region of field-effect devices
- H01L29/1075—Substrate region of field-effect devices of field-effect transistors
- H01L29/1079—Substrate region of field-effect devices of field-effect transistors with insulated gate
- H01L29/1083—Substrate region of field-effect devices of field-effect transistors with insulated gate with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
Definitions
- CMOS device for reducing radiation generated charge collection and preparation method thereof
- Embodiments of the present invention relate to a COMS device, and in particular to a CMOS device that reduces radiation generated charge collection and a method of fabricating the same. Background technique
- the single particle effect means that when a high-energy charged particle in a radiation environment passes through a sensitive region of an integrated circuit component, a large number of electron-hole pairs deposited in the track are collected under the electric field of the semiconductor pn junction depletion layer, resulting in a device logic state. Abnormal changes or device damage. The charge collected therein will have a voltage transient at the circuit node. This phenomenon is called a single-particle transient.
- Single-event transients if they occur at the output stage of the circuit, cause an error in the output; if it occurs in a storage element, it causes the storage contents to flip; even in a logic circuit, a single particle propagates along the logic and is in the propagation process. The broadening effect occurs, which increases the probability that a single particle will cause an integrated circuit to fail.
- the leakage junction is usually reverse biased, so the leakage junction of the component is considered to be a sensitive node for collecting charge by single-particle transient. Reducing the number of charges collected by sensitive nodes of integrated circuit components under radiation environment is of great significance for studying anti-radiation strengthening circuits.
- Figure 1 is a schematic diagram of a sensitive node of a charged heavy ion passing through a component.
- a is the depletion region
- b is the "funnel" region
- c is the electron-hole pair generated along the ion trajectory
- d is the ion trajectory.
- Charge generation Charged ions are incident on the semiconductor. Due to the high energy of the ions, a large number of electron-hole pairs are generated along the ion track.
- Instantaneous collection also known as funnel collection: The large number of electron-hole pairs generated will cause the depletion region of the original pn junction to occur. The distortion, the isostatic potential of the depletion zone deforms to form a shape similar to a "funnel". The electron-hole pairs in the funnel begin to drift in different directions under the action of the electric field in the depletion region and are collected by the electrodes. This process is generally only a few tens to hundreds of ps, so it is called “instantaneous collection.”
- Diffusion collection The electron-hole pairs outside the depletion region will diffuse due to the concentration difference. If the diffusion enters the reverse biased pn junction, it is again collected by the electrode under the action of the electric field in the depletion region. Since there is no electric field, most of the recombination is lost, and the charge collected by the diffusion is not dominant in the charge collected by the single-particle transient.
- the drain region of the device is typically a sensitive node in a radiated environment. Since the substrate is lightly doped with respect to the drain region, the "funnel" range of single-event transients is large, and the size of the "funnel" region is a key factor in the amount of charge collected by the sensitive nodes. Summary of the invention
- embodiments of the present invention provide a device for reducing single-event transient charge collection in a radiation environment.
- a CMOS device includes a substrate, a device isolation region, a gate region, a source region, a drain region, and an LDD region, wherein a heavily doped suppressed charge collection region is disposed directly under the source region and the drain region, the region The doping type is opposite to the doping type of the source and drain regions.
- the doping concentration of the charge collection region is suppressed to be not less than the doping concentration of the source region and the drain region.
- the lateral extent of the suppressed charge collection region is slightly less than or equal to the lateral extent of the source and drain regions, and the lateral position to the channel does not exceed the edges of the source and drain regions.
- Another object of embodiments of the present invention is to provide a method of fabricating a CMOS device that reduces radiation generated charge collection.
- a gate dielectric such as silicon dioxide or a high-k material is deposited, and a gate electrode, such as polysilicon or metal, is deposited, and a gate pattern is formed by photolithography, and a gate electrode and a gate dielectric material are formed outside the etched pattern.
- the LDD region is implanted to form an LDD region;
- the implantation depth is smaller than the implantation depth of the heavily doped suppression charge collection region, and the doping type is opposite to the doping type of the suppression charge collection region, and rapid annealing is employed. Techniques are used to effect impurity activation to form source and drain regions.
- the heavily doped region exists simultaneously under the source and drain regions of the CMOS device. In order to avoid channel floating caused by the presence of the source and drain heavily doped regions, the lateral extent of the heavily doped region to the channel must be slightly less than or equal to the range of the source and drain regions.
- a heavily doped region is added directly below the source and drain regions of a conventional CMOS device.
- the doping type of the region is opposite to the doping type at the sensitive node, and the doping concentration is not less than the doping concentration of the source region and the drain region.
- the impurity implantation depth of the charge collection region in order to ensure that the charge collection region is located directly under the source region and the drain region of the CMOS device, it is necessary to control the impurity implantation depth of the charge collection region to be larger than the impurity implantation depth of the source region and the drain region. In order to prevent the charge collection region from being located just below the source and drain regions, the problem of lateral diffusion of impurities occurring when annealing to activate the impurity is prevented.
- the edge of the charge collection region is suppressed from exceeding the source region and the drain region, and the regrowth is generated after the gate spacer is formed.
- a barrier layer then suppress the charge Injecting the collector, etching the barrier layer and then implanting the source and drain regions, so that the impurity implantation depth of the source and drain regions is less than the impurity implantation depth of the charge collection region, and the source region and the drain region are trenched.
- the lateral position of the track is greater than the lateral position of the suppressed charge collection region.
- the lateral distance extending from the charge trapping region to the channel is slightly less than or equal to the lateral distance of the source and drain regions to the channel, ie, the charge collection region is located just in the source and drain regions. Directly below, and the lateral position to the channel does not exceed the edges of the source and drain regions.
- Figure 1 is a schematic diagram of a charged heavy ion passing through a sensitive node of a component
- FIG. 2 is a cross-sectional view of a CMOS device according to an embodiment of the present invention.
- 3(a) through 3(f) are cross-sectional views showing the flow of a method of fabricating a COMS device in accordance with one embodiment of the present invention. detailed description
- the CMOS device according to the embodiment includes a substrate 1, a device isolation region 2, a gate region 4, a gate spacer 6, a source region, and The drain region 12 and the LDD region 11 are in which the charge trapping region 9 is added directly under the source and drain regions.
- Substrate preparation lightly doped P-type silicon with a crystal orientation of (100) is used as the substrate 1 with a doping concentration of 10 15 ⁇ 10 16 cm - 3 ;
- a layer of silicon dioxide is thermally grown on the substrate 1 as a buffer layer, a layer of silicon nitride is deposited, and then a photolithographic technique is used to leave the isolation region, and the reactive ion etching silicon nitride. And performing isolation region implantation, depositing silicon dioxide and a barrier layer, and chemically mechanically planarizing CMP to planarize the surface to form a device isolation region 2, as shown in FIG. 3(a);
- a gate region and an LDD region after cleaning, the gate oxide layer 3 is grown and polysilicon is deposited as the gate electrode 4, and a gate pattern is formed by photolithography, and a gate electrode and a gate dielectric material outside the pattern are formed to form a gate region of the MOSFET.
- Impurity injection 5 is performed in the LDD region using phosphorus, and the implantation concentration is 10 18 ⁇ to form the LDD region 11, as shown in Fig. 3 (b);
- Gate sidewall formation deposition of silicon dioxide, anisotropic etching of silicon dioxide to form the gate spacer 6, as shown in Figure 3 (c)
- P-type heavily doped region formation depositing a layer of silicon nitride, anisotropic etching to form a barrier side wall 7, as shown in Figure 3 (d);
- Source and drain regions Formation of source and drain regions: etching the barrier sidewall spacer 7, using source and drain regions 10 implanted with phosphorus, implanting a concentration of 10 19 cm - 3 , and implanting a depth smaller than that of the P-type heavily doped region The implantation depth of the suppression region is collected, and rapid annealing technique is employed to effect impurity activation to form source and drain regions 12, as shown in Fig. 3(f).
- the embodiments described above are not intended to limit the invention, and various modifications and changes can be made thereto without departing from the spirit and scope of the invention. Defined.
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US13/509,170 US8877594B2 (en) | 2011-11-14 | 2011-11-30 | CMOS device for reducing radiation-induced charge collection and method for fabricating the same |
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CN201110359705.9A CN102386186B (zh) | 2011-11-14 | 2011-11-14 | 一种减小辐射产生电荷收集的cmos器件及其制备方法 |
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CN113540207B (zh) * | 2021-06-04 | 2022-07-22 | 复旦大学 | 一种基于B掺杂扩散进行寿命控制的辐射加固SiC器件 |
CN113471275B (zh) * | 2021-06-23 | 2022-08-23 | 长江存储科技有限责任公司 | 半导体器件及其制备方法 |
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US20050093032A1 (en) * | 2003-11-05 | 2005-05-05 | Texas Instruments, Incorporated | Transistor having a germanium implant region located therein and a method of manufacture therefor |
US7250332B2 (en) * | 2004-08-19 | 2007-07-31 | United Microelectronics Corp. | Method for fabricating a semiconductor device having improved hot carrier immunity ability |
US7271079B2 (en) * | 2005-04-06 | 2007-09-18 | International Business Machines Corporation | Method of doping a gate electrode of a field effect transistor |
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US8569837B2 (en) * | 2007-05-07 | 2013-10-29 | Taiwan Semiconductor Manufacturing Company, Ltd. | MOS devices having elevated source/drain regions |
US7745847B2 (en) * | 2007-08-09 | 2010-06-29 | United Microelectronics Corp. | Metal oxide semiconductor transistor |
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US20050093032A1 (en) * | 2003-11-05 | 2005-05-05 | Texas Instruments, Incorporated | Transistor having a germanium implant region located therein and a method of manufacture therefor |
US7250332B2 (en) * | 2004-08-19 | 2007-07-31 | United Microelectronics Corp. | Method for fabricating a semiconductor device having improved hot carrier immunity ability |
US7271079B2 (en) * | 2005-04-06 | 2007-09-18 | International Business Machines Corporation | Method of doping a gate electrode of a field effect transistor |
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