WO2014026497A1 - 一种抗辐射的cmos器件及其制备方法 - Google Patents

一种抗辐射的cmos器件及其制备方法 Download PDF

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WO2014026497A1
WO2014026497A1 PCT/CN2013/076745 CN2013076745W WO2014026497A1 WO 2014026497 A1 WO2014026497 A1 WO 2014026497A1 CN 2013076745 W CN2013076745 W CN 2013076745W WO 2014026497 A1 WO2014026497 A1 WO 2014026497A1
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vertical channel
silicon dioxide
layer
substrate
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黄如
谭斐
安霞
武唯康
黄良喜
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北京大学
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    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
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    • H01L29/66409—Unipolar field-effect transistors
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Definitions

  • the invention belongs to the technical field of CMOS integrated circuits, and particularly relates to a radiation resistant CMOS device and a preparation method thereof. Background technique
  • CMOS integrated circuits are composed of conventional bulk silicon devices.
  • conventional bulk silicon devices with the further thinning of the gate oxide layer, the effect of the charge generated by the irradiation source in the gate oxide layer on the device performance is negligible, but the charge trapped in the STI region causes the parasitic transistor to turn on. Affect the normal operation of the device.
  • ions entering the sensitive nodes of the conventional bulk silicon device may cause a relatively serious single-particle effect, resulting in abnormal changes in the logic state of the device or device damage.
  • the object of the present invention is to overcome the problems in the prior art and to provide a novel vertical channel CMOS device capable of resisting single-particle radiation and total dose radiation in a radiation environment, while also suppressing device spacing. Reduce the charge sharing effect caused by the reduction.
  • the CMOS device of the present invention comprises a substrate, a source region, a drain region, and a vertical channel on the substrate, and a source region is disposed above the vertical channel, and the drain region is disposed on the substrate on the vertical channel.
  • a drain region is disposed above the vertical channel, the source region is disposed on the substrate on both sides of the vertical channel, and the gate dielectric and the gate spacer are disposed on both sides of the vertical channel, wherein Adding a dielectric protection zone 1 in the vertical channel, the dielectric protection zone is located in the center of the vertical channel, and divides the vertical channel into two parts.
  • the height of the dielectric protection zone 1 is equal to the vertical channel length, and the active silicon is used.
  • the center axis of the medium is centered, and the edge of the dielectric protection zone is 20 to 100 nm from the outside of the channel; at the same time, a dielectric protection zone 2 is provided below the source or drain region on the substrate, and the length and source region of the dielectric protection zone 2 are Or the length of the drain region is equal, and the height of the dielectric protection region 2 is 10 to 50 nm.
  • the material used in the dielectric protection area is a material that is easily trapped in electrons, such as silicon nitride.
  • the material used in the dielectric protection zone is a material that is easily trapped in holes, such as silicon dioxide.
  • the method of the present invention for preparing a novel vertical channel CMOS device based on a bulk silicon substrate comprises the following steps:
  • the material used in the dielectric protection zone is a material that is easily trapped in electrons, such as silicon nitride.
  • the material used in the dielectric protection region is a material that is easily trapped in holes, such as silicon dioxide or the like, which is planarized and etched to form a dielectric protection region; 7) cleaning, depositing a layer of polysilicon, planarizing;
  • a dielectric protection region in the semiconductor platform effectively blocks the source and drain regions of the device from collecting charge. The path, thus improving the single-particle nature of the device.
  • the insulating layer existing under the source and drain regions of the device can effectively block the diffusion of electrons and holes by high-energy ionization.
  • the top of the device is a drain and the bottom is used as a source, when the device is working normally, the electrons and holes generated by the high-energy charged particles passing through the drain (the sensitive node during normal operation of the device) are trapped by the adjacent device.
  • the collection needs to pass through a distance between an STI region and two source regions. During the diffusion process, electrons and holes are largely recombined, thus improving the charge sharing effect under the action of single particles.
  • FIG. 1 is a cross-sectional view of a CMOS device proposed by the present invention
  • 2(a) to 2(q) are schematic flow charts showing a method of fabricating a CMOS device of the present invention. detailed description
  • etching the active region silicon wafer first thermally oxidizing a thin layer of silicon dioxide 2a on the substrate, followed by low pressure chemical vapor deposition (LPCVD) of a layer of silicon nitride 3a, and then LPCVD-layer silicon dioxide 4a, such as Figure 2 (a); photolithography, reactive ion etching (RIE) silicon dioxide 4a, RIE etching silicon nitride 3a, hydrofluoric acid etching silicon dioxide 2a, etching silicon dioxide 4a and nitriding There is a small step between the silicon 3a; inductively coupled plasma (ICP) etches the silicon substrate 1 to form an active region silicon station, as shown in Fig. 2(b) ;
  • ICP inductively coupled plasma
  • Source and drain region formation third etching of active silicon region, LPCVD-layer silicon dioxide 11, LPCVD-layer silicon nitride 12, lithography silicon pattern, RIE etching silicon oxide 11 and nitrogen Silicon 12, with silicon dioxide 11 and silicon nitride 12 as a barrier layer, ICP etching polysilicon 10 and silicon nitride 9, as shown in Figure 2 (n) ; implanting n-type impurity ions;

Abstract

本发明公开了一种抗辐射的CMOS器件及其制备方法，属于CMOS集成电路技术领域。该CMOS器件包括衬底、源区、漏区以及位于衬底上的垂直沟道，在垂直沟道内增加一介质保护区一，该介质保护区一位于垂直沟道中央，将垂直沟道分为两部分，所述介质保护区一的高度等于垂直沟道长度，以有源硅台中轴线为中心，介质保护区一的边缘距离沟道外侧为20〜100nm；同时在衬底上的源区或漏区的下方设有介质保护区二，该介质保护区二的长度与源区或漏区的长度相等，所述介质保护区二的高度为10〜50nm。本发明由于增加介质保护区，可有效隔断器件源区和漏区收集电荷的路径，改善了器件的单粒子特性。

Description

一种抗辐射的 CMOS器件及其制各方法 相关申请的交叉引用
本申请要求于 2012年 8月 14日提交的中国专利申请 （201210289276.7) 的优先 权， 其全部内容通过引用合并于此。 技术领域
本发明属于 CMOS集成电路技术领域， 具体涉及一种抗辐射的 CMOS器件及其 制备方法。 背景技术
信息技术的高速发展和广泛应用改变了传统的生产、 经营、 管理和生活方式， 对 人类社会的各方面都带来了深刻的影响。 随着科学技术的发展， 特别是空间技术、 核 动力及核武器的发展， 核辐射环境与电子技术的关系越来越密切。为了满足航天技术 的发展对集成电路抗辐照性能的要求，卫星和宇宙飞船的某些关键核心集成电路需要 使用抗辐照加固器件。因此航天事业的发展和宇宙探索的进步，促使研究者们深入研 究空间自然辐射环境对集成电路性能的影响， 并寻找可行的加固方法。
目前关于 CMOS集成电路辐照效应的研究， 主要集中在总剂量效应、 单粒子效 应的研究上。 目前， 主流的 CMOS集成电路是由传统体硅器件构成。 在传统体硅器 件中， 随着栅氧化层的进一步减薄， 辐照源在栅氧化层中产生的电荷对器件性能的影 响可以忽略不计，但是 STI区陷入的电荷会引起寄生晶体管的打开， 影响器件的正常 工作。另外由于硅衬底中电荷收集区较大， 离子入射传统体硅器件的敏感节点时会引 发比较严重的单粒子效应， 造成器件逻辑状态的非正常改变或器件损坏。 另外， 随着 器件尺寸的不断缩小，传统体硅器件间的间距不断变小， 一个高能离子的入射会引起 多个平面体硅器件能同时收集电荷， 即出现电荷共享效应， 电荷共享效应会造成集成 电路多个节点同时发生翻转， 增大翻转横截面， 降低发生翻转所需要的能量阈值。此 外， 电荷共享效应会造成如保护环等器件级和电路级的抗辐射加固技术的失效。
为了改善传统体硅器件的抗辐射性能， 一些新的器件结构逐渐被提出和发展。但 是这些新型器件结构往往只能完成单一的抗辐射指标，不能同时兼顾满足即抗总剂量 辐射又抗单粒子辐射的要求， 同时也没有考虑小尺寸引起的电荷共享效应。 因此， 研 究即抗总剂量辐射又抗单粒子辐射同时抑制电荷共享效应的新弄抗辐射器件结构就 显得十分有价值。 发明内容
本发明的目的在于克服现有技术中存在的问题， 提出一种新型垂直沟道 CMOS 器件， 使之在辐射环境中能够即抗单粒子辐射又能抗总剂量辐射， 同时还要以抑制器 件间距缩小引起的电荷共享效应。
本发明的 CMOS器件包括衬底、 源区、 漏区以及位于衬底上的垂直沟道， 在垂 直沟道的上方设有源区，所述漏区设置在衬底上位于垂直沟道的两侧； 或者在垂直沟 道的上方设有漏区，所述源区设置在衬底上位于垂直沟道的两侧，在垂直沟道的两侧 设有栅介质和栅侧墙， 其特征在于， 在垂直沟道内增加一介质保护区一， 该介质保护 区一位于垂直沟道中央，将垂直沟道分为两部分，所述介质保护区一的高度等于垂直 沟道长度， 以有源硅台中轴线为中心， 介质保护区一的边缘距离沟道外侧为 20〜 lOOnm; 同时在衬底上的源区或漏区的下方设有介质保护区二， 该介质保护区二的长 度与源区或漏区的长度相等， 所述介质保护区二的高度为 10〜50nm。
对于 NMOS器件， 介质保护区使用的材料为易陷入电子的材料， 如氮化硅等。 对于 PMOS器件， 介质保护区使用的材料为易陷入空穴的材料， 如二氧化硅等。
本发明制备基于体硅衬底的新型垂直沟道 CMOS器件的方法包括以下步骤：
1 ) 准备半导体衬底；
2) 在衬底热氧化一薄层二氧化硅， 再淀积一层氮化硅和一层二氧化硅。 光刻， 刻蚀掉二氧化硅和氮化硅， 再腐蚀二氧化硅，刻蚀后使第一层的二氧化硅与氮化硅存 在微小的台阶； 刻蚀半导体衬底， 形成半导体台阶；
3 ) 再次热氧化一薄层二氧化硅， 淀积一层氮化硅和一层二氧化硅， 刻蚀后， 局 部场区氧化形成器件隔离区；
4) 淀积二氧化硅作为缓冲层， 多次多能量进行离子注入， 使沟道中离子浓度分 布均匀；
5 ) 淀积氮化硅层和二氧化硅层后， 以氮化硅和二氧化硅为硬掩膜， 第二次刻蚀 有源区半导体台阶；
6)淀积介质保护区材料， 对于 NMOS器件， 介质保护区使用的材料为易陷入电 子的材料， 如氮化硅等。 对于 PMOS器件， 介质保护区使用的材料为易陷入空穴的 材料， 如二氧化硅等平坦化后刻蚀， 形成介质保护区； 7) 清洗， 淀积一层多晶硅， 平坦化；
8) 第三次刻蚀有源区半导体平台， 离子注入形成器件的源漏区；
9) 热氧化一层二氧化硅， 淀积一层多晶硅， 离子注入光刻栅线条， 刻蚀后形成 多晶硅栅电极和栅侧墙。
本发明的优越性如下：
1 ) 在辐射环境中， 如果高能离子入射顶部的源区 （或漏区） 或底部的漏区 （或 源区）， 半导体平台中存在介质保护区有效隔断了器件源区和漏区收集电荷的路径， 因此改善了器件的单粒子特性。
2) 由于器件的沟道和器件隔离氧化层隔离， 即使隔离氧化层陷入足够的电荷， 但仍不能在垂直沟道中产生寄生的晶体管， 因此改善了器件的总剂量特性。
3 ) 器件的源区和漏区下方存在的绝缘层可以有效阻挡高能离子电离产生电子和 空穴的扩散。 另外， 如果器件顶部为漏区， 底部用作源区时， 器件正常工作时， 高能 带电粒子穿过漏区（器件正常工作时的敏感节点）产生的电子和空穴如果被临近器件 的漏区收集， 需要经过一个 STI区和两个源区的距离，在扩散过程中电子和空穴大量 复合， 因此改善了单粒子作用下的电荷共享效应。 附图说明
图 1为本发明提出的 CMOS器件的剖面图；
图 2 (a) 至图 2 (q) 为本发明 CMOS器件的制备方法的流程示意图。 具体实施方式
下面结合附图以 NMOS为例详细说明本发明的实施方式， 其中介质保护区材料 采用氮化硅。
1 ) 备片： 准备 P型 （100) 硅衬底 1 ;
2) 刻蚀有源区硅台： 先在衬底热氧化一薄层二氧化硅 2a， 再低压化学气相淀积 (LPCVD) 一层氮化硅 3a， 然后 LPCVD—层二氧化硅 4a， 如图 2 (a); 光刻， 反 应离子刻蚀（RIE)二氧化硅 4a， RIE刻蚀氮化硅 3a， 氢氟酸腐蚀二氧化硅 2a， 使刻 蚀后的二氧化硅 4a与氮化硅 3a间存在微小的台阶； 电感耦合等离子体 （ICP) 刻蚀 硅衬底 1， 形成有源区硅台， 如图 2 (b);
3 )形成器件隔离区： 再次热氧化一薄层二氧化硅 2b，再 LPCVD—层氮化硅 3b， 然后 LPCVD—层二氧化硅 4b，如图 2 (c); RIE二氧化硅 4b， RIE场区的氮化硅 3b， 如图 2 (d); 腐蚀淀积的二氧化硅 4a， 4b, 2b, 有源区硅台的台面和侧壁都完全被氮 化硅保护， 如图 2 (e) 所示； 局部场区氧化形成隔离区 5， 如图 2 (0; 腐蚀掉氮化 硅 3a， 3b, 二氧化硅 2a， 2b, 如图 2 (g);
4)沟道杂质注入： LPCVD二氧化硅 6作为缓冲层， 注入 p型杂质离子， 如图 2 (h);
5 ) 有源区硅台第二次刻蚀： LPCVD氮化硅 8， 光刻出硅台图形， RIE刻蚀二氧 化硅 6和氮化硅 8， 如图 2 (1)； 以氮化硅 8和二氧化硅 6为硬掩膜， ICP刻蚀硅 1 和 7， 如图 2 (j );
6) 形成阻挡层： LPCVD氮化硅 9， 化学机械抛光 （CMP)， 如图 （k); 光刻出 底部源 （或漏） 区图形， RIE刻蚀氮化硅 9， 如图 2 (1)；
7)形成源漏多晶硅： 清洗， LPCVD—层多晶硅 10， 化学机械抛光 （CMP)， 如 图 2 (m);
8)源漏区形成： 有源区硅台第三次刻蚀， LPCVD—层二氧化硅 11， LPCVD— 层氮化硅 12， 光刻出硅台图形， RIE刻蚀二氧化硅 11和氮化硅 12， 以二氧化硅 11 和氮化硅 12为阻挡层， ICP刻蚀多晶硅 10和氮化硅 9， 如图 2 (n); 注入 n型杂质 离子；
9) 栅氧及栅侧墙的形成： 热氧化一层二氧化硅 13， LPCVD—层多晶硅 14， 如 图 2 (o); 光刻栅线条， 刻蚀多晶硅 14， 二氧化硅 13， 形成多晶硅栅电极 14和栅侧 墙 13， 如图 2 (p); 平坦化， 去除硅台顶层源漏区上方的二氧化硅 11， 氮化硅 12， 二氧化硅 13， 如图 2 (q)。
最后需要注意的是， 公布实施方式的目的在于帮助进一步理解本发明， 但是本领 域的技术人员可以理解： 在不脱离本发明及所附的权利要求的精神和范围内，各种替 换和修改都是可能的。 因此， 本发明不应局限于实施例所公开的内容， 本发明要求保 护的范围以权利要求书界定的范围为准。

Claims

权 利 要 求
1. 一种 CMOS器件， 包括衬底、 源区、 漏区以及位于衬底上的垂直沟道， 在垂直沟道的上方设有源区， 所述漏区设置在衬底上位于垂直沟道的两侧； 或者 在垂直沟道的上方设有漏区， 所述源区设置在衬底上位于垂直沟道的两侧； 在垂 直沟道的两侧设有栅介质和栅侧墙， 其特征在于， 在垂直沟道内增加一介质保护 区一， 该介质保护区一位于垂直沟道中央， 将垂直沟道分为两部分， 所述介质保 护区一的高度等于垂直沟道长度， 以有源硅台中轴线为中心， 介质保护区一的边 缘距离沟道外侧为 20〜100nm;同时在衬底上的源区或漏区的下方设有介质保护 区二， 该介质保护区二的长度与源区或漏区的长度相等， 所述介质保护区二的高 度为 10〜50nm。
2. 如权利要求 1所述的 CMOS器件， 其特征在于， 对于 NMOS器件， 介质 保护区使用的材料为易陷入电子的材料； 对于 PMOS器件， 介质保护区使用的 材料为易陷入空穴的材料。
3. 如权利要求 1所述的 CMOS器件的方法， 包括以下步骤：
1 ) 准备半导体衬底；
2) 在衬底热氧化形成第一二氧化硅层， 再淀积第一氮化硅层和第二二氧化 硅层； 光刻、 刻蚀掉第二二氧化硅层和第一氮化硅层， 再腐蚀第一二氧化硅层， 刻蚀后使第一二氧化硅层与第一氮化硅层存在微小的台阶； 刻蚀半导体衬底， 形 成半导体台阶；
3 ) 再次热氧化形成第三二氧化硅层， 淀积形成第二氮化硅层和第四二氧化 硅层， 刻蚀、 局部场区氧化， 形成器件隔离区；
4) 淀积第五二氧化硅层作为缓冲层， 进行离子注入， 使沟道中离子浓度分 布均匀；
5 ) 淀积第三氮化硅层和第六二氧化硅层后， 以第三氮化硅层和第六二氧化 硅层为硬掩膜， 第二次刻蚀有源区半导体台阶；
6) 淀积介质保护区材料并刻蚀；
7) 淀积第一多晶硅层， 平坦化；
8) 第三次刻蚀有源区半导体平台， 离子注入， 形成器件的源漏区；
9) 热氧化第七二氧化硅层， 淀积第二多晶硅层， 离子注入， 光刻栅线条， 刻蚀后形成多晶硅栅电极和栅侧墙 c
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Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102769016B (zh) * 2012-08-14 2015-01-14 北京大学 一种抗辐射的cmos器件及其制备方法
CN103219384B (zh) * 2013-04-03 2015-05-20 北京大学 一种抗单粒子辐射的多栅器件及其制备方法
CN104078509A (zh) * 2014-07-08 2014-10-01 电子科技大学 一种具有抗单粒子烧毁能力的功率mos器件
CN106331541B (zh) * 2016-09-18 2019-06-21 首都师范大学 可收集寄生光生电荷的图像传感器
US10347745B2 (en) * 2016-09-19 2019-07-09 Globalfoundries Inc. Methods of forming bottom and top source/drain regions on a vertical transistor device
US10546857B2 (en) * 2017-02-16 2020-01-28 International Business Machines Corporation Vertical transistor transmission gate with adjacent NFET and PFET
CN110034069B (zh) * 2018-01-11 2020-12-01 中芯国际集成电路制造(上海)有限公司 半导体结构及其形成方法
CN108511402B (zh) * 2018-05-31 2019-12-06 西北核技术研究所 基于温度的cmos工艺器件抗辐射加固方法
CN111341663A (zh) * 2020-03-12 2020-06-26 上海华虹宏力半导体制造有限公司 射频器件的形成方法
CN111987152B (zh) * 2020-09-09 2024-01-26 电子科技大学 一种抗辐照双栅ldmos器件结构
CN112345795A (zh) * 2020-11-09 2021-02-09 哈尔滨工业大学 一种加速度计

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110037104A1 (en) * 2009-08-13 2011-02-17 International Business Machines Corporation Vertical spacer forming and related transistor
WO2012051824A1 (zh) * 2010-10-22 2012-04-26 北京大学 一种快闪存储器及其制备方法和操作方法
US20120132986A1 (en) * 2010-11-26 2012-05-31 Pil-Kyu Kang Semiconductor devices and methods of manufacturing the same
CN102769016A (zh) * 2012-08-14 2012-11-07 北京大学 一种抗辐射的cmos器件及其制备方法

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03187272A (ja) * 1989-12-15 1991-08-15 Mitsubishi Electric Corp Ｍｏｓ型電界効果トランジスタ及びその製造方法
US6559491B2 (en) * 2001-02-09 2003-05-06 Micron Technology, Inc. Folded bit line DRAM with ultra thin body transistors
US6531727B2 (en) * 2001-02-09 2003-03-11 Micron Technology, Inc. Open bit line DRAM with ultra thin body transistors
US7202523B2 (en) * 2003-11-17 2007-04-10 Micron Technology, Inc. NROM flash memory devices on ultrathin silicon
US7888721B2 (en) * 2005-07-06 2011-02-15 Micron Technology, Inc. Surround gate access transistors with grown ultra-thin bodies
US7439576B2 (en) * 2005-08-29 2008-10-21 Micron Technology, Inc. Ultra-thin body vertical tunneling transistor
US8409959B2 (en) * 2007-03-13 2013-04-02 Micron Technology, Inc. Vertically base-connected bipolar transistor
JP5356970B2 (ja) * 2009-10-01 2013-12-04 ユニサンティス エレクトロニクス シンガポール プライベート リミテッド 半導体装置
CN101707210B (zh) * 2009-11-27 2012-05-30 北京大学 一种抗辐照的场效应晶体管、cmos集成电路及其制备
CN102074577B (zh) * 2010-10-09 2013-03-06 北京大学 一种垂直沟道场效应晶体管及其制备方法
US8748983B2 (en) * 2011-04-29 2014-06-10 Institute of Microelectronics, Chinese Academy of Sciences Embedded source/drain MOS transistor
CN102222687B (zh) * 2011-06-23 2012-12-19 北京大学 一种锗基nmos器件及其制备方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110037104A1 (en) * 2009-08-13 2011-02-17 International Business Machines Corporation Vertical spacer forming and related transistor
WO2012051824A1 (zh) * 2010-10-22 2012-04-26 北京大学 一种快闪存储器及其制备方法和操作方法
US20120132986A1 (en) * 2010-11-26 2012-05-31 Pil-Kyu Kang Semiconductor devices and methods of manufacturing the same
CN102769016A (zh) * 2012-08-14 2012-11-07 北京大学 一种抗辐射的cmos器件及其制备方法

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