WO2012174872A1 - 一种锗基nmos器件及其制备方法 - Google Patents

一种锗基nmos器件及其制备方法 Download PDF

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WO2012174872A1
WO2012174872A1 PCT/CN2012/071393 CN2012071393W WO2012174872A1 WO 2012174872 A1 WO2012174872 A1 WO 2012174872A1 CN 2012071393 W CN2012071393 W CN 2012071393W WO 2012174872 A1 WO2012174872 A1 WO 2012174872A1
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dielectric layer
germanium
insulating dielectric
substrate
oxide
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PCT/CN2012/071393
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English (en)
French (fr)
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黄如
李志强
安霞
郭岳
张兴
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北京大学
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Priority to US13/519,857 priority Critical patent/US20130069126A1/en
Publication of WO2012174872A1 publication Critical patent/WO2012174872A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41775—Source or drain electrodes for field effect devices characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
    • H01L29/41783—Raised source or drain electrodes self aligned with the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0895—Tunnel injectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66643—Lateral single gate silicon transistors with source or drain regions formed by a Schottky barrier or a conductor-insulator-semiconductor structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/517—Insulating materials associated therewith the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

Definitions

  • the embodiment of the invention belongs to the field of ultra-large scale integrated circuit (ULSI) process manufacturing technology, and particularly relates to a germanium-based MOS device structure and a preparation method thereof.
  • ULSI ultra-large scale integrated circuit
  • the ⁇ -based Schottky MOS transistor is a very promising device structure.
  • the main difference between it and the traditional MOS transistor is that it replaces the traditional highly doped source and drain with metal or metal telluride source and drain, whereby the contact between the source and drain and the channel changes from PN junction to Schottky in contact with metal and semiconductor.
  • the knot not only avoids the problem of low solid solubility and rapid diffusion of impurities in the tantalum material, but also ensures low resistivity and obtains a source of leakage.
  • the ⁇ -Schottky MOS transistor also has problems to be solved: a large number of interface states cause the Fermi level to be pinned near the valence band, resulting in a large electron barrier which limits the performance of the ⁇ -based Schottky MOS transistor. Upgrade. These interface states generally have two sources: On the one hand, the incomplete attenuation of the electron wave function of the metal (or metal telluride) in the enthalpy leads to the production of a large amount of metal-induced band gap state (MIGS) in the forbidden zone; In respect, there are a large number of dangling bonds on the surface of the crucible, and these unsaturated dangling bonds also cause the interface state to be generated.
  • MIGS metal-induced band gap state
  • the germanium-based MOS device provided by the invention inserts an insulating dielectric layer between the metal source drain and the substrate, thereby blocking metal or metal telluride from generating a metal induced band gap state (MIGS) in the forbidden zone, thereby achieving Attenuate the Fermi level pinning effect and adjust the height of the Schottky barrier.
  • MIGS metal induced band gap state
  • the pinning factor of the insulating dielectric layer is required to be high and the conduction band offset is small.
  • the material of the underlying dielectric layer is insulated with a high pinning factor (S>0.55).
  • Dielectric materials such as silicon nitride (Si 3 N 4 ), hafnium oxide (Hf0 2 ), hafnium silicon oxide (HfSi0 4 ), etc.; the material of the upper dielectric layer is low conduction band offset (AE c ⁇ 1.0eV)
  • the insulating dielectric material such as titanium dioxide CTi0 2 ), gallium oxide (Ga 2 0 3 ), niobium titanium oxide (SrTi0 3 ), and the like.
  • the electron barrier of the source and drain can be reduced, and the performance of the germanium-based Schottky MOS device can be improved.
  • the preparation method of a bismuth-based Schottky MOS device of the present invention is briefly described below. The steps are as follows:
  • Steps 1 to 1) include:
  • the germanium-based substrate of the step 1 - 1) includes a bulk germanium substrate, a germanium-insulated insulating substrate (GOI) or an epitaxial germanium substrate, and the like.
  • the underlying insulating dielectric layer of the step 1 - 2) uses a dielectric material having a high pinning factor S such as silicon nitride (Si 3 N 4 ), hafnium oxide (Hf0 2 ), or hafnium silicon oxide (HfSi0 4 );
  • the dielectric layer is made of a dielectric material having a low conduction band offset AE C such as titanium oxide (Ti0 2 ), gallium oxide (Ga 2 0 3 ), or strontium titanium oxide (SrTi0 3 ).
  • the metal film of the step 1 - 3) is an aluminum film or other low work function metal film. Compared with the prior art, the beneficial effects of the present invention are:
  • the Schottky barrier formed by the source/drain and channel contact can be effectively adjusted, the switching current ratio of the device is increased, and the subthreshold slope is lowered.
  • the underlying insulating dielectric layer has a large pinning factor S, the Fermi level pinning effect can be well suppressed, and the Schottky barrier height varies to some extent with the change of the work function of the metal;
  • the conduction band offset AE C of the upper insulating dielectric layer is small, the MIGS interface state introduced by the electron wave function in the metal in the semiconductor band gap can be further blocked, and a small tunneling resistance is ensured. .
  • the underlying insulating dielectric layer is generally required to have a pinning factor S>0.55, such as silicon nitride (Si 3 N 4 ), hafnium oxide (Hf0 2 ), germanium silicon oxide (HfSi0 4 ).
  • a dielectric material having a high pinning factor S; and a conduction band offset of the upper insulating dielectric layer is required to be AE c ⁇ 1.0eV, such as titanium dioxide (Ti0 2 ), gallium oxide (Ga 2 0 3 ), niobium titanium oxide (SrTi0 3 ) )
  • AE C silicon dioxide
  • Ga 2 0 3 gallium oxide
  • FIG. 1(a) - FIG. 1(j) is a flow chart of preparing a bismuth-based Schottky NMOS device according to an embodiment of the present invention.
  • 1 substrate; 2 - P well region; 3 - isolation region; 4 a gate dielectric layer; 5 - metal gate; 6 - side wall; 7 - underlying insulating dielectric layer; 8 - upper insulating dielectric layer; A metal source, a leak; 10 - a metal wiring layer.
  • Step 1 is a flow chart of a method of fabricating a germanium based Schottky MOS device in accordance with a preferred embodiment of the present invention.
  • the method of fabricating a germanium-based Schottky MOS device according to an embodiment of the invention comprises the following steps: Step 1: providing a germanium-based substrate. As shown in FIG. 1(a), an N-type semiconductor germanium substrate 1 is provided, wherein the semiconductor germanium substrate 1 may be a body germanium, a germanium-insulated insulating (G0I) or an epitaxial germanium substrate. Step 2: Make a P-well region.
  • Step 3 Implement trench isolation.
  • the isolation region 3 first deposits a silicon oxide layer and a silicon nitride layer on the semiconductor germanium substrate 1, and then lithographically defines and etches the silicon nitride layer by reactive ion etching.
  • the silicon layer and the semiconductor germanium substrate 1 form a trench, and then a silicon oxide layer is deposited by a chemical vapor deposition (CVD) method to backfill the isolation trench, and finally the surface is ground by chemical mechanical polishing (CMP) to achieve isolation between devices.
  • CVD chemical vapor deposition
  • CMP chemical mechanical polishing
  • Device isolation is not limited to shallow trench isolation (STI), but techniques such as field oxide isolation can also be used.
  • Step 4 Form a gate dielectric layer on the active region.
  • the gate dielectric layer may be made of a high-k dielectric, cerium oxide, cerium oxynitride or the like. Before the deposition of the gate dielectric layer, it is generally required to perform surface passivation treatment with PH 3 , H 3 , and F plasma, or deposit an interface layer such as silicon (Si), aluminum nitride (A1N;), or antimony oxide. (Y 2 0 3 ) and so on.
  • a thin layer of yttrium oxide ( ⁇ 2 O 3 ) is formed on the semiconductor germanium substrate 1 as an interface layer, and then a hafnium oxide (Hf0 2 ) gate dielectric layer is obtained by an atomic layer deposition (ALD) method. , as shown in Figure 1 (d).
  • the gate may be a polysilicon gate, a metal gate, a FUSI gate or a full germanium gate.
  • a metal gate is formed by depositing titanium nitride (TiN), and then lithographically defined and etched to form a gate structure, as shown in FIG. 1 (e) ) as shown.
  • Step 6 Prepare the side walls on both sides of the grid.
  • the spacers may be prepared by depositing SiO 2 or Si 3 N 4 and etching, or sequentially depositing Si 3 N 4 and SiO 2 to form a double-sided wall structure.
  • a sidewall structure 6 is formed on both sides of the gate by depositing Si0 2 and dry etching.
  • Step 7 depositing an underlying dielectric layer of the source and drain regions.
  • the Fermi level pinning factor of the dielectric material of this layer is S>0.55, such as silicon nitride (Si 3 N 4 ), hafnium oxide (Hf0 2 ), hafnium silicon oxide (HfSi0 4 ), etc., which is adopted in the preferred embodiment.
  • Silicon Nitride (Si 3 N 4 ) This layer can be obtained by ALD deposition and has a thickness of about 0.5 to 2 nm, as shown in Figure 1 (g).
  • Step 8 deposit an upper insulating dielectric layer of the source and drain regions.
  • the conduction band offset of the dielectric material of this layer is required to be ⁇ E c ⁇ 1.0eV, such as titanium dioxide (Ti0 2 ), gallium oxide (Ga 2 0 3 ), strontium titanyl oxide (SrTi0 3 ), etc., and the preferred embodiment of the present embodiment uses titanium dioxide. (Ti0 2 ).
  • This layer can also be obtained by ALD deposition with a thickness ranging from 0.5 to 4 nm, as shown in Figure 1 (h).
  • Step 9 Prepare a metal source drain.
  • a low work function metal film such as aluminum (Al), titanium (Ti), ytterbium (Y) or the like may be deposited on the semiconductor germanium substrate 1 by physical vapor deposition such as evaporation or sputtering.
  • the preferred embodiment is aluminum, the thickness of which is in the range of 100 nm lm, which is defined by lithography and etched to obtain a metal source drain, as shown in Fig. 1 (i).
  • Step 10 Form contact holes and metal wires.
  • CVD is used to deposit a silicon oxide layer, lithography Defining the opening position and etching the silicon oxide oxide layer to form a contact hole; then sputtering a metal layer such as Al, Al-Ti, etc., and then photolithographically defining the wiring pattern and etching to form a metal wiring pattern, and finally performing Metallization treatment is performed to obtain the metal wiring layer 10 as shown in Fig. 1 (j).
  • Embodiments of the present invention provide a NMOS-based MOS device structure and a method of fabricating the same.
  • This method can not only reduce the barrier height of electrons in the source and drain of ⁇ -based Schottky MOS devices, improve the current switching ratio of ⁇ -based Schottky devices, improve the performance of ⁇ -based Schottky MOS devices, and the fabrication process and silicon CMOS
  • the technology is fully compatible and maintains the advantages of a simple process.
  • the device structure and the preparation method can simply and effectively improve the performance of the bismuth-based Schottky MOS device.
  • the method for preparing a bismuth-based Schottky device according to the embodiment of the present invention is described in detail above by way of a preferred embodiment. Those skilled in the art should understand that the above description is only a preferred embodiment of the present invention.
  • the device structure of the present invention may be modified or modified.
  • the source-drain structure may also adopt a lifted, recessed source/drain structure, or other new structures such as a double gate, a FinFET, an ⁇ gate, a triple gate, and Fences and the like; the preparation method thereof is not limited to the contents disclosed in the embodiments, and all changes and modifications made in accordance with the claims of the present invention are within the scope of the present invention.

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Abstract

本发明实施例提出一种锗基NMOS器件及其制备方法，属于超大规模集成电路（ULSI）工艺制造技术领域。该锗基NMOS器件的金属源、漏和衬底之间插入两层绝缘介质层，底层绝缘介质层采用氧化铪、氮化硅或铪硅氧等高钉扎系数S介质材料；而上层绝缘介质层采用二氧化钛、氧化镓或锶钛氧等低导带偏移量ΔEC介质材料。本发明可以减弱费米能级钉扎效应，降低电子势垒，进而改善锗基肖特基NMOS器件的性能。与现有的采用单层绝缘介质层如氧化铝（Al2O3）等相比，本发明能够有效降低肖特基势垒并能保持较低的源漏电阻，在很大程度上改善了器件性能。

Description

一种锗基 NMOS器件及其制备方法
相关申请的交叉引用
本申请要求于 2011年 6月 23日提交至中国国家知识产权局的中国专利申请（申 请号为： 201110171004.2) 的优先权， 其全部内容通过引用合并于此。 技术领域
本发明实施例属于超大规模集成电路 （ULSI) 工艺制造技术领域， 具体涉及一 种锗基 MOS器件结构及其制备方法。 背景技术 随着 CMOS器件尺寸不断缩小， 传统硅基 MOS器件遇到了诸多挑战， 其中迁移 率退化成为影响器件性能进一步提升的关键因素之一。相比硅材料，锗材料具有更高、 更加对称的低场载流子迁移率， 而且锗器件的制备工艺与传统 CMOS工艺兼容， 因 此， 锗基器件成为目前研究热点之一。
锗基肖特基 MOS晶体管是一种非常有潜力的器件结构。它与传统 MOS晶体管的 主要区别就是用金属或者金属锗化物源漏替代了传统的高掺杂源漏，由此源漏和沟道 的接触由 PN结变成了金属和半导体接触的肖特基结， 这样不仅避免了锗材料中杂质 固溶度低和扩散快的问题， 而且还能保证低电阻率和获得突变源漏结。但锗基肖特基 MOS 晶体管也存在亟待解决的问题： 大量的界面态使费米能级被钉扎在价带附近， 导致电子势垒较大进而限制了锗基肖特基 MOS晶体管性能的提升。 这些界面态一般 有两个来源： 一方面， 金属 (或金属锗化物)的电子波函数在锗中的不完全衰减导致在 锗禁带当中产生大量的金属诱导带隙态（MIGS); 另一方面， 锗表面存在大量的悬挂 键， 这些不饱和的悬挂键也会导致界面态的产生。 发明内容
本发明的目的是提供一种锗基 MOS 器件及其制备方法， 可减弱费米能级钉扎 效应、 调节肖特基势垒高度。 本发明提供的锗基 MOS 器件是在金属源漏和衬底之间插入了绝缘介质层， 由 此可以阻挡金属或金属锗化物在锗禁带中产生金属诱导带隙态（MIGS),进而达到减 弱费米能级钉扎效应、调节肖特基势垒高度的目的。为了有效抑制费米能级钉扎效应， 要求绝缘介质层的钉扎系数高以及导带偏移量小。但能同时满足这两个参数要求的介 质材料很少， 因此本发明提出采用双层绝缘介质层的结构来达到此要求： 底层绝缘介 质层的材料采用高钉扎系数 (S>0.55)的绝缘介质材料， 如氮化硅 (Si3N4) 、 氧化铪 (Hf02)、 铪硅氧 (HfSi04)等； 上层绝缘介质层的材料采用低导带偏移量 (AEc<1.0eV) 的绝缘介质材料， 如二氧化钛 CTi02)、 氧化镓 (Ga203)、 锶钛氧 (SrTi03)等。 通过在源 漏区和衬底间淀积两层绝缘介质层， 可以降低源漏的电子势垒， 改善锗基肖特基 MOS器件的性能。 下面简述本发明的一种锗基肖特基 MOS器件的制备方法， 步骤如下：
1-1 ) 在锗基衬底上制作 MOS结构；
1-2) 淀积源漏区域的两层绝缘介质层， 具体是， 在衬底上淀积底层绝缘介质 层， 该底层绝缘介质层的高钉扎系数 S>0.55， 在底层绝缘介质层上淀积一层上层绝 缘介质层， 该上层绝缘介质层的低导带偏移量 AEc<1.0eV;
1-3 ) 溅射低功函数金属薄膜， 刻蚀形成金属源漏；
1- 4) 形成接触孔、 金属连线。
步骤 1一 1)包括：
2— 1)在衬底上制备隔离区；
2— 2)淀积栅介质层以及栅；
2— 3)形成栅结构；
2— 4)形成侧墙结构。 所述步骤 1一 1 )的锗基衬底包括体锗衬底、锗覆绝缘衬底 (GOI)或外延锗衬底等。 所述步骤 1一 2) 的底层绝缘介质层采用氮化硅 (Si3N4) 、 氧化铪 (Hf02)、 铪硅氧 (HfSi04)等高钉扎系数 S 的介质材料； 而上层绝缘介质层采用二氧化钛 (Ti02)、 氧化 镓 (Ga203)、 锶钛氧 (SrTi03)等低导带偏移量 AEC的介质材料。 所述步骤 1一 3 ) 的金属薄膜为铝膜或其他低功函数金属膜。 与现有技术相比， 本发明的有益效果是：
通过在金属源漏和衬底之间插入两层薄的绝缘介质层，能有效调节源 /漏与沟道接 触所形成的肖特基势垒， 提升器件的开关电流比， 降低亚阈值斜率。一方面， 由于底 层绝缘介质层有较大的钉扎系数 S， 能较好地抑制费米能级钉扎效应， 使肖特基势垒 高度在一定程度上随金属的功函数变化而变化； 另一方面， 由于上层绝缘介质层的导 带偏移量 AEC较小， 能够进一步阻挡金属中的电子波函数在半导体禁带中引入的 MIGS界面态， 同时又保证了较小的隧穿电阻。 为了有效抑制费米能级钉扎效应， 一般要求下层绝缘介质层其钉扎系数 S>0.55， 如氮化硅 (Si3N4) 、 氧化铪 (Hf02)、 铪硅氧 (HfSi04)等高钉扎系数 S的介质材料； 而要 求上层绝缘介质层的导带偏移量 AEc<1.0eV， 如二氧化钛 (Ti02)、 氧化镓 (Ga203)、 锶 钛氧 (SrTi03)等低导带偏移量 AEC的介质材料。 此方法可以减弱费米能级钉扎效应， 降低电子势垒， 进而改善锗基肖特基 MOS器件的性能。 与现有的采用单层绝缘介 质层如氧化铝 （A1203) 等相比， 本发明能够有效降低肖特基势垒并能保持较低的源 漏电阻， 可以显著提升器件性能。 附图说明 图 1 (a)—图 1 (j ) 为本发明实施例提出的制备锗基肖特基 NMOS器件的流程 图。
其中， 1一锗衬底； 2— P阱区域； 3—隔离区； 4一栅介质层； 5—金属栅； 6—侧 墙； 7—底层绝缘介质层； 8—上层绝缘介质层； 9一金属源、 漏； 10—金属连线层。 具体实施方式 下面结合附图和具体实施方式对本发明作进一步详细描述：
图 1为本发明一优选实施例的制作锗基肖特基 MOS器件的方法的流程图。 本 发明实施例的制作锗基肖特基 MOS器件的方法包括如下步骤： 步骤 1 : 提供锗基衬底。 如图 1 (a) 所示， 提供 N型半导体锗衬底 1， 其中半导 体锗衬底 1可采用体锗、 锗覆绝缘 （G0I) 或外延锗衬底等。 步骤 2: 制作 P阱区域。 在半导体锗衬底 1上淀积氧化硅层和氮化硅层， 首先通 过光刻定义 P阱区域并反应离子刻蚀掉 P阱区域的氮化硅层， 然后离子注入 P型杂 质如硼等， 再退火驱入制作 P阱区域 2， 最后去掉注入时使用的掩蔽层， 完成后如图 1 (b) 所示。
步骤 3 : 实现沟槽隔离。 如图 1 (c) 中隔离区 3， 首先在半导体锗衬底 1上淀积 氧化硅层和氮化硅层，然后通过光刻定义并利用反应离子刻蚀技术刻蚀氮化硅层、氧 化硅层以及半导体锗衬底 1形成沟槽， 再利用化学气相淀积（CVD)方法淀积氧化硅 层回填隔离槽，最后采用化学机械抛光技术（CMP)将表面磨平，实现器件间的隔离。 器件隔离不局限于浅槽隔离 （STI)， 也可以采用场氧隔离等技术。
步骤 4: 在有源区上形成栅介质层。 栅介质层可以采用高 K介质、 二氧化锗、 氮 氧化锗等材料。 在淀积栅介质层之前， 一般需要用 PH3、 H3以及 F等离子体等进行 表面钝化处理， 或淀积一层界面层如硅 (Si)、 氮化铝 (A1N；)、 氧化钇 (Y203)等。 本优选 实施例先在半导体锗衬底 1上制作一层薄的氧化钇 (Υ203)作为界面层， 然后采用原子 层淀积 （ALD) 方法得到氧化铪 (Hf02) 栅介质层 4， 如图 1 (d) 所示。 步骤 5: 在所述栅极介质层 4上形成栅。 栅可采用多晶硅栅、 金属栅、 FUSI栅或 全锗化物栅等， 本实施例采用淀积氮化钛 （TiN) 制备金属栅， 然后光刻定义并刻蚀 形成栅结构， 如图 1 (e) 所示。
步骤 6: 在栅两侧制备侧墙。可以通过淀积 Si02或 Si3N4并刻蚀的方式制备侧墙， 也可依次淀积 Si3N4和 Si02形成双侧墙结构。 如图 1 (0 所示， 本实施例采用淀积 Si02加干法刻蚀的方法， 在栅的两侧形成侧墙结构 6。 步骤 7: 淀积源漏区域的底层绝缘介质层。 要求此层的介质材料的费米能级钉扎 系数 S>0.55， 如采用氮化硅 (Si3N4) 、 氧化铪 (Hf02)、 铪硅氧 (HfSi04)等， 本优选实施 例采用氮化硅 (Si3N4)。 此层可以通过 ALD淀积的方式得到， 其厚度约为 0.5~2nm， 如图 1 (g) 所示。
步骤 8: 淀积源漏区域的上层绝缘介质层。 要求此层的介质材料的导带偏移量 Δ Ec<1.0eV, 如二氧化钛 (Ti02)、 氧化镓 (Ga203)、 锶钛氧 (SrTi03)等， 本实施优选例采 用二氧化钛 (Ti02)。此层同样可以通过 ALD淀积的方式得到， 其厚度范围在 0.5~4nm 之间， 如图 1 (h) 所示。 步骤 9: 制备金属源漏。 可以采用物理气相淀积方式如蒸镀或溅射， 在半导体锗 衬底 1上淀积一层低功函数金属薄膜如铝 (Al)、钛 (Ti)、钇 (Y)等。本优选实施例为铝， 其厚度范围在 lOOnm l m, 通过光刻定义并刻蚀得到金属源漏， 如图 1 (i) 所示。
步骤 10: 形成接触孔、 金属连线。 首先用 CVD方式淀积二氧化硅氧化层， 光刻 定义出开孔位置并刻蚀二氧化硅氧化层， 形成接触孔； 然后溅射金属层如 Al、 Al-Ti 等， 再光刻定义出连线图形并刻蚀形成金属连线图形， 最后进行金属化处理， 获得金 属连线层 10， 如图 1 (j ) 所示。 本发明实施例提出了一种锗基 MOS 器件结构及其制备方法。 此方法不但可以 降低锗基肖特基 MOS器件源漏处电子的势垒高度， 提升锗基肖特基器件的电流开 关比，改善锗基肖特基 MOS器件的性能，而且制作工艺与硅 CMOS技术完全兼容， 保持了工艺简单的优势。相对于现有技术，所述器件结构及制备方法能简单有效地提 升锗基肖特基 MOS器件的性能。 以上通过优选实施例详细描述了本发明实施例所提出的一种锗基肖特基器件的 制备方法， 本领域的技术人员应当理解， 以上所述仅为本发明的优选实施例， 在不脱 离本发明实质的范围内，可以对本发明的器件结构做一定的变形或修改，例如源漏结 构也可采用提升、 凹陷源漏结构， 或其他新结构如双栅、 FinFET、 Ω栅、 三栅和围栅 等； 其制备方法也不限于实施例中所公开的内容， 凡依本发明权利要求所做的均等变 化与修饰， 皆应属本发明的涵盖范围。

Claims

权 利 要 求
1. 一种锗基 MOS器件， 其特征在于， 在金属源、 漏和衬底之间插入两层 绝缘介质层， 具体是， 在衬底上淀积底层绝缘介质层， 该绝缘介质层的高钉扎系 数 S>0.55，在底层绝缘介质层上淀积上层绝缘介质层，该上层绝缘介质层的低导 带偏移量 AEc<1.0eV， 在上层绝缘介质层上淀积金属源、 漏。
2. 如权利要求 1所述的锗基 MOS器件， 其特征在于， 底层绝缘介质层选 用氮化硅、 氧化铪或铪硅氧。
3. 如权利要求 1所述的锗基 MOS器件， 其特征在于， 上层绝缘介质层可 选用二氧化钛、 氧化镓或锶钛氧。
4. 如权利要求 1所述的锗基 MOS器件， 其特征在于， 底层绝缘介质层的 厚度为 0.5~2nm。
5. 如权利要求 1所述的锗基 MOS器件， 其特征在于， 上层绝缘介质层的 厚度约为 0.5~4nm。
6. 一种锗基肖特基 MOS器件的制备方法， 步骤如下：
1—1 ) 在锗基衬底上制作 MOS结构；
1-2) 淀积源漏区域的两层绝缘介质层， 具体是， 在衬底上淀积底层绝缘 介质层， 该绝缘介质层的高钉扎系数 S>0.55， 在底层绝缘介质层上淀积一层 上层绝缘介质层， 该上层绝缘介质层的低导带偏移量 AEc<1.0eV，；
1- 3 ) 溅射低功函数金属薄膜， 刻蚀形成金属源漏；
1-4) 形成接触孔、 金属连线。
7. 如权利要求 6所述的方法， 其特征在于， 步骤 1一 1)包括：
2— 1)在衬底上制备隔离区；
2— 2)淀积栅介质层以及栅； 2— 3)形成栅结构；
2— 4)形成侧墙结构。
8. 如权利要求 6所述的方法， 其特征在于， 所述步骤 1一 1 ) 的锗基衬底包 括体锗衬底、 锗覆绝缘衬底 (GOI)或外延锗衬底。
9. 如权利要求 6所述的方法， 其特征在于， 所述步骤 1一 2) 的底层绝缘介 质层采用氮化硅、氧化铪或铪硅氧等高钉扎系数 S的介质材料； 而上层绝缘介质 采用二氧化钛、 氧化镓或锶钛氧等低导带偏移量 AEC的介质材料。
10. 如权利要求 6所述的方法， 其特征在于， 所述步骤 1一 3 ) 的金属薄膜为 铝膜或其他低功函数金属膜。
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