JP2005354105A - 半導体デバイスパッケージ及び半導体ダイの製造方法 - Google Patents
半導体デバイスパッケージ及び半導体ダイの製造方法 Download PDFInfo
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- 239000010703 silicon Substances 0.000 description 4
- DEVSOMFAQLZNKR-RJRFIUFISA-N (z)-3-[3-[3,5-bis(trifluoromethyl)phenyl]-1,2,4-triazol-1-yl]-n'-pyrazin-2-ylprop-2-enehydrazide Chemical compound FC(F)(F)C1=CC(C(F)(F)F)=CC(C2=NN(\C=C/C(=O)NNC=3N=CC=NC=3)C=N2)=C1 DEVSOMFAQLZNKR-RJRFIUFISA-N 0.000 description 3
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- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
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Abstract
【解決手段】 チップスケールパッケージは、フォトリソグラフィによってパターニングされて電極の部分を露出させ、パッシベーション層又はソルダマスクの働きをする感光性液体エポキシ層で覆われた上面電極表面を有するMOSFETダイ30を有する。液体エポキシ層の残りの部分の上には、はんだ付け可能なコンタクト層40が形成される。各個別のダイ30はドレイン側を下にして金属クリップ100に装着され、又はカン底面101から延びるフランジ105と同一平面上にあるように配置されたドレイン電極を有するカンの中に、ドレイン側を下にして装着される。
【選択図】 図21
Description
Claims (52)
- MOSゲートデバイスウェーハの表面を、ソルダマスクとして機能するパッシベーション層で覆うステップと、
下側にあるソース電極における間隔を置いて露出された複数の表面領域を形成するために、前記パッシベーション層に開口を形成するとともに、各ダイにおける下側にあるゲート電極を露出する開口を形成し、前記パッシベーション層に形成された前記開口を、下側にあるはんだ付け可能な上面金属に達するように形成するステップと、
前記ウェーハを個々のダイに個別化するステップと、
前記個別化された個々のダイをドレイン側のドレインクリップに電気的に取り付けるステップと
を有することを特徴とする半導体デバイスパッケージの製造方法。 - 前記ドレインクリップが、U字形であることを特徴とする請求項1に記載の半導体デバイスパッケージの製造方法。
- 前記ドレインクリップが、カップ形であることを特徴とする請求項1に記載の半導体デバイスパッケージの製造方法。
- 前記ドレインクリップが、メッキされることを特徴とする請求項1に記載の半導体デバイスパッケージの製造方法。
- 前記ダイが、導電性エポキシ又ははんだによって前記ドレインクリップに電気的に取り付けられることを特徴とする請求項1に記載の半導体デバイスパッケージの製造方法。
- 前記ドレインクリップが、前記ダイのソース側と脚の底面とが同一平面上になるような少なくとも1つの脚を備えることを特徴とする請求項1に記載の半導体デバイスパッケージの製造方法。
- 前記ダイと前記ドレインクリップの組立体の部分が少なくともオーバーモールドされることを特徴とする請求項1に記載の半導体デバイスパッケージの製造方法。
- 前記パッシベーション層が、エポキシからなることを特徴とする請求項1に記載の半導体デバイスパッケージの製造方法。
- 前記ウェーハが、スピニングによって覆われることを特徴とする請求項8に記載の半導体デバイスパッケージの製造方法。
- 前記ウェーハが、スクリーニングによって覆われることを特徴とする請求項8に記載の半導体デバイスパッケージの製造方法。
- 前記ウェーハが、液体エポキシを付着させることによって覆われることを特徴とする請求項8に記載の半導体デバイスパッケージの製造方法。
- 前記パッシベーション層が、感光性エポキシからなることを特徴とする請求項1に記載の半導体デバイスパッケージの製造方法。
- 前記パッシベーション層が、窒化シリコンからなることを特徴とする請求項1に記載の半導体デバイスパッケージの製造方法。
- MOSゲートデバイスウェーハの表面を、ソルダマスク及びメッキレジストとして機能するパッシベーション層で覆うステップと、
下側にあるソース電極における間隔を置いて露出された複数の表面領域を形成するために、前記パッシベーション層に開口を形成するとともに、各ダイにおける下側にあるゲート電極を露出する開口を形成するステップと、
前記ソース電極とゲート電極を、メッキレジストとして機能する前記パッシベーション層を用いてメッキし、前記ソース電極上にはんだ付け可能なコンタクトを形成するとともに、前記ゲート電極上にはんだ付け可能なコンタクトを形成するステップと、
前記ウェーハを個々のダイに個別化するステップと、
前記個別化された個々のダイをドレイン側のドレインクリップに電気的に取り付けるステップと
を有することを特徴とする半導体デバイスパッケージの製造方法。 - 前記ソース電極とゲート電極が、ニッケル及び金フラッシュ,銅,スズ、その他のはんだ付け可能な金属のいずれかでメッキされることを特徴とする請求項14に記載の半導体デバイスパッケージの製造方法。
- 前記はんだ付け可能な金属が、銀であることを特徴とする請求項14に記載の半導体デバイスパッケージの製造方法。
- 前記ドレインクリップが、U字形であることを特徴とする請求項14に記載の半導体デバイスパッケージの製造方法。
- 前記ドレインクリップが、カップ形であることを特徴とする請求項14に記載の半導体デバイスパッケージの製造方法。
- 前記ドレインクリップが、メッキされていることを特徴とする請求項14に記載の半導体デバイスパッケージの製造方法。
- 前記ダイが、導電性エポキシ又ははんだによって前記ドレインクリップに電気的に取り付けられていることを特徴とする請求項14に記載の半導体デバイスパッケージの製造方法。
- 前記ドレインクリップが、前記ダイのソース側と脚の底面とが同一平面上になるような少なくとも1つの脚を備えることを特徴とする請求項14に記載の半導体デバイスパッケージの製造方法。
- 前記ダイと前記ドレインクリップの組立体の部分が少なくともオーバーモールドされることを特徴とする請求項14に記載の半導体デバイスパッケージの製造方法。
- 前記パッシベーション層が、エポキシからなることを特徴とする請求項14に記載の半導体デバイスパッケージの製造方法。
- 前記ウェーハが、スピニングによって覆われることを特徴とする請求項23に記載の半導体デバイスパッケージの製造方法。
- 前記ウェーハが、スクリーニングによって覆われることを特徴とする請求項23に記載の半導体デバイスパッケージの製造方法。
- 前記ウェーハが、液体エポキシを付着させることによって覆われることを特徴とする請求項23に記載の半導体デバイスパッケージの製造方法。
- 前記パッシベーション層が、感光性エポキシからなることを特徴とする請求項14に記載の半導体デバイスパッケージの製造方法。
- 前記パッシベーション層が、窒化シリコンからなることを特徴とする請求項14に記載の半導体デバイスパッケージの製造方法。
- 主要な表面上に設けられる少なくとも1つの電極を有する複数のダイを半導体ウェーハに形成するステップと、
前記半導体ウェーハの前記ダイの少なくとも1つの電極をマスク材料で覆うステップと、
前記各電極に向けて少なくとも1つの開口を前記マスク材料に形成し、前記開口が前記各電極の底面に達するようにするステップと、
前記各電極に向けて前記各開口の底面に少なくとも金属層を形成するステップと、
前記半導体ウェーハから各ダイを個別化するステップと
を有することを特徴とする半導体ダイの製造方法。 - 前記ダイが、パワー半導体デバイスであることを特徴とする請求項29に記載の半導体ダイの製造方法。
- 前記ダイが、パワーMOSFETであることを特徴とする請求項29に記載の半導体ダイの製造方法。
- 前記少なくとも1つの電極が、ソース電極であることを特徴とする請求項31に記載の半導体ダイの製造方法。
- 前記各ダイの前記主要な表面上に第2の電極を備えることを特徴とする請求項29に記載の半導体ダイの製造方法。
- 前記第2の電極が、ゲート電極であることを特徴とする請求項33に記載の半導体ダイの製造方法。
- 前記マスク材料が、フォトイメージ性のソルダマスクであることを特徴とする請求項29に記載の半導体ダイの製造方法。
- 前記マスク材料が、エポキシであることを特徴とする請求項29に記載の半導体ダイの製造方法。
- 前記エポキシが、感光性であることを特徴とする請求項36に記載の半導体ダイの製造方法。
- 前記マスク材料が、メッキレジストとして機能することを特徴とする請求項29に記載の半導体ダイの製造方法。
- 前記マスク材料が、パッシベーションとして機能することを特徴とする請求項29に記載の半導体ダイの製造方法。
- 前記マスク材料が、窒化シリコンからなることを特徴とする請求項29に記載の半導体ダイの製造方法。
- 前記開口するステップが、レチクルで行われることを特徴とする請求項29に記載の半導体ダイの製造方法。
- 前記開口するステップが、レーザエッチングで行われることを特徴とする請求項29に記載の半導体ダイの製造方法。
- 前記少なくとも1つの金属層が、メッキによって形成されることを特徴とする請求項29に記載の半導体ダイの製造方法。
- 前記少なくとも1つの金属層が、ニッケルからなることを特徴とする請求項43に記載の半導体ダイの製造方法。
- 前記1つの金属層の上面に第2の金属層を形成するステップを有することを特徴とする請求項29に記載の半導体ダイの製造方法。
- 前記第2の金属層が、金からなることを特徴とする請求項45に記載の半導体ダイの製造方法。
- 前記第2の金属層が、スズからなることを特徴とする請求項45に記載の半導体ダイの製造方法。
- 前記第2の金属層が、銅からなることを特徴とする請求項45に記載の半導体ダイの製造方法。
- 前記第2の金属層の上面に第3の金属層を形成するステップを有することを特徴とする請求項45に記載の半導体ダイの製造方法。
- 前記第3の金属層が、銀からなることを特徴とする請求項49に記載の半導体ダイの製造方法。
- 前記第2の金属層が、メッキされていることを特徴とする請求項45に記載の半導体ダイの製造方法。
- 前記第3の金属層が、メッキされていることを特徴とする請求項50に記載の半導体ダイの製造方法。
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JP2009533871A (ja) * | 2006-04-13 | 2009-09-17 | インターナショナル レクティファイアー コーポレイション | 高電力密度装置用、特にigbtおよびダイオード用の低インダクタンスのボンドワイヤレス共同パッケージ |
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JP2014216508A (ja) * | 2013-04-26 | 2014-11-17 | パナソニック株式会社 | 半導体装置 |
JP2015164779A (ja) * | 2014-03-03 | 2015-09-17 | セイコーエプソン株式会社 | 液体吐出装置、ヘッドユニットおよび液体吐出装置の制御方法 |
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US10490489B2 (en) | 2017-01-09 | 2019-11-26 | Silanna Asia Pte Ltd | Conductive clip connection arrangements for semiconductor packages |
Also Published As
Publication number | Publication date |
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US7476979B2 (en) | 2009-01-13 |
TW503487B (en) | 2002-09-21 |
EP1287553A1 (en) | 2003-03-05 |
JP2009105437A (ja) | 2009-05-14 |
AU2001249587A1 (en) | 2001-10-15 |
HK1057648A1 (en) | 2004-04-08 |
US7122887B2 (en) | 2006-10-17 |
US20040026796A1 (en) | 2004-02-12 |
US6890845B2 (en) | 2005-05-10 |
US6767820B2 (en) | 2004-07-27 |
WO2001075961A8 (en) | 2002-02-07 |
US20010048116A1 (en) | 2001-12-06 |
CN1430791A (zh) | 2003-07-16 |
US20040038509A1 (en) | 2004-02-26 |
CN1316577C (zh) | 2007-05-16 |
US20040224438A1 (en) | 2004-11-11 |
JP3768158B2 (ja) | 2006-04-19 |
WO2001075961A1 (en) | 2001-10-11 |
US20050186707A1 (en) | 2005-08-25 |
US6624522B2 (en) | 2003-09-23 |
US7253090B2 (en) | 2007-08-07 |
EP1287553A4 (en) | 2007-11-07 |
JP2004500720A (ja) | 2004-01-08 |
US20060220123A1 (en) | 2006-10-05 |
JP4343158B2 (ja) | 2009-10-14 |
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