EP0978871A3 - A low power packaging design - Google Patents

A low power packaging design Download PDF

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Publication number
EP0978871A3
EP0978871A3 EP19990114184 EP99114184A EP0978871A3 EP 0978871 A3 EP0978871 A3 EP 0978871A3 EP 19990114184 EP19990114184 EP 19990114184 EP 99114184 A EP99114184 A EP 99114184A EP 0978871 A3 EP0978871 A3 EP 0978871A3
Authority
EP
European Patent Office
Prior art keywords
low power
packaging design
power packaging
bent edge
edge tab
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP19990114184
Other languages
German (de)
French (fr)
Other versions
EP0978871A2 (en
Inventor
Charles Hewitt
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Harris Corp
Original Assignee
Harris Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Harris Corp filed Critical Harris Corp
Publication of EP0978871A2 publication Critical patent/EP0978871A2/en
Publication of EP0978871A3 publication Critical patent/EP0978871A3/en
Withdrawn legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H01L23/043—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having a conductive base as a mounting as well as a lead for the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54406—Marks applied to semiconductor devices or parts comprising alphanumeric information
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54473—Marks applied to semiconductor devices or parts for use after dicing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54473—Marks applied to semiconductor devices or parts for use after dicing
    • H01L2223/54486—Located on package parts, e.g. encapsulation, leads, package substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/731—Location prior to the connecting process
    • H01L2224/73151—Location prior to the connecting process on different surfaces
    • H01L2224/73153—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01075—Rhenium [Re]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12042—LASER
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1301—Thyristor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Abstract

A connector 20 has a strap 21 for a drain contact formed in a conventional sheet of leadframe metal. The sheet is punched and formed to a fashion bent edge tab contacts 22, 24 with a surface for mounting the power MOSFET. The bent edge tab contains 22, 24 bring the drain electrical current from the backside of a mounted device to the plane comprising the top side of the device 90.
EP19990114184 1998-08-05 1999-07-22 A low power packaging design Withdrawn EP0978871A3 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US129321 1993-09-30
US12932198A 1998-08-05 1998-08-05

Publications (2)

Publication Number Publication Date
EP0978871A2 EP0978871A2 (en) 2000-02-09
EP0978871A3 true EP0978871A3 (en) 2001-12-19

Family

ID=22439435

Family Applications (1)

Application Number Title Priority Date Filing Date
EP19990114184 Withdrawn EP0978871A3 (en) 1998-08-05 1999-07-22 A low power packaging design

Country Status (2)

Country Link
EP (1) EP0978871A3 (en)
JP (1) JP2000082816A (en)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7595547B1 (en) 2005-06-13 2009-09-29 Vishay-Siliconix Semiconductor die package including cup-shaped leadframe
US6744124B1 (en) * 1999-12-10 2004-06-01 Siliconix Incorporated Semiconductor die package including cup-shaped leadframe
US6624522B2 (en) 2000-04-04 2003-09-23 International Rectifier Corporation Chip scale surface mounted device and process of manufacture
US6893901B2 (en) 2001-05-14 2005-05-17 Fairchild Semiconductor Corporation Carrier with metal bumps for semiconductor die packages
US7476964B2 (en) 2001-06-18 2009-01-13 International Rectifier Corporation High voltage semiconductor device housing with increased clearance between housing can and die for improved flux flushing
JP3868777B2 (en) * 2001-09-11 2007-01-17 株式会社東芝 Semiconductor device
US6784540B2 (en) 2001-10-10 2004-08-31 International Rectifier Corp. Semiconductor device package with improved cooling
US7397137B2 (en) 2002-07-15 2008-07-08 International Rectifier Corporation Direct FET device for high frequency application
US7579697B2 (en) 2002-07-15 2009-08-25 International Rectifier Corporation Arrangement for high frequency application
DE10249206B3 (en) * 2002-10-22 2004-07-01 Siemens Ag Method of assembling a power device
US20050269677A1 (en) * 2004-05-28 2005-12-08 Martin Standing Preparation of front contact for surface mounting
US7524701B2 (en) 2005-04-20 2009-04-28 International Rectifier Corporation Chip-scale package
US7230333B2 (en) 2005-04-21 2007-06-12 International Rectifier Corporation Semiconductor package
US8466546B2 (en) 2005-04-22 2013-06-18 International Rectifier Corporation Chip-scale package
US20070215997A1 (en) * 2006-03-17 2007-09-20 Martin Standing Chip-scale package
CN109671766B (en) 2017-10-13 2023-06-27 联华电子股份有限公司 Power mosfet

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2964431A (en) * 1959-07-28 1960-12-13 Rca Corp Jig alloying of semiconductor devices
US3972062A (en) * 1973-10-04 1976-07-27 Motorola, Inc. Mounting assemblies for a plurality of transistor integrated circuit chips
JPS61247063A (en) * 1985-04-24 1986-11-04 Nec Corp Structure of lead frame
US4646129A (en) * 1983-09-06 1987-02-24 General Electric Company Hermetic power chip packages
JPH01239963A (en) * 1988-03-22 1989-09-25 Nippon Inter Electronics Corp Composite semiconductor device
US5139972A (en) * 1991-02-28 1992-08-18 General Electric Company Batch assembly of high density hermetic packages for power semiconductor chips
US5311059A (en) * 1992-01-24 1994-05-10 Motorola, Inc. Backplane grounding for flip-chip integrated circuit

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2964431A (en) * 1959-07-28 1960-12-13 Rca Corp Jig alloying of semiconductor devices
US3972062A (en) * 1973-10-04 1976-07-27 Motorola, Inc. Mounting assemblies for a plurality of transistor integrated circuit chips
US4646129A (en) * 1983-09-06 1987-02-24 General Electric Company Hermetic power chip packages
JPS61247063A (en) * 1985-04-24 1986-11-04 Nec Corp Structure of lead frame
JPH01239963A (en) * 1988-03-22 1989-09-25 Nippon Inter Electronics Corp Composite semiconductor device
US5139972A (en) * 1991-02-28 1992-08-18 General Electric Company Batch assembly of high density hermetic packages for power semiconductor chips
US5311059A (en) * 1992-01-24 1994-05-10 Motorola, Inc. Backplane grounding for flip-chip integrated circuit

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
"THERMALLY CONDUCTIVE SUBSTRATE MOUNTED MULTI-CHIP MODULE CAP", IBM TECHNICAL DISCLOSURE BULLETIN, IBM CORP. NEW YORK, US, VOL. 36, NR. 9B, PAGE(S) 623-624, ISSN: 0018-8689, XP000397284 *
PATENT ABSTRACTS OF JAPAN vol. 011, no. 095 (E - 492) 25 March 1987 (1987-03-25) *
PATENT ABSTRACTS OF JAPAN vol. 013, no. 574 (E - 863) 19 December 1989 (1989-12-19) *

Also Published As

Publication number Publication date
EP0978871A2 (en) 2000-02-09
JP2000082816A (en) 2000-03-21

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