CN1430791A - 芯片尺度表面安装器件及其制造方法 - Google Patents

芯片尺度表面安装器件及其制造方法 Download PDF

Info

Publication number
CN1430791A
CN1430791A CN01810001A CN01810001A CN1430791A CN 1430791 A CN1430791 A CN 1430791A CN 01810001 A CN01810001 A CN 01810001A CN 01810001 A CN01810001 A CN 01810001A CN 1430791 A CN1430791 A CN 1430791A
Authority
CN
China
Prior art keywords
electrode
metal
tube core
plane
face
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN01810001A
Other languages
English (en)
Other versions
CN1316577C (zh
Inventor
M·斯坦丁
H·D·肖菲尔德
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon science and technology Americas
Original Assignee
International Rectifier Corp USA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Rectifier Corp USA filed Critical International Rectifier Corp USA
Publication of CN1430791A publication Critical patent/CN1430791A/zh
Application granted granted Critical
Publication of CN1316577C publication Critical patent/CN1316577C/zh
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/492Bases or plates or solder therefor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544Marks applied to semiconductor devices or parts
    • H01L2223/54473Marks applied to semiconductor devices or parts for use after dicing
    • H01L2223/54486Located on package parts, e.g. encapsulation, leads, package substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/1147Manufacturing methods using a lift-off mask
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/29198Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29199Material of the matrix
    • H01L2224/2929Material of the matrix with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/29198Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298Fillers
    • H01L2224/29299Base material
    • H01L2224/293Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29338Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29339Silver [Ag] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/731Location prior to the connecting process
    • H01L2224/73151Location prior to the connecting process on different surfaces
    • H01L2224/73153Bump and layer connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/812Applying energy for connecting
    • H01L2224/8121Applying energy for connecting using a reflow oven
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818Bonding techniques
    • H01L2224/81801Soldering or alloying
    • H01L2224/81815Reflow soldering
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838Bonding techniques
    • H01L2224/8385Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/83851Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester being an anisotropic conductive adhesive
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/544Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01004Beryllium [Be]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01057Lanthanum [La]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01068Erbium [Er]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01077Iridium [Ir]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01078Platinum [Pt]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01079Gold [Au]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/102Material of the semiconductor or solid state bodies
    • H01L2924/1025Semiconducting materials
    • H01L2924/10251Elemental semiconductors, i.e. Group IV
    • H01L2924/10253Silicon [Si]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/12Passive devices, e.g. 2 terminal devices
    • H01L2924/1204Optical Diode
    • H01L2924/12042LASER
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1301Thyristor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1301Thyristor
    • H01L2924/13034Silicon Controlled Rectifier [SCR]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1305Bipolar Junction Transistor [BJT]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1305Bipolar Junction Transistor [BJT]
    • H01L2924/13055Insulated gate bipolar transistor [IGBT]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1306Field-effect transistor [FET]
    • H01L2924/13091Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/301Electrical effects
    • H01L2924/3025Electromagnetic shielding

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Physics & Mathematics (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Die Bonding (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

一种芯片尺度封装,具有一个金属氧化物半导体场效应管管芯,此管芯具有一个顶电极表面(37),其被一层光敏液态环氧树脂(111)所覆盖,环氧树脂被光刻成图案以使电极(37)的一部分曝露在外,并用作钝化层或焊料掩模。在留下的液态环氧树脂层(111)的一部分上形成可焊接的接触层(40)。每个单独的管芯(30)以漏极边朝下安装在一金属夹片(100)内,或者以漏极边朝下安装在一个壳内,此时漏极(34)与一个从壳底(101)伸出的法兰边(105)处在同一平面内。

Description

芯片尺度表面安装器件及其制造方法
发明背景
本发明涉及半导体器件,更具体地说,涉及一种新型半导体器件的低成本制造方法。
半导体器件和它们外壳是广为人知的。在先有技术的器件中,外壳的面积常常比半导体器件的面积大好多倍。另外,在许多现有的半导体器件封装中,热量只是从管芯的一面(通常是底面)散出。还有,在当前的封装中,由于采用的是单个器件的处理方法而使制造过程变得很昂贵。
更具体地说,目前的半导体器件(特别是功率MOS门器件)中,顶面接触件(源极)一般是包含1.0%硅的铝接触件(以后就称为铝接触件)。之所以采用铝接触件是因为它很适合于晶片的制造工艺过程。然而,由于很难与这种铝接触件形成电连接,通常要采用一种导线连接工艺,将导线通过超声方法连到下面的铝接触件上。这些导线固定连接点的面积很有限,因而电阻源(RDSON)和工作过程中产生的热量也不大。但是,如美国专利5,451,544等所表明的那样,底部漏极接触件一般是一个三金属片,它很容易焊接或用其它方法电连接到一个大面积接触面上,而不必用导线连接的方式。热量主要是在背接触面处从硅管芯上散出去,虽然大部分热量是产生在顶面的连接点和导线连接处。
还知道,可以把可焊接的顶面接触件做在管芯的顶面上,如美国专利5,047,833所示。然而,与管芯面积相比,用于这种可焊接顶面接触件结构的封装具有很大的“占地面积”。
希望封装结构及其制造工艺能做到对同样的管芯采用较小的封装,而同时改善其电性能(如MOS门半导体器件的RDSON)。同时还希望生产这类器件能采用容许批量处理的工艺,并减少生产线上的设备和降低成本。
发明概要
根据本发明的一种形式,将MOS门器件晶片的源边用一层钝化层盖住,最好是用光敏液态环氧,或一层氮化硅等材料。采用旋转,屏蔽,或其它方式将液态环氧淀积在晶片表面上而对晶片进行涂复。然后让材料干燥,并用标准的光刻技术让已涂复的晶片曝光以使晶片成象,同时在钝化层上形成一些开孔,以产生一些底层源金属的间隔曝光表面区域和一个类似的开口,将每个管芯的底层门电极曝光在晶片上。因此,这种新型的钝化层不仅用作普通的钝化层,而且还用作涂敷抗蚀剂(如需要的话)和焊料模,标出并形成焊料区。新型钝化层中的开口可以做成一直贯穿一层普通的可焊接的底层上部金属,如钛/钨/镍/银金属。或者,如果底层金属是更为普通的铝金属,则可将已曝光的铝镀上镍和金或其它的金属,以形成一个可焊接的表面,这时采用钝化层作为一种涂敷抗蚀剂。与将普通的导线固定到铝电极的高电阻连接相比,涂敷金属部分的顶面是容易焊接或者与低电阻接触的。
源极接触区可能具有各种几何形状,甚至可以构成一个单一的大面积区域。
然后将晶片锯成或用其它方法分成单个的管芯。接着将单个管芯的源边朝下,并采用导电环氧或焊料等将U形或杯形的经部分涂敷的漏极与管芯的可焊接漏极边相连,以将漏极固定于管芯的底漏极。漏极的腿的底部与管芯的源边表面(即接触件伸出部分的顶端)处在同一平面内。然后将管芯的外表面从上面塑封在一个模盘内。可以把大量具有这种漏极的管芯同时塑封在一个模盘内。
可以用一片惰性材料,或者将组件的全部或一部分从上面塑封起来以保护固定材料。生产中可以采用一个铅框或连续的带条来制造这些部件,或者将各器件塑封在单一的块中并从该块中将器件单分出来。
塑封后对器件进行测试并用激光打上标记,然后再锯在单个的器件。
附图简介
图1是一个可按本发明进行封装的单个功率MOSFET管芯的顶视图。
图2是沿图1的2-2线的剖视图。
图3是图1的管芯按本发明处理后的顶视图,它包含一些分离的“可焊接的”源接触区和一个“可焊接的”门区。
图4是沿图3的4-4线的剖视图。
图5是具有改变的源接触模式的象图3那样的管芯的视图。
图6是具有更大面积的“可焊接”源接触模式的象图3和5那样的管芯的视图。
图7是利用本发明的工艺形成的另一种接触件布局(带角门)的顶视图。
图8是沿图7的8-8线的剖视图。
图9是本发明一种漏极夹片的第一种形式的透视图。
图10是图9的漏极夹片的顶视图,其中模塑块的开口形成于夹片内。
图11是图3和4的管芯以及图9的夹片的局部底视图。
图12是沿图11的12-12线剖开的图11的剖视图。
图13是将图11和12从上面塑封到横盘后的部装图。
图14是沿图13的14-14线剖开的图13的剖面图。
图15是沿图13的15-15线剖开的图13的剖面图。
图16是漏极夹片的另一种具体实施装置的透视图。
图17是图16的夹片的顶视图。
图18是图16和17的夹片组件的底视图,其中的管芯是图3和图4那种普通类型的管芯经过从上面塑封。
图19是沿图18的19-19线切开的剖面图。
图20是一种杯形漏极夹片的底视图,其中管芯的布局为图7和图8所示。
图21是沿图20的21-21线切开的剖面图。
图22表示在MOSFET管芯分开之前的一个晶片。
图23表示在图22的晶片源极表面上形成一个钝化层并作出一定图形的各工艺步骤。
图24表示在图23的钝化层顶部涂敷金属的过程。
附图的详细描述
本发明为在管芯的两对面具有功率电极或其它电极的那类半导体管芯提供一种新型的封装,并能以低成本的制造方法使两个电极的表面安装在一个公共的支撑面(例如在印刷电路板的金属化图案)上。虽然本发明是参照一种垂直形导电功率MOSFET(一面上有门和源电极,相对的一面有漏极)来描述的,但本发明同样可用于IGBT,闸流晶体管,二极管,及各种类似的布局。
因此,正如我们要将看到的,一种新型的管芯夹片至少围绕并接触一部分背面电极(MOSFET中的一个漏极),同时夹片的至少一条腿伸出管芯的边缘,并终止于一个平面内,此平面与前面接触件(MOSFET的门极和源极)同平面,但与它彼此绝缘。因此,这种器件能围绕管芯和夹片的背面和侧面从上面模塑,以将所有管芯电极的处在同一平面内的平的可焊接接触面座安置在一个安装表面上。
所有顶部接触面都是采用一个新型的焊接模来形成的,以在管芯顶面形成容易焊接的接触面,这时管芯还处在晶片阶段。然后将漏极夹片与分开后的管芯相连并经批量模塑工艺从上面模制。
图1示出一种可应用本发明的典型功率MOSFET30。管芯30可以是如美国专利5,795,793中所示的那种类型,但也可以是具有一个结的任何种类的管芯,这个结包含硅基体31,顶层铝(即含1.0%硅的铝)源电极32,一个铝门电极33和一个底层体漏极34(它可以是一个普通的易于焊接的三元金属)。顶面铝层可以是任何其它适宜的金属材料。通常利用引线接合将铝电极32和33连起来。
下面将会谈到,按本发明要将一些易于焊接的接触柱36固定到(或形成在)源极上,且如图3和4所示,接触柱37被固定在门电极33上。对于银顶金属管芯,接触柱36和37稍稍比钝化层的厚度小一点;而对于镀铝顶金属管芯,则为钝化层厚度的一半左右。平的接触顶面处在一个平面内。与这些接触面的触点是由焊膏形成的,焊膏的最小可印刷厚度约为层38厚度的4至5倍。
接触件36的图形可取不同的形式,如图5、11、18所示的那些。另外,对图6、7、8的管芯,也可采用一个大面积可焊接接触件,如源接触件40或41。形成接触件36、37和40的金属化工艺将在后面描述。
在形成具有如图3至8所示管芯的新型封装时,要采用如图9所示的新形导电涂敷(或部分涂敷)金属夹片45。夹片45可以是一种铜合金,且至少有部分镀银的表面,在此表面上制成与其它表面的接触。
夹片45具有普通的“U形”形状,其腿46很短,如从表面47测量至接触柱36、37的自由表面,再加上粘接剂(用来将漏极连到夹片的薄平腹板48的经涂敷的内表面47)的厚度,腿46的长度稍微比管芯31的厚度大一些。例如,夹片沿腿46整个长度的总厚度为0.7mm,而从表面47至腿46自由端的长度约为0.39mm。两腿46之间的距离与管芯的尺寸有关,如对于International Rectifier Corporation的尺寸为4.6的管芯,采用5.6mm的距离,每条腿46的总宽度约为1.5mm
也可以在夹片45上形成模塑锁眼48和49,如图10所示。
按照本发明的一种形式,管芯30的可焊接底面漏极34是用导电胶60电连接并固定到漏极夹片45的经过镀金属的内表面上,如图12所示。这种胶可以是适当固化的加银环氧树脂材料。在管芯30的侧边和夹片45的腿46的相对边留有间隙61和62。
此结构的尺寸应控制成使得腿46的自由表面(漏极连接部)与接触柱36和37自由表面处在同一平面内。
以后就如图13、14和15所示,将图11和12的器件用模塑料70封装在一个模塑盘内。模塑料70处于夹片45的整个外露表面之上,但不包括腿46的自由外表面。如图13和15所示,模塑料填入隙缝61和62中。现在就可以把器件表面安装到印刷电路板的导线上,这些导线与接触件36、37和46对齐。
图16至19为采用一种不同夹片形状的本发明的另一种实施装置。图16和17的夹片80有一块腹板81和三个分段的伸出腿82、83和84。首先把一个具有伸出接触件36和37的管芯30在其漏极触片(未示)处与腹板81粘结(如图18和19所示),使得接触件36、37和漏极夹片伸出部分82、83及84处于一个共同的平面内。然后在一个合适的模塑盘内用模塑料70在器件上进行模塑。
图20和21表示本发明的另一种实施装置,其中将图7和8的管芯安装在杯形夹片100内,此夹片是用镀银的铜合金制成的。夹片100的内部区域的长度和宽度都比管芯30大些,且管芯30的底面漏极用加银的(导电)环氧树脂102与腹板的内表面101(图21)相连。环氧树脂被固化。最好环绕管芯边缘施加一圈低应力高粘结性的环氧树脂103,以将封装密封并增加其结构强度。
可焊接接触件40的顶面与漏极夹片伸出的表面105处在同一平面内。因而全部接触件105,40和37都与印刷电路板上的接线对齐。漏极接触件可以是任何适当的形状,而且需要的话可以构成一个单一的接触边。
图22至24表示在普通管芯铝电极上形成导电柱的一种新工艺。图中标出了在管芯分开前在晶片110内的一些相同的管芯,每个管芯有一个门电极37和分开的源电极(沿有标号)。虽然仍然是晶片的形式,但晶片110的顶面被涂上了一个可光成象的焊料掩模111。掩模111是一种光敏液态环氧树脂,它用作钝化层,一种涂敷抗蚀剂(如需要的话)和一种焊料掩模,用来确定和形成焊料区。但也可以采用其它的掩模材料,如氮化硅等。利用普通的光栅,可以通过掩模在管芯顶层金属上的底层源极和门极接触件上形成许多开孔111a至111d。也可以采用激光刻蚀工艺来形成这些开孔。
如图24所示,在此之后将一系列的金属112镀到晶片的顶面上,且镀层与源极32的金属(以及其它的电极)相粘结,构成与源极的接触件112a至112d,以及一个类似的至门极的接触件,源极是通过开孔111a至111d而露在外面的。金属112a至112d的第一层可以是镍(它与铝接触良好),下一层是金。在镍下面也可以是一层铜或锡等,最后是一个容易焊接的金属顶面(如银)。
然后将晶片锯开,让管芯沿线112和113分离,使管芯分开。典型的管芯30的外形为图3至8所示,而且有一些可焊接的源极接触件和门极接触件,它们都伸到绝缘表面50的上面。
此后将被分开的管芯的漏极源极边朝下置于导电夹片内,夹片的内部镀有银或其它的导电层。把管芯用普通的粘固材料(如前面讲过的导电环氧树脂)粘到夹片上。夹片/外罩可以做成铅框的形式,以后可将器件从铅框中分离出来。
虽然本发明是参照一些特定的实施装置来描述的,但本领域技术人员显然明白,可以对它们作许多的修改和变型。因此,本发明并不局限于上面的公布具体内容,其范围将由下面的权利要求书予以界定。

Claims (15)

1.一种半导体器件封装,包括具有平行的顶面和底面的半导体器件管芯;所述顶面有一个平面金属电极,所述底面有一个可焊接的平面金属电极;在该平面金属电极的至少第一部分上形成有至少一层可焊接的导电层,所述至少一层可焊接的导电层有一个上平表面;一个金属夹片具有一个平腹板部分和至少一个从平腹板部分的边缘延伸出去的周边缘部分;所述腹板的底面以面对面接触的方式与管芯底面上的可焊接平金属电极电连接;所述夹片的周边缘部分延伸至管芯边缘的上方并与之分开,且终止于夹片边缘表面,此边缘表面处在与上述至少一个可焊接平面金属电极的上表面平面相平行的平面内且与该平面绝缘开,这样就可以把该夹片边缘表面和该至少一个可焊接平面金属电极安装在一个支撑表面上的金属化图案上。
2.如权利要求1所述的封装,其中一些可焊接的平面金属柱形电极与所述金属功率电极相连,且全部终止于所述上平面表面的平面内。
3.如权利要求1或2所述的封装,其中在所述管芯上表面上还包含一个第二平面金属电极,该电极包括一个控制电极;且第二可焊接平面金属电极有一个上表面,它与该至少一个可焊接平面金属电极的上表面处在同一个平面内。
4.如权利要求1至3所述的器件,其中所述至少一个可焊接平面金属电极包含一层的与所述金属电极相连镍和一种与所述镍层顶面相连的易焊金属。
5.如权利要求1至3所述的器件,其中所有所述可焊平面电极包含一层与它下面的金属电极相连的镍和一种与镍层顶面相连的易焊金属。
6.如权利要求1至5所述的器件,还包含一种导电环氧树脂,它将所述腹板底面连接到所述管芯底面。
7.如权利要求1至6所述的器件,其中所述夹片具有第二周边缘部分,其处在离开该至少一个周边缘部分的夹片反面上,该至少一个周边缘部分延伸至所述管芯的相对边缘上面并与之分开,同时终止于与该至少一个周边缘部分终止平面相平行的平面内。
8.如权利要求1至6所述的器件,其中所述夹片为杯形结构,所述周边缘是一个连续的边缘,环绕着所述管芯的外部并与之分开。
9.如权利要求8所述的器件,其中所述管芯和周边缘之间的空隙由绝缘熔珠填充。
10.在具有金属顶电极结构的半导体管芯上形成可焊顶面的方法:该方法包括在包含一些具有所述金属顶电极结构的相同管芯的晶片表面上淀积一个掩模层;用光刻方法在这些管芯的每一个上在所述掩模层中开出至少第一和第二两个开孔;淀积第一金属层,它与所述掩模层上方的金属电极相连,并位于与至少由第一和第二开孔暴露的金属电极表面上;在第一金属层上淀积可焊接的第二金属层;除去掩模层和位于其上的第一和第二金属层,保留形成在至少是第一和第二开孔中的金属,以在由于除去掩模层而外露的硅表面上方形成一个钝化绝缘层,并让金属保留在该至少第一和第二开孔中并突出钝化绝缘层的表面之外,且终止于钝化层上方的一个公共平面内;此后由所述晶片分成所述管芯。
11.如权利要求10所述的方法,其中所述晶片有一个公共的可焊接电极,该电极形成于它的整个底面上。
12.如权利要求10和11所述的方法,其中所述顶面铝电极被分割成第一和第二绝缘部分;该至少第一和第二开孔分别形成于第一和第二部分的上方。
13.如权利要求12所述的方法,其中所述至少第一和第二开孔包含一些处于第一部分上方的开孔,用来确定一些与第一部分相连的导电柱。
14.如权利要求12和13所述的方法,其中所述第一和第二部分分别为一个功率金属氧化物半导体场效应晶体管的源极和门极。
15.如权利要求10至14的所述的方法,其中所述掩模层是光敏聚酰亚胺。
CNB018100015A 2000-04-04 2001-03-29 芯片尺度表面安装器件及其制造方法 Expired - Fee Related CN1316577C (zh)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US19452200P 2000-04-04 2000-04-04
US60/194,522 2000-04-04
US09/819,774 US6624522B2 (en) 2000-04-04 2001-03-28 Chip scale surface mounted device and process of manufacture
US09/819,774 2001-03-28

Publications (2)

Publication Number Publication Date
CN1430791A true CN1430791A (zh) 2003-07-16
CN1316577C CN1316577C (zh) 2007-05-16

Family

ID=26890112

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB018100015A Expired - Fee Related CN1316577C (zh) 2000-04-04 2001-03-29 芯片尺度表面安装器件及其制造方法

Country Status (8)

Country Link
US (6) US6624522B2 (zh)
EP (1) EP1287553A4 (zh)
JP (3) JP3768158B2 (zh)
CN (1) CN1316577C (zh)
AU (1) AU2001249587A1 (zh)
HK (1) HK1057648A1 (zh)
TW (1) TW503487B (zh)
WO (1) WO2001075961A1 (zh)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101964332A (zh) * 2009-07-22 2011-02-02 万国半导体股份有限公司 芯片级表面封装的半导体器件封装及其制备过程
CN103420331A (zh) * 2012-05-23 2013-12-04 飞思卡尔半导体公司 腔式半导体封装及其封装方法
CN104900546A (zh) * 2015-05-04 2015-09-09 嘉兴斯达半导体股份有限公司 一种功率模块的封装结构
CN104916597A (zh) * 2014-03-14 2015-09-16 尼克森微电子股份有限公司 晶圆级扇出芯片的封装方法及封装结构
CN105448871A (zh) * 2014-08-18 2016-03-30 万国半导体股份有限公司 功率半导体器件及制备方法
CN107026140A (zh) * 2015-11-09 2017-08-08 罗伯特·博世有限公司 具有可焊接的正面的半导体芯片及制造半导体芯片的方法
WO2018036319A1 (zh) * 2016-08-22 2018-03-01 杰群电子科技(东莞)有限公司 半导体封装结构及加工方法

Families Citing this family (155)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6133634A (en) 1998-08-05 2000-10-17 Fairchild Semiconductor Corporation High performance flip chip package
US6624522B2 (en) * 2000-04-04 2003-09-23 International Rectifier Corporation Chip scale surface mounted device and process of manufacture
US6661082B1 (en) * 2000-07-19 2003-12-09 Fairchild Semiconductor Corporation Flip chip substrate design
US6777786B2 (en) * 2001-03-12 2004-08-17 Fairchild Semiconductor Corporation Semiconductor device including stacked dies mounted on a leadframe
US6930397B2 (en) * 2001-03-28 2005-08-16 International Rectifier Corporation Surface mounted package with die bottom spaced from support board
US7119447B2 (en) * 2001-03-28 2006-10-10 International Rectifier Corporation Direct fet device for high frequency application
US7476964B2 (en) * 2001-06-18 2009-01-13 International Rectifier Corporation High voltage semiconductor device housing with increased clearance between housing can and die for improved flux flushing
US6784540B2 (en) 2001-10-10 2004-08-31 International Rectifier Corp. Semiconductor device package with improved cooling
US6891256B2 (en) * 2001-10-22 2005-05-10 Fairchild Semiconductor Corporation Thin, thermally enhanced flip chip in a leaded molded package
JP3627738B2 (ja) * 2001-12-27 2005-03-09 株式会社デンソー 半導体装置
US6677669B2 (en) * 2002-01-18 2004-01-13 International Rectifier Corporation Semiconductor package including two semiconductor die disposed within a common clip
US7122884B2 (en) * 2002-04-16 2006-10-17 Fairchild Semiconductor Corporation Robust leaded molded packages and methods for forming the same
GB0213094D0 (en) * 2002-06-07 2002-07-17 Power Innovations Ltd Lead frame
US6919599B2 (en) * 2002-06-28 2005-07-19 International Rectifier Corporation Short channel trench MOSFET with reduced gate charge
JP3942500B2 (ja) 2002-07-02 2007-07-11 Necエレクトロニクス株式会社 半導体装置の製造方法
JP3853263B2 (ja) 2002-07-08 2006-12-06 Necエレクトロニクス株式会社 半導体装置
US7579697B2 (en) * 2002-07-15 2009-08-25 International Rectifier Corporation Arrangement for high frequency application
US7397137B2 (en) * 2002-07-15 2008-07-08 International Rectifier Corporation Direct FET device for high frequency application
US7061077B2 (en) * 2002-08-30 2006-06-13 Fairchild Semiconductor Corporation Substrate based unmolded package including lead frame structure and semiconductor die
US6777800B2 (en) * 2002-09-30 2004-08-17 Fairchild Semiconductor Corporation Semiconductor die package including drain clip
US6841865B2 (en) * 2002-11-22 2005-01-11 International Rectifier Corporation Semiconductor device having clips for connecting to external elements
US7088004B2 (en) * 2002-11-27 2006-08-08 International Rectifier Corporation Flip-chip device having conductive connectors
US6867481B2 (en) * 2003-04-11 2005-03-15 Fairchild Semiconductor Corporation Lead frame structure with aperture or groove for flip chip in a leaded molded package
US6946744B2 (en) * 2003-04-24 2005-09-20 Power-One Limited System and method of reducing die attach stress and strain
JP3759131B2 (ja) 2003-07-31 2006-03-22 Necエレクトロニクス株式会社 リードレスパッケージ型半導体装置とその製造方法
US7315081B2 (en) * 2003-10-24 2008-01-01 International Rectifier Corporation Semiconductor device package utilizing proud interconnect material
JP4312616B2 (ja) 2004-01-26 2009-08-12 Necエレクトロニクス株式会社 半導体装置
US8368211B2 (en) 2004-03-11 2013-02-05 International Rectifier Corporation Solderable top metalization and passivation for source mounted package
US20050269677A1 (en) * 2004-05-28 2005-12-08 Martin Standing Preparation of front contact for surface mounting
US7678680B2 (en) * 2004-06-03 2010-03-16 International Rectifier Corporation Semiconductor device with reduced contact resistance
US8390131B2 (en) 2004-06-03 2013-03-05 International Rectifier Corporation Semiconductor device with reduced contact resistance
US7235877B2 (en) * 2004-09-23 2007-06-26 International Rectifier Corporation Redistributed solder pads using etched lead frame
JP4153932B2 (ja) * 2004-09-24 2008-09-24 株式会社東芝 半導体装置および半導体装置の製造方法
US7692316B2 (en) * 2004-10-01 2010-04-06 International Rectifier Corporation Audio amplifier assembly
US7812441B2 (en) * 2004-10-21 2010-10-12 Siliconix Technology C.V. Schottky diode with improved surge capability
TWI278090B (en) * 2004-10-21 2007-04-01 Int Rectifier Corp Solderable top metal for SiC device
JP2006222298A (ja) 2005-02-10 2006-08-24 Renesas Technology Corp 半導体装置およびその製造方法
US7394151B2 (en) * 2005-02-15 2008-07-01 Alpha & Omega Semiconductor Limited Semiconductor package with plated connection
US7834376B2 (en) 2005-03-04 2010-11-16 Siliconix Technology C. V. Power semiconductor switch
US9419092B2 (en) 2005-03-04 2016-08-16 Vishay-Siliconix Termination for SiC trench devices
US7524701B2 (en) * 2005-04-20 2009-04-28 International Rectifier Corporation Chip-scale package
US7230333B2 (en) 2005-04-21 2007-06-12 International Rectifier Corporation Semiconductor package
US8466546B2 (en) * 2005-04-22 2013-06-18 International Rectifier Corporation Chip-scale package
JP4490861B2 (ja) * 2005-04-25 2010-06-30 日立協和エンジニアリング株式会社 基板
US7682935B2 (en) * 2005-06-08 2010-03-23 International Rectifier Corporation Process of manufacture of ultra thin semiconductor wafers with bonded conductive hard carrier
US20070013053A1 (en) * 2005-07-12 2007-01-18 Peter Chou Semiconductor device and method for manufacturing a semiconductor device
US7514769B1 (en) * 2005-08-13 2009-04-07 National Semiconductor Corporation Micro surface mount die package and method
US7504733B2 (en) 2005-08-17 2009-03-17 Ciclon Semiconductor Device Corp. Semiconductor die package
EP1925028B1 (en) 2005-09-02 2020-11-11 Infineon Technologies Americas Corp. Protective barrier layer for semiconductor device electrodes
US7569927B2 (en) * 2005-09-21 2009-08-04 Microsemi Corporation RF power transistor package
US7560808B2 (en) * 2005-10-19 2009-07-14 Texas Instruments Incorporated Chip scale power LDMOS device
US8368165B2 (en) 2005-10-20 2013-02-05 Siliconix Technology C. V. Silicon carbide Schottky diode
US7786558B2 (en) * 2005-10-20 2010-08-31 Infineon Technologies Ag Semiconductor component and methods to produce a semiconductor component
US7968984B2 (en) 2005-10-25 2011-06-28 International Rectifier Corporation Universal pad arrangement for surface mounted semiconductor devices
US8089147B2 (en) * 2005-11-02 2012-01-03 International Rectifier Corporation IMS formed as can for semiconductor housing
US20070158796A1 (en) * 2005-12-09 2007-07-12 International Rectifier Corporation Semiconductor package
DE102005061015B4 (de) * 2005-12-19 2008-03-13 Infineon Technologies Ag Verfahren zum Herstellen eines Halbleiterbauteils mit einem vertikalen Halbleiterbauelement
US8018056B2 (en) * 2005-12-21 2011-09-13 International Rectifier Corporation Package for high power density devices
US8698294B2 (en) * 2006-01-24 2014-04-15 Stats Chippac Ltd. Integrated circuit package system including wide flange leadframe
US7749877B2 (en) * 2006-03-07 2010-07-06 Siliconix Technology C. V. Process for forming Schottky rectifier with PtNi silicide Schottky barrier
US7446375B2 (en) * 2006-03-14 2008-11-04 Ciclon Semiconductor Device Corp. Quasi-vertical LDMOS device having closed cell layout
US20070215997A1 (en) * 2006-03-17 2007-09-20 Martin Standing Chip-scale package
US7663212B2 (en) * 2006-03-21 2010-02-16 Infineon Technologies Ag Electronic component having exposed surfaces
US20070222087A1 (en) * 2006-03-27 2007-09-27 Sangdo Lee Semiconductor device with solderable loop contacts
US7923289B2 (en) * 2006-03-31 2011-04-12 International Rectifier Corporation Process for fabricating a semiconductor package
US7554188B2 (en) 2006-04-13 2009-06-30 International Rectifier Corporation Low inductance bond-wireless co-package for high power density devices, especially for IGBTs and diodes
US7541681B2 (en) * 2006-05-04 2009-06-02 Infineon Technologies Ag Interconnection structure, electronic component and method of manufacturing the same
US7757392B2 (en) 2006-05-17 2010-07-20 Infineon Technologies Ag Method of producing an electronic component
US7476978B2 (en) * 2006-05-17 2009-01-13 Infineon Technologies, Ag Electronic component having a semiconductor power device
US7626262B2 (en) * 2006-06-14 2009-12-01 Infineon Technologies Ag Electrically conductive connection, electronic component and method for their production
US9627552B2 (en) 2006-07-31 2017-04-18 Vishay-Siliconix Molybdenum barrier metal for SiC Schottky diode and process of manufacture
US7719096B2 (en) * 2006-08-11 2010-05-18 Vishay General Semiconductor Llc Semiconductor device and method for manufacturing a semiconductor device
DE102006044690B4 (de) * 2006-09-22 2010-07-29 Infineon Technologies Ag Elektronisches Bauteil und Verfahren zum Herstellen
DE102006047761A1 (de) * 2006-10-06 2008-04-10 Infineon Technologies Ag Halbleiterbauteil und Verfahren zu dessen Herstellung
KR100818101B1 (ko) * 2006-11-08 2008-03-31 주식회사 하이닉스반도체 웨이퍼 레벨 칩 사이즈 패키지
US8552543B2 (en) * 2006-11-13 2013-10-08 International Rectifier Corporation Semiconductor package
US8106501B2 (en) 2008-12-12 2012-01-31 Fairchild Semiconductor Corporation Semiconductor die package including low stress configuration
DE102007007142B4 (de) * 2007-02-09 2008-11-13 Infineon Technologies Ag Nutzen, Halbleiterbauteil sowie Verfahren zu deren Herstellung
US7880280B2 (en) * 2007-02-16 2011-02-01 Infineon Technologies Ag Electronic component and method for manufacturing an electronic component
US9147644B2 (en) 2008-02-26 2015-09-29 International Rectifier Corporation Semiconductor device and passive component integration in a semiconductor package
US8786072B2 (en) * 2007-02-27 2014-07-22 International Rectifier Corporation Semiconductor package
US8083832B2 (en) * 2007-02-27 2011-12-27 International Rectifier Corporation Paste for forming an interconnect and interconnect formed from the paste
US7447041B2 (en) * 2007-03-01 2008-11-04 Delphi Technologies, Inc. Compression connection for vertical IC packages
US8686554B2 (en) * 2007-03-13 2014-04-01 International Rectifier Corporation Vertically mountable semiconductor device package
JP2008235837A (ja) * 2007-03-23 2008-10-02 Matsushita Electric Ind Co Ltd 半導体装置及びその製造方法
GB2455940B (en) 2007-03-30 2010-11-24 Cambridge Semiconductor Ltd Forward power converter controllers
US7759777B2 (en) * 2007-04-16 2010-07-20 Infineon Technologies Ag Semiconductor module
US7838985B2 (en) * 2007-07-12 2010-11-23 Vishay General Semiconductor Llc Semiconductor assembly that includes a power semiconductor die located on a cell defined by first and second patterned polymer layers
US7915728B2 (en) * 2007-07-12 2011-03-29 Vishay General Semiconductor Llc Subassembly that includes a power semiconductor die and a heat sink having an exposed surface portion thereof
US7879652B2 (en) * 2007-07-26 2011-02-01 Infineon Technologies Ag Semiconductor module
US20090057855A1 (en) * 2007-08-30 2009-03-05 Maria Clemens Quinones Semiconductor die package including stand off structures
US8421214B2 (en) * 2007-10-10 2013-04-16 Vishay General Semiconductor Llc Semiconductor device and method for manufacturing a semiconductor device
US7701065B2 (en) * 2007-10-26 2010-04-20 Infineon Technologies Ag Device including a semiconductor chip having a plurality of electrodes
JP5153316B2 (ja) * 2007-12-21 2013-02-27 新光電気工業株式会社 半導体パッケージ用放熱板およびそのめっき方法
US8426960B2 (en) * 2007-12-21 2013-04-23 Alpha & Omega Semiconductor, Inc. Wafer level chip scale packaging
US7799614B2 (en) * 2007-12-21 2010-09-21 Infineon Technologies Ag Method of fabricating a power electronic device
JP2009164442A (ja) * 2008-01-09 2009-07-23 Nec Electronics Corp 半導体装置
US8143729B2 (en) * 2008-01-25 2012-03-27 International Rectifier Corporation Autoclave capable chip-scale package
US7955893B2 (en) * 2008-01-31 2011-06-07 Alpha & Omega Semiconductor, Ltd Wafer level chip scale package and process of manufacture
US7968378B2 (en) * 2008-02-06 2011-06-28 Infineon Technologies Ag Electronic device
US7972906B2 (en) * 2008-03-07 2011-07-05 Fairchild Semiconductor Corporation Semiconductor die package including exposed connections
US8637341B2 (en) * 2008-03-12 2014-01-28 Infineon Technologies Ag Semiconductor module
US7759163B2 (en) * 2008-04-18 2010-07-20 Infineon Technologies Ag Semiconductor module
US8680658B2 (en) * 2008-05-30 2014-03-25 Alpha And Omega Semiconductor Incorporated Conductive clip for semiconductor device package
US8053891B2 (en) * 2008-06-30 2011-11-08 Alpha And Omega Semiconductor Incorporated Standing chip scale package
US7932180B2 (en) 2008-07-07 2011-04-26 Infineon Technologies Ag Manufacturing a semiconductor device via etching a semiconductor chip to a first layer
US7910992B2 (en) * 2008-07-15 2011-03-22 Maxim Integrated Products, Inc. Vertical MOSFET with through-body via for gate
US8441804B2 (en) 2008-07-25 2013-05-14 Infineon Technologies Ag Semiconductor device and method of manufacturing a semiconductor device
US8110912B2 (en) 2008-07-31 2012-02-07 Infineon Technologies Ag Semiconductor device
US7767495B2 (en) 2008-08-25 2010-08-03 Infineon Technologies Ag Method for the fabrication of semiconductor devices including attaching chips to each other with a dielectric material
US7982292B2 (en) 2008-08-25 2011-07-19 Infineon Technologies Ag Semiconductor device
US7923350B2 (en) * 2008-09-09 2011-04-12 Infineon Technologies Ag Method of manufacturing a semiconductor device including etching to etch stop regions
US8373257B2 (en) * 2008-09-25 2013-02-12 Alpha & Omega Semiconductor Incorporated Top exposed clip with window array
US8710665B2 (en) 2008-10-06 2014-04-29 Infineon Technologies Ag Electronic component, a semiconductor wafer and a method for producing an electronic component
US7898067B2 (en) * 2008-10-31 2011-03-01 Fairchild Semiconductor Corporaton Pre-molded, clip-bonded multi-die semiconductor package
US7994646B2 (en) * 2008-12-17 2011-08-09 Infineon Technologies Ag Semiconductor device
US7851856B2 (en) * 2008-12-29 2010-12-14 Alpha & Omega Semiconductor, Ltd True CSP power MOSFET based on bottom-source LDMOS
US8049312B2 (en) * 2009-01-12 2011-11-01 Texas Instruments Incorporated Semiconductor device package and method of assembly thereof
JP5420274B2 (ja) 2009-03-02 2014-02-19 パナソニック株式会社 半導体装置及びその製造方法
US8358014B2 (en) * 2009-05-28 2013-01-22 Texas Instruments Incorporated Structure and method for power field effect transistor
US8563360B2 (en) * 2009-06-08 2013-10-22 Alpha And Omega Semiconductor, Inc. Power semiconductor device package and fabrication method
JP5500936B2 (ja) * 2009-10-06 2014-05-21 イビデン株式会社 回路基板及び半導体モジュール
US7939370B1 (en) * 2009-10-29 2011-05-10 Alpha And Omega Semiconductor Incorporated Power semiconductor package
JP2011151109A (ja) * 2010-01-20 2011-08-04 Fuji Electric Co Ltd 半導体装置およびその製造方法
JP5375708B2 (ja) * 2010-03-29 2013-12-25 パナソニック株式会社 半導体装置の製造方法
US8362606B2 (en) 2010-07-29 2013-01-29 Alpha & Omega Semiconductor, Inc. Wafer level chip scale package
EP2453476A1 (en) * 2010-11-12 2012-05-16 Nxp B.V. Semiconductor device packaging method and semiconductor device package
US20120175688A1 (en) 2011-01-10 2012-07-12 International Rectifier Corporation Semiconductor Package with Reduced On-Resistance and Top Metal Spreading Resistance with Application to Power Transistor Packaging
US8546925B2 (en) 2011-09-28 2013-10-01 Texas Instruments Incorporated Synchronous buck converter having coplanar array of contact bumps of equal volume
US8970035B2 (en) 2012-08-31 2015-03-03 Taiwan Semiconductor Manufacturing Company, Ltd. Bump structures for semiconductor package
US9202811B2 (en) * 2012-12-18 2015-12-01 Infineon Technologies Americas Corp. Cascode circuit integration of group III-N and group IV devices
US9041067B2 (en) 2013-02-11 2015-05-26 International Rectifier Corporation Integrated half-bridge circuit with low side and high side composite switches
US9070721B2 (en) 2013-03-15 2015-06-30 Semiconductor Components Industries, Llc Semiconductor devices and methods of making the same
US8865523B2 (en) * 2013-03-15 2014-10-21 Alpha & Omega Semiconductor, Inc. Semiconductor package and fabrication method thereof
JP6167397B2 (ja) * 2013-04-26 2017-07-26 パナソニックIpマネジメント株式会社 半導体装置
DE102013212446A1 (de) * 2013-06-27 2015-01-15 Zf Friedrichshafen Ag Elektrische Schaltung und Verfahren zum Herstellen einer elektrischen Schaltung zur Ansteuerung einer Last
US20150001696A1 (en) * 2013-06-28 2015-01-01 Infineon Technologies Ag Semiconductor die carrier structure and method of manufacturing the same
US9536800B2 (en) 2013-12-07 2017-01-03 Fairchild Semiconductor Corporation Packaged semiconductor devices and methods of manufacturing
US9653386B2 (en) 2014-10-16 2017-05-16 Infineon Technologies Americas Corp. Compact multi-die power semiconductor package
US9620475B2 (en) 2013-12-09 2017-04-11 Infineon Technologies Americas Corp Array based fabrication of power semiconductor package with integrated heat spreader
US9704787B2 (en) * 2014-10-16 2017-07-11 Infineon Technologies Americas Corp. Compact single-die power semiconductor package
US9570379B2 (en) 2013-12-09 2017-02-14 Infineon Technologies Americas Corp. Power semiconductor package with integrated heat spreader and partially etched conductive carrier
US9214419B2 (en) * 2014-02-28 2015-12-15 Alpha And Omega Semiconductor Incorporated Power semiconductor device and preparation method thereof
JP6287341B2 (ja) * 2014-03-03 2018-03-07 セイコーエプソン株式会社 液体吐出装置および液体吐出装置の制御方法
TWI546906B (zh) 2014-03-14 2016-08-21 尼克森微電子股份有限公司 晶圓級扇出晶片的封裝結構及封裝方法
JP2015231027A (ja) * 2014-06-06 2015-12-21 住友電気工業株式会社 半導体装置
EP3065172A1 (en) 2015-03-06 2016-09-07 Nxp B.V. Semiconductor device
DE102015205695B4 (de) * 2015-03-30 2020-09-24 Robert Bosch Gmbh Halbleiterbauelement, Kontaktanordnung und Verfahren zur Herstellung
DE102015104996B4 (de) * 2015-03-31 2020-06-18 Infineon Technologies Austria Ag Halbleitervorrichtungen mit Steuer- und Lastleitungen von entgegengesetzter Richtung
JP6598037B2 (ja) * 2015-07-01 2019-10-30 パナソニックIpマネジメント株式会社 半導体装置
US10256168B2 (en) 2016-06-12 2019-04-09 Nexperia B.V. Semiconductor device and lead frame therefor
US10128170B2 (en) 2017-01-09 2018-11-13 Silanna Asia Pte Ltd Conductive clip connection arrangements for semiconductor packages
JP6894544B2 (ja) * 2018-07-17 2021-06-30 富士電機株式会社 半導体装置の製造方法
US11355470B2 (en) 2020-02-27 2022-06-07 Amkor Technology Singapore Holding Pte. Ltd. Semiconductor device and methods of manufacturing semiconductor devices
EP4044226A1 (en) * 2021-02-16 2022-08-17 Nexperia B.V. A semiconductor device and a method of manufacturing of a semiconductor device

Family Cites Families (70)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3403438A (en) 1964-12-02 1968-10-01 Corning Glass Works Process for joining transistor chip to printed circuit
US3871014A (en) 1969-08-14 1975-03-11 Ibm Flip chip module with non-uniform solder wettable areas on the substrate
US3972062A (en) 1973-10-04 1976-07-27 Motorola, Inc. Mounting assemblies for a plurality of transistor integrated circuit chips
GB1487945A (en) 1974-11-20 1977-10-05 Ibm Semiconductor integrated circuit devices
US4454454A (en) 1983-05-13 1984-06-12 Motorola, Inc. MOSFET "H" Switch circuit for a DC motor
US4646129A (en) 1983-09-06 1987-02-24 General Electric Company Hermetic power chip packages
US4604644A (en) 1985-01-28 1986-08-05 International Business Machines Corporation Solder interconnection structure for joining semiconductor devices to substrates that have improved fatigue life, and process for making
US4639760A (en) 1986-01-21 1987-01-27 Motorola, Inc. High power RF transistor assembly
JPH0676790B2 (ja) * 1987-07-30 1994-09-28 株式会社東芝 イグナイタ
JPH07118514B2 (ja) * 1989-04-24 1995-12-18 株式会社東芝 半田バンプ型半導体装置
US5075759A (en) 1989-07-21 1991-12-24 Motorola, Inc. Surface mounting semiconductor device and method
US5182632A (en) 1989-11-22 1993-01-26 Tactical Fabs, Inc. High density multichip package with interconnect structure and heatsink
US5047833A (en) 1990-10-17 1991-09-10 International Rectifier Corporation Solderable front metal contact for MOS devices
JP2984068B2 (ja) 1991-01-31 1999-11-29 株式会社日立製作所 半導体装置の製造方法
JPH05129516A (ja) * 1991-11-01 1993-05-25 Hitachi Ltd 半導体装置
CA2089435C (en) 1992-02-14 1997-12-09 Kenzi Kobayashi Semiconductor device
JP2833326B2 (ja) 1992-03-03 1998-12-09 松下電器産業株式会社 電子部品実装接続体およびその製造方法
JPH065401A (ja) 1992-06-23 1994-01-14 Mitsubishi Electric Corp チップ型抵抗素子及び半導体装置
JPH0637143A (ja) 1992-07-15 1994-02-10 Toshiba Corp 半導体装置および半導体装置の製造方法
US5394490A (en) 1992-08-11 1995-02-28 Hitachi, Ltd. Semiconductor device having an optical waveguide interposed in the space between electrode members
US5313366A (en) 1992-08-12 1994-05-17 International Business Machines Corporation Direct chip attach module (DCAM)
JPH06244231A (ja) 1993-02-01 1994-09-02 Motorola Inc 気密半導体デバイスおよびその製造方法
US5371404A (en) 1993-02-04 1994-12-06 Motorola, Inc. Thermally conductive integrated circuit package with radio frequency shielding
JP2795788B2 (ja) 1993-02-18 1998-09-10 シャープ株式会社 半導体チップの実装方法
US5703405A (en) 1993-03-15 1997-12-30 Motorola, Inc. Integrated circuit chip formed from processing two opposing surfaces of a wafer
US5510758A (en) 1993-04-07 1996-04-23 Matsushita Electric Industrial Co., Ltd. Multilayer microstrip wiring board with a semiconductor device mounted thereon via bumps
JP3258764B2 (ja) 1993-06-01 2002-02-18 三菱電機株式会社 樹脂封止型半導体装置の製造方法ならびに外部引出用電極およびその製造方法
JPH0745620A (ja) * 1993-07-26 1995-02-14 Hitachi Ltd 半導体装置およびその製造方法並びにその実装構造体
US5397921A (en) 1993-09-03 1995-03-14 Advanced Semiconductor Assembly Technology Tab grid array
US5455456A (en) 1993-09-15 1995-10-03 Lsi Logic Corporation Integrated circuit package lid
US5451544A (en) 1993-10-15 1995-09-19 International Rectifier Corporation Method of manufacturing a back contact for semiconductor die
US5734201A (en) 1993-11-09 1998-03-31 Motorola, Inc. Low profile semiconductor device with like-sized chip and mounting substrate
US5367435A (en) 1993-11-16 1994-11-22 International Business Machines Corporation Electronic package structure and method of making same
US5454160A (en) 1993-12-03 1995-10-03 Ncr Corporation Apparatus and method for stacking integrated circuit devices
JPH07193184A (ja) 1993-12-27 1995-07-28 Fujitsu Ltd マルチチップモジュールの製造方法及びマルチチップモジュール
JP3073644B2 (ja) 1993-12-28 2000-08-07 株式会社東芝 半導体装置
US5446316A (en) * 1994-01-06 1995-08-29 Harris Corporation Hermetic package for a high power semiconductor device
US5578869A (en) * 1994-03-29 1996-11-26 Olin Corporation Components for housing an integrated circuit device
US6486003B1 (en) * 1996-12-13 2002-11-26 Tessera, Inc. Expandable interposer for a microelectronic package and method therefor
JP3377867B2 (ja) 1994-08-12 2003-02-17 京セラ株式会社 半導体素子収納用パッケージ
JP2546192B2 (ja) 1994-09-30 1996-10-23 日本電気株式会社 フィルムキャリア半導体装置
US5532512A (en) 1994-10-03 1996-07-02 General Electric Company Direct stacked and flip chip power semiconductor device structures
JP3138159B2 (ja) 1994-11-22 2001-02-26 シャープ株式会社 半導体装置、半導体装置実装体、及び半導体装置の交換方法
US5904499A (en) 1994-12-22 1999-05-18 Pace; Benedict G Package for power semiconductor chips
JPH08335653A (ja) 1995-04-07 1996-12-17 Nitto Denko Corp 半導体装置およびその製法並びに上記半導体装置の製造に用いる半導体装置用テープキャリア
US5655703A (en) 1995-05-25 1997-08-12 International Business Machines Corporation Solder hierarchy for chip attachment to substrates
US5674785A (en) 1995-11-27 1997-10-07 Micron Technology, Inc. Method of producing a single piece package for semiconductor die
US5726502A (en) 1996-04-26 1998-03-10 Motorola, Inc. Bumped semiconductor device with alignment features and method for making the same
JPH1022336A (ja) * 1996-06-28 1998-01-23 Sanyo Electric Co Ltd 半導体装置の製造方法
CN1179626A (zh) * 1996-09-05 1998-04-22 国际整流器公司 一种改进的表面封装的大功率半导体封壳及其制造方法
US5814884C1 (en) * 1996-10-24 2002-01-29 Int Rectifier Corp Commonly housed diverse semiconductor die
KR100209760B1 (ko) * 1996-12-19 1999-07-15 구본준 반도체 패키지 및 이의 제조방법
US6051888A (en) 1997-04-07 2000-04-18 Texas Instruments Incorporated Semiconductor package and method for increased thermal dissipation of flip-chip semiconductor package
KR100219806B1 (ko) * 1997-05-27 1999-09-01 윤종용 반도체장치의 플립 칩 실장형 솔더 범프의 제조방법, 이에 따라 제조되는 솔더범프 및 그 분석방법
JPH1154673A (ja) 1997-07-31 1999-02-26 Nec Kansai Ltd 半導体装置
GB9725960D0 (en) 1997-12-08 1998-02-04 Westinghouse Brake & Signal Encapsulating semiconductor chips
JP3654485B2 (ja) * 1997-12-26 2005-06-02 富士通株式会社 半導体装置の製造方法
JP3097644B2 (ja) * 1998-01-06 2000-10-10 日本電気株式会社 半導体装置接続構造及び接続方法
US6423623B1 (en) * 1998-06-09 2002-07-23 Fairchild Semiconductor Corporation Low Resistance package for semiconductor devices
EP0966038A3 (en) * 1998-06-15 2001-02-28 Ford Motor Company Bonding of semiconductor power devices
US6133634A (en) 1998-08-05 2000-10-17 Fairchild Semiconductor Corporation High performance flip chip package
EP0978871A3 (en) * 1998-08-05 2001-12-19 Harris Corporation A low power packaging design
US6268275B1 (en) * 1998-10-08 2001-07-31 Micron Technology, Inc. Method of locating conductive spheres utilizing screen and hopper of solder balls
KR20000057810A (ko) * 1999-01-28 2000-09-25 가나이 쓰토무 반도체 장치
JP4408475B2 (ja) * 1999-02-23 2010-02-03 三洋電機株式会社 ボンディングワイヤを採用しない半導体装置
US6744124B1 (en) * 1999-12-10 2004-06-01 Siliconix Incorporated Semiconductor die package including cup-shaped leadframe
US6624522B2 (en) 2000-04-04 2003-09-23 International Rectifier Corporation Chip scale surface mounted device and process of manufacture
US6362087B1 (en) * 2000-05-05 2002-03-26 Aptos Corporation Method for fabricating a microelectronic fabrication having formed therein a redistribution structure
JP3467454B2 (ja) 2000-06-05 2003-11-17 Necエレクトロニクス株式会社 半導体装置の製造方法
US6391687B1 (en) 2000-10-31 2002-05-21 Fairchild Semiconductor Corporation Column ball grid array package

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101964332A (zh) * 2009-07-22 2011-02-02 万国半导体股份有限公司 芯片级表面封装的半导体器件封装及其制备过程
CN101964332B (zh) * 2009-07-22 2013-03-13 万国半导体股份有限公司 芯片级表面封装的半导体器件封装及其制备过程
CN103420331A (zh) * 2012-05-23 2013-12-04 飞思卡尔半导体公司 腔式半导体封装及其封装方法
CN103420331B (zh) * 2012-05-23 2016-12-28 飞思卡尔半导体公司 腔式半导体封装及其封装方法
CN104916597A (zh) * 2014-03-14 2015-09-16 尼克森微电子股份有限公司 晶圆级扇出芯片的封装方法及封装结构
CN104916597B (zh) * 2014-03-14 2018-06-05 尼克森微电子股份有限公司 晶圆级扇出芯片的封装方法及封装结构
CN105448871A (zh) * 2014-08-18 2016-03-30 万国半导体股份有限公司 功率半导体器件及制备方法
CN105448871B (zh) * 2014-08-18 2019-03-08 万国半导体股份有限公司 功率半导体器件及制备方法
CN104900546A (zh) * 2015-05-04 2015-09-09 嘉兴斯达半导体股份有限公司 一种功率模块的封装结构
CN107026140A (zh) * 2015-11-09 2017-08-08 罗伯特·博世有限公司 具有可焊接的正面的半导体芯片及制造半导体芯片的方法
CN107026140B (zh) * 2015-11-09 2022-02-01 罗伯特·博世有限公司 具有可焊接的正面的半导体芯片及制造半导体芯片的方法
WO2018036319A1 (zh) * 2016-08-22 2018-03-01 杰群电子科技(东莞)有限公司 半导体封装结构及加工方法

Also Published As

Publication number Publication date
US7476979B2 (en) 2009-01-13
TW503487B (en) 2002-09-21
EP1287553A1 (en) 2003-03-05
JP2009105437A (ja) 2009-05-14
AU2001249587A1 (en) 2001-10-15
HK1057648A1 (en) 2004-04-08
US7122887B2 (en) 2006-10-17
US20040026796A1 (en) 2004-02-12
US6890845B2 (en) 2005-05-10
US6767820B2 (en) 2004-07-27
WO2001075961A8 (en) 2002-02-07
US20010048116A1 (en) 2001-12-06
US20040038509A1 (en) 2004-02-26
CN1316577C (zh) 2007-05-16
US20040224438A1 (en) 2004-11-11
JP3768158B2 (ja) 2006-04-19
WO2001075961A1 (en) 2001-10-11
US20050186707A1 (en) 2005-08-25
US6624522B2 (en) 2003-09-23
US7253090B2 (en) 2007-08-07
JP2005354105A (ja) 2005-12-22
EP1287553A4 (en) 2007-11-07
JP2004500720A (ja) 2004-01-08
US20060220123A1 (en) 2006-10-05
JP4343158B2 (ja) 2009-10-14

Similar Documents

Publication Publication Date Title
CN1430791A (zh) 芯片尺度表面安装器件及其制造方法
CN1311548C (zh) 具有改进的散热能力的半导体器件封装
US6316287B1 (en) Chip scale surface mount packages for semiconductor device and process of fabricating the same
US7390698B2 (en) Packaged semiconductor device and method of manufacture using shaped die
US6562647B2 (en) Chip scale surface mount package for semiconductor device and process of fabricating the same
US8890296B2 (en) Wafer level chip scale package
CN1734755B (zh) 用于源安装封装的可焊接的顶部金属化和钝化
JP2005506691A5 (zh)
US8970032B2 (en) Chip module and method for fabricating a chip module
US20240213202A1 (en) Encapsulant-defined land grid array (lga) package and method for making the same

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
CP01 Change in the name or title of a patent holder

Address after: American California

Patentee after: Infineon science and technology Americas

Address before: American California

Patentee before: International Rectifier Corporation

CP01 Change in the name or title of a patent holder
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20070516

Termination date: 20200329

CF01 Termination of patent right due to non-payment of annual fee