CN101964332B - 芯片级表面封装的半导体器件封装及其制备过程 - Google Patents

芯片级表面封装的半导体器件封装及其制备过程 Download PDF

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CN101964332B
CN101964332B CN2010102386499A CN201010238649A CN101964332B CN 101964332 B CN101964332 B CN 101964332B CN 2010102386499 A CN2010102386499 A CN 2010102386499A CN 201010238649 A CN201010238649 A CN 201010238649A CN 101964332 B CN101964332 B CN 101964332B
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substrate
device substrate
wafer
conductive layer
semiconductor packages
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CN101964332A (zh
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冯涛
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Alpha and Omega Semiconductor Cayman Ltd
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Alpha and Omega Semiconductor Inc
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Abstract

本发明提出了一种半导体器件封装晶片及其制备方法。此器件封装晶片可以包括具有位于器件衬底的前表面上的一个或多个前电极的器件衬底，并且相应地电连接到形成在前表面附近的器件衬底中的一个或多个器件区域。在器件衬底的后表面上制备一个背部导电层。此背部导电层电连接到形成在器件衬底的后表面附近的器件衬底中的一个器件区域上。一个或多个导电延伸部分，相应地形成在与背部导电层电接触的器件衬底的一个或多个侧壁上，并延伸到器件衬底的一部分前表面上。在器件衬底的后表面上黏接一个支持衬底。

Description

芯片级表面封装的半导体器件封装及其制备过程
技术领域
本发明涉及半导体器件制造，更确切地说，涉及表面封装的芯片级半导体器件封装的晶圆级制造。
背景技术
在一个晶圆上制备多个器件封装晶片的过程中，半导体器件面临着诸多挑战。对于芯片级封装金属氧化物场效应管(MOSFET)器件也是如此，尤其是垂直传导功率MOSFET器件，在半导体衬底的一个表面上有栅极和源极区，在另一面上有漏极区。
在一种指定半导体器件的一个表面上的电连接，以及在器件的另一个表面上的电连接，必须延伸到一个公共面上，以便用于器件的后包装。指定半导体器件的背面连接扩展至前表面，增加了器件的封装尺寸，当在晶圆级工作时，减少了在指定晶圆上安装的半导体器件封装晶片的数量。对于垂直传导功率MOSFET等半导体器件，需要朝着更小的器件结构/最小化引脚、以及更小的封装厚度的方向努力。这使得单晶圆适合更多的半导体器件封装晶片，从而接近最优化的真正的芯片级封装。每个半导体器件封装晶片同样要求具有较小的电阻，这可以通过避免传统的引线接合互联，以及减小半导体器件封装晶片的厚度来完成。半导体器件封装晶片的另一个可取的特点在于良好的热膨胀，这是通过底部和顶部曝光获得的。另一个预期的效果是为半导体器件提供良好的承载。较好的稳定性以及较稳固的支撑，都将半导体器件晶片/衬底破碎的风险降至最低。最后，很重要的一点是，这种半导体器件封装晶片的制备应该作为一个晶圆级批量生产的过程来完成，以实现效率最大化，并且制备这些半导体器件封装晶片所需的时间最少。
对于在一个表面上带有多个连接、在另一表面上带有一个连接的半导体器件来说(例如MOSFET器件)，要获得上述所需的特点，在公共面的延伸连接中将需要新的连接方式。另外还需要简便、快捷、高效地封装半导体器件的方法。因此，原有技术中采用了各种封装的思路及方法。
尽管在过去的十年中，硅工艺技术取得了显著的进展，但就绝大部分而言，基本的封装方法仍然沿用过去的封装工艺。环氧树脂或焊锡芯片黏接，与铝线或金线黏接到引线框上，仍然是主要的半导体封装方法。然而，在半导体处理工艺方面的进展，使得与传统的封装技术相关连的寄生现象(例如电阻、电容和电感)，更变成局限性能的一个因素。至于传统的倒装晶片技术，除了其他缺点以外，在保持引脚很小的情况下，还很难实现器件背部的电连接。这些局限在功率转换器件等高电流应用中，尤为明显。
美国专利号2003/052405提出了一种垂直功率MOSFET器件，漏极电极形成在硅衬底的底面上，连接到它上面的引线框上，源极电极和漏极电极裸露在器件底面。用环氧树脂或硅有机树脂等树脂封装MOSFET器件，以覆盖MOSFET器件以及引线框的内部。在MOSFET器件的底面上，树脂的表面与引线框和栅极/源极电极的表面，大致在一个平面上。也就是说，在半导体器件的底面上，引线框的外部引线部分的底面以及栅极/源极电极的底面都裸露在外，用于连接组装衬底的传导垫(表面安装)。然后，用树脂覆盖这些栅极/源极电极的边缘。
美国专利号6,133,634提出了一种倒装晶片封装方法，使用一个含有漏极端、源极端以及栅极端的功率MOSFET器件。漏极端连接到焊锡球的导电载流子和外部阵列上。源极端和栅极端连接到焊锡球的内部阵列上。焊锡球的导电载流子和外部阵列，作为到源极端和栅极端的电连接，为同一平面中的漏极端提供电连接。
上述垂直功率MOSFET器件的原有技术的封装设计，可以为独立的MOSFET提供源极、栅极和漏极的电连接。但是把晶圆分成独立的晶片之后，需要附加的组装步骤，不用再进行高成本而且制备时间更长的晶圆级处理。此外，使用金属夹片提供从晶片背面到前端的漏极接触，可以缩减器件在器件封装晶片中的有效空间。有必要提出一种封装设计和工艺，可以使用更低成本的晶圆级处理，并减少独立元件的引脚。
正是在这一背景下，提出了本发明的各种实施例。
发明内容
本发明的一种半导体器件封装晶片，包括：
一个器件衬底，具有一个或多个前电极，位于器件衬底的前表面上，并且相应地电连接到形成在前表面附近的器件衬底中的一个或多个器件区域上；
一个形成在器件衬底的后表面上的背部导电层，其中背部导电层电连接到形成在器件衬底的后表面附近的器件衬底中的一个器件区域上；
一个或多个同背部导电层电接触的导电延伸部分，其中一个或多个导电延伸部分相应地形成在器件衬底的一个或多个侧壁上，并延伸到衬底的前表面部分；以及
一个黏接到器件衬底的后表面上的支持衬底。
上述的半导体器件封装晶片，其中，器件区域包括一个源极区域、一个漏极区域以及一个栅极区域。
上述的半导体器件封装晶片，其中，形成在器件衬底的前表面附近的器件衬底中的一个或多个器件区域，是由一个源极区域和一个栅极区域组成的，形成在后表面附近的器件衬底中的器件区域是由一个漏极区域组成的。
上述的半导体器件封装晶片，其中，一个或多个前电极以及一个或多个导电延伸部分是由相同的导电材料制成的。
上述的半导体器件封装晶片，其中，一个或多个导电延伸部分是由一种电镀材料制成的。
上述的半导体器件封装晶片，其中，一个或多个前电极，与延伸到衬底的一部分前表面上的一部分一个或多个导电延伸部分基本共面。
上述的半导体器件封装晶片，其中，器件衬底的侧壁含有一个或多个倾斜的侧壁。
上述的半导体器件封装晶片，其中，倾斜侧壁具有55度的倾斜角。
上述的半导体器件封装晶片，其中，一个或多个导电延伸部分中的每一个，都沿器件衬底的边缘长度方向延伸。
上述的半导体器件封装晶片，其中，器件衬底和支持衬底具有近似匹配的热膨胀系数。
上述的半导体器件封装晶片，其中，器件衬底的厚度小于100微米。
上述的半导体器件封装晶片，其中，器件衬底和支持衬底是由同种材料组成的。
上述的半导体器件封装晶片，其中，器件衬底和支持衬底是由硅制成的。
一种用于制备多个半导体器件封装晶片的方法，包括：
步骤a：在一个公共器件衬底上，制备多个半导体器件晶片，其中每个半导体器件晶片都含有形成在器件衬底的前表面附近的器件衬底中的一个或多个器件区域，以及形成在器件衬底的后表面附近的器件衬底中的一个器件区域；
步骤b：在器件衬底的后表面上，制备一个背部导电层，其中背部导电层电连接到形成在器件衬底的后表面附近的器件衬底中的一个器件区域上；
步骤c：将一个支持衬底黏接到后表面上；
步骤d：通过除去相邻晶片之间的器件衬底材料、保留附着在支持衬底上的多个器件晶片并且定义每个器件晶片的器件衬底部分的侧壁，将器件衬底分成多个器件晶片；并且
步骤e：在每个器件晶片的器件衬底部分的一个或多个侧壁上，相应地制备一个或多个导电延伸部分，导电延伸部分延伸到器件晶片的一部分前表面上，其中一个或多个导电延伸部分与背部导电层电接触。
上述方法，还包括切割支持衬底，以便将器件晶片分成独立的半导体器件封装晶片。
上述方法，还包括在所述的制备背部导电层之前，通过从后表面上除去材料，将器件衬底减薄至所需的厚度。
上述方法，将器件衬底减薄至所需的厚度，是通过Taiko晶圆研磨方法，即是仅研磨器件衬底底部表面的中心部分而保留器件衬底周围较厚的边缘部分的晶圆研磨的方法完成的。
上述方法，其中，背部导电层是通过在器件衬底的后表面上，至少电镀一个金属层而形成的。
上述方法，其中，至少一个金属层包括一个最厚的铜的金属层。
上述方法，其中，支持衬底和器件衬底具有近似匹配的热膨胀系数。
上述方法，其中，步骤d是通过各向异性刻蚀完成的。
上述方法，其中，各向异性刻蚀是一种湿刻蚀。
上述方法，其中，各向异性湿刻蚀是利用氢氧化钾完成的。
上述方法，其中，步骤e中所述的侧壁为倾斜的侧壁。
上述方法，其中，一个或多个导电延伸部分中的每一个，都沿器件衬底部分的边缘长度方向上延伸。
上述方法，其中，还包括制备一个或多个前电极，与形成在前表面附近的器件衬底中的一个或多个器件区域电接触。
上述方法，其中，制备一个或多个导电延伸部分是通过在器件上电镀导电材料而形成的。
一种半导体器件封装衬底，包括：
支持衬底；
多个从一个公共器件衬底形成的半导体器件晶片，附着在支持衬底上，其中通过除去相邻晶片之间的器件衬底材料、保留附着在支持衬底上的多个器件晶片并且定义每个器件晶片的器件衬底部分的侧壁，将器件衬底分成多个器件晶片，其中每个半导体器件晶片包括：
形成在器件衬底的前表面附近的器件衬底中的一个或多个器件区域，以及形成在器件衬底的后表面附近的器件衬底中的一个器件区域；
一个或多个前电极，与形成在前表面附近的器件衬底中的一个或多个器件区域电接触；
一个或多个导电延伸部分，相应地形成在每个器件晶片的器件衬底部分的一个或多个侧壁上，并延伸到器件晶片的一部分前表面上；
一个背部导电层，形成在器件衬底的后表面和支持衬底之间，其中背部导电层与形成在每个器件晶片的后表面附近的区域电接触，其中背部导电层与一个或多个导电延伸部分电接触。
附图说明
图1A表示依据本发明的一个实施例，一种半导体器件封装晶片前端的透视图。
图1B表示依据本发明的一个实施例，一种半导体器件封装晶片前端的俯视图。
图2A-2K表示依据本发明的一个实施例，多个半导体器件封装晶片的制备方法的剖面图。
图3A-3C表示依据图2B-2D，研磨方法、制备背部导电层以及黏接支持晶圆的一种可能的晶圆级视图的示意图。
图4表示通过支持衬底进行切割的示意图，利用切割装置，将晶圆分成独立的半导体器件封装晶片。
具体实施方式
尽管为了解释说明，以下详细说明中包含许多特殊细节，但本领域的技术人员应理解这些细节的变化和修正都属本发明的范围。因此，下文中所提出的本发明的实施例并没有损失其一般性，而且不作为对请求保护的发明的局限。
依据本发明的一个实施例，器件封装可以如图1A-1B所示。器件封装晶片100通常包括一个器件衬底101，贴在支持衬底111上。在器件衬底101中制备一个或多个有源器件。器件衬底101可以由硅等半导体材料构成。作为示例，有源器件可以是垂直金属氧化物半导体场效应管(MOSFET)器件。通过传统的半导体器件制备工艺，有源器件在器件衬底101中含有源极、栅极和漏极区。
支持衬底111也称为支持晶片，为有源器件提供机械支持。这使有源器件可以形成在一个比没有支持衬底时更薄的器件衬底101上。支持衬底111还给有源器件提供更多的热传导，更好地进行散热。器件衬底101的较佳厚度应小于6密耳。支持衬底可以比器件衬底更厚。器件衬底101更薄的话，与器件衬底101有关的电阻将降低。支持衬底111的材料可以和器件衬底101的材料相同，或者其热膨胀系数基本等于器件衬底101的热膨胀系数，这作为示例，不作为局限，
如果支持衬底材料的热膨胀系数(CTE)在器件衬底材料的CTE的±100％之内，那么衬底材料的CTE和支持衬底的CTE可以看做充分匹配。作为示例，硅(Si)在25℃时的CTE为2.6x10-6K-1，而且在任何可能的封装过程或器件工作温度范围内，CTE都小于4x10-6K-1。可以认为CTE在0至8x10-6K-1之间的其他材料和Si器件衬底近似匹配。铜在25℃时的CTE为16.5x10-6K-1，就不能认为和Si近似匹配。
器件衬底101含有在两个对边上形成的电连接。例如，在衬底101中形成的器件为二极管，那么不同类型掺杂的半导体区的电接头可以形成在器件衬底101的对边上。就MOSFET器件而言，源极电极103和栅极电极105电连接到有源器件的源极区和栅极区，从而在器件衬底101的前端附近形成有源器件，这仅作为示例，不作为局限。背部导电层104可以形成在器件衬底101的背部，以接触器件的漏极区。背部导电层104通常沉积在器件衬底101和支持衬底111之间。通过背部导电层104和侧边延伸部分108，漏极电极可以同器件衬底中的漏极区在背部附近，形成电接触。在可选实施例中，器件衬底101可以包含这样一个器件结构：在前端形成栅极和漏极接触，从背部形成源极接触。此外，从一侧形成栅极和漏极接触，同时从背部形成源极接触，这也在本发明的实施例范围之内。
钝化层102形成在器件衬底101的表面上，通过钝化层102中的开口，源极电极103和栅极电极105可以与源极和栅极区相接触。作为示例，钝化层102可以由聚酰亚胺、氮化硅、氧化硅或氧氮化硅组成，通过相互电接触，构成绝缘电极103、105以及延伸部分108。
为了有可能从器件封装100的前端，就形成与漏极的电接触，背部导电金属层104可以与导电延伸部分108电接触，导电延伸部分105沿器件衬底101的一个或多个侧壁106，延伸到器件衬底101前端的一部分。背部导电金属层104和导电延伸部分108结合起来，作为漏极电极，在与其他前端电极103、105一样，位于器件同侧，形成电接触。在器件的前端，源极电极103和栅极电极105，与漏极电极的导电延伸部分108近似共面。每个导电延伸部分108都沿器件衬底101的边缘长度方向延伸。为了便于制备导电延伸部分108，侧壁106可以具有一定的倾角(例如55度的斜面)。在延伸部分108的制备过程中，倾斜的侧壁106有利于在侧壁上沉积导电材料。通过沿器件衬底101的边缘长度方向上形成导电延伸部分108，可以获得从器件衬底的背部到前端的电接触。
可以通过用铜(Cu)等金属对一部分器件封装晶片100进行选择性电镀，或用镍/金(Ni/Au)或其他电镀材料等金属组合物对所选的一部分器件封装晶片100进行非电解镀层，形成源极电极103、栅极电极105、背部导电层104以及延伸部分108。NiAu是由一层镍，上面覆盖一层比较薄的金组成的，以防止氧化。导电延伸部分108提供一个或多个前端电接头，通过位于器件衬底101和延伸部分108的背面的背部导电层104，电接头电连接到形成在器件衬底101的背面中的漏极区。背部导电层104可以用Ti-Ni-Cu、Ti-Ni-Al、Ti-Ni-Ag或Ti-Ni-Au等金属，对器件衬底101的背面进行蒸发、溅射或电镀，形成背部导电层104。为了简便，器件衬底101，包括全部电极103、105、108以及背部导电层104，以下统称为有源器件。
这种半导体器件封装晶片100，通过限制电极在延伸到公共面上时所占用的面积，在不缩减半导体器件可用尺寸的同时，实现了将器件所有的电极都延伸到一个公共面上的目标。因此，可以在一个指定晶圆上，形成多个半导体器件封装晶片100，减少了封装引脚，使我们离真正的芯片级封装更近了一步。由于存在附加的支持衬底111，使得我们可以减小半导体衬底101的厚度，从而进一步降低半导体衬底101的电阻。支持衬底111除了提供物理支持之外，还使器件封装晶片100不会轻易破碎，而且可以更好地适应热膨胀。
如图1A-图1B所示的器件封装晶片，可以根据图2A-2K所示的新方法制备。这种封装方法可以用多个半导体器件晶片，在晶圆级实现。此外，一些工艺还可以在晶圆批量级完成，例如一次使用多个晶圆。为了清楚地说明，一个区域相当于仅封装两个半导体器件晶片。本领域的技术人员应理解，这两个晶片可以代表在半导体器件衬底上形成的更多个这种晶片。
如图2A所示，要制备器件封装晶片200，首先要在器件衬底101中形成器件结构(例如MOSFET器件)。图2K表示所形成的器件封装晶片200。器件衬底101可以含有形成在器件衬底101的前表面附近的源极区和栅极区，以及形成在器件衬底101的后表面附近的漏极区，这作为示例，不作为局限。在器件衬底101中形成的器件，可以电连接到一个或多个前端接头201上。例如，前端接头201可以含有一个源极垫和一个栅极垫，它们位于器件衬底101的前表面上。源极垫和栅极垫(图中没有表示出)通过钝化层102，相互绝缘。作为示例，钝化层102可以用聚酰亚胺、氮化硅、氧化硅或氮氧化硅制备。
如图2B所示，将器件衬底101的后表面减薄至所需厚度。作为示例，研磨器件衬底101，使其厚约100微米(μm)或更小，最好是约为50μm或更小。通过将器件衬底101的后表面研磨至所需厚度，我们可以有效地降低成形后的器件封装晶片200的总电阻。除了选择研磨器件衬底以外，还可以利用刻蚀工艺使晶圆变薄。刻蚀工艺最好是与机械研磨配合使用，在机械掩埋之后进行刻蚀效果更佳。
如图2C所示，清洗器件衬底101的后表面，并使其金属化，以便在器件衬底101的后表面上形成一个背部导电层104。背部导电层104可以为衬底101后表面中所形成的漏极区，提供电接触。要将器件衬底101的后表面金属化，首先要在器件衬底101的后表面上沉积一个很薄的种子金属层。种子金属层可以是一个很薄的金属层或金属合金层，伴有背部导电层104的材料沉积在它上方。作为示例，如果用铜(Cu)作为背部导电层104，那么可以使用厚度小于4μm的TiCu层作种子层。一旦沉积了金属种子层之后，可以用金属(例如先用镍Ni然后用铜Cu)蒸发在器件衬底101的后表面上形成导电层104。还可选择，通过溅射或蒸发等方法，用TiNiAg、TiNiAu、TiNiAl等其他材料制备背部导电层104。
如图2D所示，支持衬底111贴在器件衬底101的背面，构成封装衬底。背部导电层104形成在器件衬底101的后表面上，支持衬底111可以直接贴在背部导电层104上。支持衬底可以用环氧树脂或利用共晶方法，贴在器件衬底101上，这仅作为示例，不作为局限。支持衬底111可以作为衬底的形式，其热膨胀系数与器件衬底101的热膨胀系数近似匹配，还可选择用与器件衬底101相同的材料，制备支持衬底111。例如，如果用硅来制备器件衬底101，那么支持衬底111也可以用硅制备。也可选择用科瓦铁镍钴合金或合金42(镍铁合金)来制备支持衬底111，镍铁合金的热膨胀系数与硅的近似匹配。支持衬底111为器件封装晶片200提供机械稳定性，以补偿由于对器件衬底101减薄，而在稳定性上的损失。支持衬底111不仅降低了在操作过程中对器件封装晶片200造成损伤的可能性，还有利于器件封装晶片200更好地热膨胀。将减薄的器件衬底101贴在支持衬底111上，所形成的封装衬底十分坚硬和/或牢固，可以在后续的处理过程中，用传统的晶圆处理设备来处理。例如，封装衬底的厚度可以与传统晶圆相同，这些处理设备一般都能处理。器件衬底101加上支持衬底111的封装总厚度，应至少是0.25mm，但对于实际产品，还应小于0.9mm。图3A-3C分别表示从晶圆级的角度来看，图2B-2D所示的工艺实施图，下文还将详细介绍。
如图2E所示，在器件衬底101上进行各向异性刻蚀，以便将器件衬底分成附着在公共的支持衬底111上的独立的器件晶片101’。各向异性刻蚀在每个器件晶片101’的边上，限定了侧壁106。可以利用掩膜和停止层进行各向异性刻蚀，以保护背部导电层104、钝化层102、前端接头201和支持衬底111不受刻蚀。如果器件衬底101是由硅制备的，那么各向异性刻蚀可以利用氢氧化钾(KOH)进行湿刻蚀，这仅作为示例，不作为局限。之所以选用湿刻蚀，而不用干刻蚀，是因为湿刻蚀可以将晶圆分批处理，而不是一次一个晶圆。掩膜(即钝化层102)可以用氮化物实现，停止层可以在之前的背部金属化过程中，利用沉积Ni来实行，以便与KOH湿刻蚀一起取得最佳效果，这仅作为示例，不作为局限。如果将钝化层102用作掩膜，那么在此过程中，就无需使用额外的光致抗蚀剂掩膜。沿器件衬底101特定的晶体学平面，KOH湿刻蚀硅，使得所形成的侧壁106带有一定斜度(例如大约55度)。斜侧壁106有利于将来继续在侧壁106上沉积导电层。
图2F表示封装过程中的下一个步骤。在器件封装晶片200的上方形成一个光致抗蚀剂掩膜203，以便在钝化层102中留下一个区域，置于前端接头201上方裸露着。光致抗蚀剂掩膜203可以利用喷涂光致抗蚀剂技术来制备，这仅作为示例，不作为局限。然后对裸露的钝化层102进行刻蚀，暴露出所选的部分前端接头201。按照这种方法，可以选择除去钝化层102，以暴露源极垫201和栅极垫。可以用标准的干刻蚀或湿刻蚀工艺，刻蚀掉钝化层102的裸露部分。要注意的是，图2F表示的是已经刻蚀掉钝化层102的裸露部分之后的结果。
如图2G所示，刻蚀掉部分钝化层102，暴露出前端接头201之后，可以除去光致抗蚀剂掩膜203。例如，利用抗蚀剂脱落剂使抗蚀剂化学改性，不再附着在器件晶片101’上，从而除去光致抗蚀剂掩膜203，或者用含氧的等离子，使抗蚀剂氧化，从而除去光致抗蚀剂掩膜203。一旦除去光致抗蚀剂掩埋203之后，就可以选择导电材料形成在裸露的部分背部导电层104、倾斜的侧壁106以及在器件晶片101’前端的部分钝化层102上方，从而将背部导电层104提供的电接触，延伸到器件晶片101’的前端。
可以在器件封装晶片200上沉积一个种子金属薄层，以便将来沉积导电层，这仅作为示例，不作为局限。种子金属层尽管在图2G中没有表示出来，但它却沉积在背部导电层104的裸露部分、倾斜的侧壁106、部分钝化层102以及前端接头201的裸露部分上方。种子层可以是一个很薄的金属层或金属合金层，伴有背部导电层104的材料沉积在它上方。例如，如果用铜(Cu)作为背部导电层104，那么可以使用厚度小于4μm的TiCu层作种子层。
如图2H所示，沉积种子金属层之后，在器件晶片101’上方形成第二个光致抗蚀剂掩膜205。第二个光致抗蚀剂掩膜205将器件晶片101’的裸露区域形成图案，以便金属化。裸露区域包括在背部导电层104的一个区域、器件101’的倾斜的侧壁106、在器件晶片101’前端的钝化层102的一个区域、以及裸露的前端接头201。可以利用喷涂光致抗蚀剂技术形成第二个光致抗蚀剂掩膜205，这仅作为示例，不作为局限。第二个光致抗蚀剂掩膜205限定了器件晶片101’上将被金属化的区域，并保护器件封装晶片200的其他区域不受金属化过程影响。
如图2I所示，制备第二个掩膜205并形成图案之后，在通过光致抗蚀剂掩膜205裸露的区域上，以及裸露的种子金属上方，形成一个导电层，以便通过背部导电层104，形成背面电接触(例如漏极电极)的前端延伸部分108。延伸部分108与背部导电层104电接触。导电层也可以构成前端电极103(例如源极电极和栅极电极(图中没有表示出))。可以在种子金属层上方，电镀铜(Cu)，还可选择继续电镀金，厚度在5-100μm之内，这仅作为示例，不作为局限。前端电极103(例如源极电极103和栅极电极(图2中没有表示出))，为对应的下方的前端接头201(例如源极垫和栅极垫(图中没有表示出)提供电接触，前端接头201位于器件晶片101’的前表面上。背部电接头的延伸部分108沿器件衬底101对面的倾斜侧壁106，延伸到器件衬底101的一部分前端上方。延伸部分108通过背部导电层104，为形成在器件晶片101’的后表面中的漏极区域提供电接触。通过将电连接从器件晶片101’的背部漏极区，延伸到前端电接头(例如源极区和栅极电极)的同一平面上，所形成的器件封装晶片200可以更加高效地用于封装后的器件。此外，这种结构限制了器件晶片101’将背部电极延伸到公共面上所牺牲的面积，从而增加了在一个指定晶圆上可以制备的器件晶片101’的数量，也使我们离真正的芯片级封装更近了一步—封装的引脚仅比半导体晶片区域稍大一点。
图2J中除去了光致抗蚀剂掩膜205，并且刻蚀掉任何多余的种子金属。利用抗蚀剂脱落剂使抗蚀剂化学改性，不再附着在衬底101上，从而除去光致抗蚀剂掩膜205，或者用含氧的等离子，使抗蚀剂氧化，从而除去光致抗蚀剂掩膜205。一旦除去光致抗蚀剂掩埋205之后，上面没有沉积导电层(例如电极103或延伸部分108)的种子金属就会被刻蚀掉。可以通过标准的金属刻蚀工艺，除去金属种子层。例如，电镀导电层103、108可能比种子层和背部金属层104加起来还要厚。因此，如图2K所示，可以控制金属刻蚀时间，将种子层和背部金属层上没有被厚导电层覆盖的地方刻蚀掉。这时，可以将支持衬底沿器件晶片101’之间的划线207切割开来，把封装衬底分成独立的器件封装晶片200。如图2K所示，如果背部导电层104比电极103、108薄许多的话，那么可以在切割之前的刻蚀过程中，将划线207上的背部导电层104除去。但是，如图2J所示，如果背部导电层104并不比铜板电极103、108薄许多的话，那么可以将它保留到刻蚀过程之后。
图3A-3C表示分别表示从晶圆级的角度来看，对应图2B-2D所示的研磨、制备背部导电层以及黏接支持晶圆的方法。2B之前的所有的封装步骤都与上述内容相同，2D之后的所有的封装步骤也都与上述内容相同。为了简便，研磨、制备背部导电层以及黏接支持晶圆的方法，仅用器件衬底101来表示，而没有表示出前端接头201和钝化层102。综上所述，可以在器件衬底101上形成多个器件晶片。
图3A-3C表示整个晶圆的剖面图。图3A表示一种叫做Taiko研磨的研磨方法。Taiko研磨包括仅研磨器件衬底101底部表面的中心部分，保留器件衬底101周围较厚的边缘301部分，厚边缘301作为支持环，提供机械支持。这种研磨方法适用于超薄的器件衬底101，器件衬底101具有足够的机械稳定性，在后续的晶圆黏接过程中，可以用传统的设备处理。Taiko研磨之后，器件衬底101中较薄部分的厚度小于100μm，或者甚至小于50μm。器件衬底101的较厚边缘的厚度在400μm至全晶圆厚度(例如675μm)之间，典型的全晶圆厚度为500μm。
如图3B所示，器件衬底101的底面完成Taiko研磨之后，将器件衬底101的背面金属化，以便在器件衬底101的背面形成一个背部导电层104。可以参照上述图2C进行器件衬底101的背面金属化。需注意的是，背部导电层104不是仅仅形成在器件衬底101的较薄部分上，而是形成在器件衬底101的较薄部分的背面、厚边缘301的侧壁以及厚边缘301的背面上。
如图3C所示，一旦在器件衬底101的背面上形成背部导电层104之后，就可以在器件衬底101上黏接一个支持衬底111。虽然，支持衬底111黏接在器件衬底101的较薄部分的背面上所形成的背部导电层104上，还可以黏接在厚边缘301的侧壁上所形成的背部导电层104上，但却不能黏接在厚边缘301的底面上。一旦黏接完支持衬底111之后，就按照图2E-2K所示继续封装半导体器件晶片。
如图4所示，完成封装过程之后，可以选择穿过支持衬底，切割半导体器件封装晶片，利用切裁设备401将封装衬底400分成独立的器件晶片封装。如果背部导电层104如图2K所示，已经通过划线被刻蚀掉，那么可以用金刚石锯作为切裁设备401，穿过支持衬底，将晶圆400切割成独立的部分。但是，如果刻蚀完之后，背部导电层仍然覆盖着支持衬底的话，那么可以用激光切割机作为切裁设备401，穿过背部导电层和支持衬底，将晶圆400切割成独立的部分。还可选择一种混合方法，即利用激光切割机切割背部导电层，利用金刚石锯切割支持衬底，将晶圆400切割成独立的部分。由于切割封装衬底400仅仅切割的是支持衬底，而不是器件衬底，因此对器件晶片造成损害的可能性较小。
尽管以上完整说明了本发明的较佳实施例，但仍可能存在各种等价的变化和修正。因此，本发明的范围不应由上述说明限定，而应所附的权利要求书及其全部等价内容决定。任何特征，无论是否较佳，都可以与任何其他无论是否较佳的特征相结合。

Claims (28)

1.一种半导体器件封装晶片，其特征在于，包括：
一个器件衬底，具有一个或多个前电极，位于器件衬底的前表面上，并且相应地电连接到形成在前表面附近的器件衬底中的一个或多个器件区域上；
一个形成在器件衬底的后表面上的背部导电层，其中背部导电层电连接到形成在器件衬底的后表面附近的器件衬底中的一个器件区域上；
一个或多个同背部导电层电接触的导电延伸部分，其中一个或多个导电延伸部分相应地形成在器件衬底的一个或多个侧壁上，并延伸到衬底的前表面部分；以及
一个黏接到器件衬底的后表面上的支持衬底。
2.如权利要求1所述的半导体器件封装晶片，其特征在于，器件区域包括一个源极区域、一个漏极区域以及一个栅极区域。
3.如权利要求2所述的半导体器件封装晶片，其特征在于，形成在器件衬底的前表面附近的器件衬底中的一个或多个器件区域，是由一个源极区域和一个栅极区域组成的，形成在后表面附近的器件衬底中的器件区域是由一个漏极区域组成的。
4.如权利要求1所述的半导体器件封装晶片，其特征在于，一个或多个前电极以及一个或多个导电延伸部分是由相同的导电材料制成的。
5.如权利要求1所述的半导体器件封装晶片，其特征在于，一个或多个导电延伸部分是由一种电镀材料制成的。
6.如权利要求1所述的半导体器件封装晶片，其特征在于，一个或多个前电极，与延伸到衬底的一部分前表面上的一部分一个或多个导电延伸部分基本共面。
7.如权利要求1所述的半导体器件封装晶片，其特征在于，器件衬底的侧壁含有一个或多个倾斜的侧壁。
8.如权利要求7所述的半导体器件封装晶片，其特征在于，倾斜侧壁具有55度的倾斜角。
9.如权利要求1所述的半导体器件封装晶片，其特征在于，一个或多个导电延伸部分中的每一个，都沿器件衬底的边缘长度方向延伸。
10.如权利要求1所述的半导体器件封装晶片，其特征在于，器件衬底和支持衬底具有近似匹配的热膨胀系数。
11.如权利要求1所述的半导体器件封装晶片，其特征在于，器件衬底的厚度小于100微米。
12.如权利要求1所述的半导体器件封装晶片，其特征在于，器件衬底和支持衬底是由同种材料组成的。
13.如权利要求12所述的半导体器件封装晶片，其特征在于，器件衬底和支持衬底是由硅制成的。
14.一种用于制备多个半导体器件封装晶片的方法，其特征在于，包括：
步骤a：在一个公共器件衬底上，制备多个半导体器件晶片，其中每个半导体器件晶片都含有形成在器件衬底的前表面附近的器件衬底中的一个或多个器件区域，以及形成在器件衬底的后表面附近的器件衬底中的一个器件区域；
步骤b：在器件衬底的后表面上，制备一个背部导电层，其中背部导电层电连接到形成在器件衬底的后表面附近的器件衬底中的一个器件区域上；
步骤c：将一个支持衬底黏接到后表面上；
步骤d：通过除去相邻晶片之间的器件衬底材料、保留附着在支持衬底上的多个器件晶片并且定义每个器件晶片的器件衬底部分的侧壁，将器件衬底分成多个器件晶片；并且
步骤e：在每个器件晶片的器件衬底部分的一个或多个侧壁上，相应地制备一个或多个导电延伸部分，导电延伸部分延伸到器件晶片的一部分前表面上，其中一个或多个导电延伸部分与背部导电层电接触。
15.如权利要求14所述的方法，其特征在于，还包括切割支持衬底，以便将器件晶片分成独立的半导体器件封装晶片。
16.如权利要求14所述的方法，其特征在于，还包括在所述的制备背部导电层之前，通过从后表面上除去材料，将器件衬底减薄至所需的厚度。
17.如权利要求16所述的方法，其特征在于，将器件衬底减薄至所需的厚度，是通过仅研磨器件衬底底部表面的中心部分而保留器件衬底周围较厚的边缘部分的晶圆研磨的方法完成的。
18.如权利要求14所述的方法，其特征在于，背部导电层是通过在器件衬底的后表面上，至少电镀一个金属层而形成的。
19.如权利要求18所述的方法，其特征在于，至少一个金属层包括一个铜的金属层。
20.如权利要求14所述的方法，其特征在于，支持衬底和器件衬底具有近似匹配的热膨胀系数。
21.如权利要求14所述的方法，其特征在于，步骤d是通过各向异性刻蚀完成的。
22.如权利要求21所述的方法，其特征在于，各向异性刻蚀是一种湿刻蚀。
23.如权利要求22所述的方法，其特征在于，各向异性湿刻蚀是利用氢氧化钾完成的。
24.如权利要求14所述的方法，其特征在于，步骤e中所述的侧壁为倾斜的侧壁。
25.如权利要求14所述的方法，其特征在于，一个或多个导电延伸部分中的每一个，都沿器件衬底部分的边缘长度方向上延伸。
26.如权利要求14所述的方法，其特征在于，还包括制备一个或多个前电极，与形成在前表面附近的器件衬底中的一个或多个器件区域电接触。
27.如权利要求14所述的方法，其特征在于，制备一个或多个导电延伸部分是通过在器件上电镀导电材料而形成的。
28.一种半导体器件封装衬底，其特征在于，包括：
支持衬底；
多个从一个公共器件衬底形成的半导体器件晶片，附着在支持衬底上，其中通过除去相邻晶片之间的器件衬底材料、保留附着在支持衬底上的多个器件晶片并且定义每个器件晶片的器件衬底部分的侧壁，将器件衬底分成多个器件晶片，其中每个半导体器件晶片包括：
形成在器件衬底的前表面附近的器件衬底中的一个或多个器件区域，以及形成在器件衬底的后表面附近的器件衬底中的一个器件区域；
一个或多个前电极，与形成在前表面附近的器件衬底中的一个或多个器件区域电接触；
一个或多个导电延伸部分，相应地形成在每个器件晶片的器件衬底部分的一个或多个侧壁上，并延伸到器件晶片的一部分前表面上；
一个背部导电层，形成在器件衬底的后表面和支持衬底之间，其中背部导电层与形成在每个器件晶片的后表面附近的区域电接触，其中背部导电层与一个或多个导电延伸部分电接触。
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