JP2005340327A - 半導体装置及びその製造方法 - Google Patents

半導体装置及びその製造方法 Download PDF

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Publication number
JP2005340327A
JP2005340327A JP2004154226A JP2004154226A JP2005340327A JP 2005340327 A JP2005340327 A JP 2005340327A JP 2004154226 A JP2004154226 A JP 2004154226A JP 2004154226 A JP2004154226 A JP 2004154226A JP 2005340327 A JP2005340327 A JP 2005340327A
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JP
Japan
Prior art keywords
element isolation
insulating film
film
isolation insulating
oxide film
Prior art date
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Pending
Application number
JP2004154226A
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English (en)
Japanese (ja)
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JP2005340327A5 (enExample
Inventor
Norio Ishizuka
典男 石塚
Jun Tanaka
順 田中
Tomio Iwasaki
富生 岩▲崎▼
Hiroyuki Ota
裕之 太田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Technology Corp
Original Assignee
Renesas Technology Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Technology Corp filed Critical Renesas Technology Corp
Priority to JP2004154226A priority Critical patent/JP2005340327A/ja
Priority to TW094112882A priority patent/TWI282141B/zh
Priority to CNB2005100738401A priority patent/CN100461414C/zh
Priority to KR1020050043401A priority patent/KR100732647B1/ko
Priority to US11/139,002 priority patent/US7279769B2/en
Publication of JP2005340327A publication Critical patent/JP2005340327A/ja
Publication of JP2005340327A5 publication Critical patent/JP2005340327A5/ja
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0151—Manufacturing their isolation regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/601—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H01L21/02134—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material comprising hydrogen silsesquioxane, e.g. HSQ
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H01L21/02137—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material comprising alkyl silsesquioxane, e.g. MSQ
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02203—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being porous

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)
JP2004154226A 2004-05-25 2004-05-25 半導体装置及びその製造方法 Pending JP2005340327A (ja)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP2004154226A JP2005340327A (ja) 2004-05-25 2004-05-25 半導体装置及びその製造方法
TW094112882A TWI282141B (en) 2004-05-25 2005-04-22 Semiconductor device and manufacturing method thereof
CNB2005100738401A CN100461414C (zh) 2004-05-25 2005-05-24 半导体器件及其制造方法
KR1020050043401A KR100732647B1 (ko) 2004-05-25 2005-05-24 반도체장치 및 그 제조 방법
US11/139,002 US7279769B2 (en) 2004-05-25 2005-05-25 Semiconductor device and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2004154226A JP2005340327A (ja) 2004-05-25 2004-05-25 半導体装置及びその製造方法

Publications (2)

Publication Number Publication Date
JP2005340327A true JP2005340327A (ja) 2005-12-08
JP2005340327A5 JP2005340327A5 (enExample) 2006-11-24

Family

ID=35446761

Family Applications (1)

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JP2004154226A Pending JP2005340327A (ja) 2004-05-25 2004-05-25 半導体装置及びその製造方法

Country Status (5)

Country Link
US (1) US7279769B2 (enExample)
JP (1) JP2005340327A (enExample)
KR (1) KR100732647B1 (enExample)
CN (1) CN100461414C (enExample)
TW (1) TWI282141B (enExample)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009027131A (ja) * 2007-06-20 2009-02-05 Toshiba Corp 半導体装置およびその製造方法
WO2009022719A1 (ja) * 2007-08-16 2009-02-19 National University Corporation Tohoku University 半導体装置及びその製造方法
WO2010073947A1 (ja) * 2008-12-25 2010-07-01 国立大学法人東北大学 半導体装置及びその製造方法
WO2011138906A1 (ja) * 2010-05-07 2011-11-10 国立大学法人東北大学 半導体装置の製造方法
JP2012009791A (ja) * 2010-06-28 2012-01-12 Panasonic Corp 固体撮像装置及びその製造方法
WO2012060399A1 (ja) * 2010-11-05 2012-05-10 Ａｚエレクトロニックマテリアルズ株式会社 アイソレーション構造の形成方法
JP2012134302A (ja) * 2010-12-21 2012-07-12 Jsr Corp トレンチ埋め込み方法、及びトレンチ埋め込み用組成物
JP2013074169A (ja) * 2011-09-28 2013-04-22 Kyocera Corp 薄膜配線基板

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5195747B2 (ja) * 2007-03-27 2013-05-15 富士通セミコンダクター株式会社 半導体装置の製造方法
US7871895B2 (en) * 2008-02-19 2011-01-18 International Business Machines Corporation Method and structure for relieving transistor performance degradation due to shallow trench isolation induced stress
KR102102815B1 (ko) 2013-09-26 2020-04-22 인텔 코포레이션 Ｎｍｏｓ 구조체들에서 전위가 높아진 변형을 형성하는 방법
US10204982B2 (en) * 2013-10-08 2019-02-12 Stmicroelectronics, Inc. Semiconductor device with relaxation reduction liner and associated methods
FR3024587B1 (fr) * 2014-08-01 2018-01-26 Soitec Procede de fabrication d'une structure hautement resistive
US10822692B2 (en) 2016-08-12 2020-11-03 University Of North Texas Binary Ag—Cu amorphous thin-films for electronic applications
KR102549340B1 (ko) * 2016-09-27 2023-06-28 삼성전자주식회사 반도체 장치 및 이의 제조 방법
CN110880473B (zh) * 2018-09-06 2025-02-25 长鑫存储技术有限公司 半导体器件、半导体器件制造方法

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03203351A (ja) * 1989-12-29 1991-09-05 Nec Corp 半導体装置及びその製造方法
JPH09205140A (ja) * 1995-11-21 1997-08-05 Toshiba Corp 素子分離半導体基板およびその製造方法
JPH10242259A (ja) * 1997-02-27 1998-09-11 Nec Corp 半導体装置およびその製造方法
JP2000114362A (ja) * 1998-10-02 2000-04-21 Nec Corp 半導体装置の製造方法
JP2000124304A (ja) * 1998-10-20 2000-04-28 Samsung Electronics Co Ltd 半導体装置の素子分離膜形成方法
JP2000286254A (ja) * 1999-03-31 2000-10-13 Hitachi Ltd 半導体集積回路装置およびその製造方法
JP2002289681A (ja) * 2001-03-26 2002-10-04 Mitsui Chemicals Inc 半導体装置
JP2004039902A (ja) * 2002-07-04 2004-02-05 Renesas Technology Corp 半導体装置およびその製造方法
WO2004023539A1 (ja) * 2002-09-06 2004-03-18 Asahi Glass Company, Limited 半導体集積回路用絶縁膜研磨剤組成物および半導体集積回路の製造方法

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0547918A (ja) 1991-08-13 1993-02-26 Hitachi Ltd 半導体装置の製造方法
JPH05114646A (ja) 1991-10-24 1993-05-07 Fujitsu Ltd 半導体装置の製造方法
JPH0697274A (ja) 1992-09-14 1994-04-08 Hitachi Ltd 素子分離方法
JPH0897210A (ja) 1994-09-28 1996-04-12 Mitsubishi Electric Corp 半導体装置及びその製造方法
JP3542189B2 (ja) * 1995-03-08 2004-07-14 株式会社ルネサステクノロジ 半導体装置の製造方法及び半導体装置
US5707888A (en) * 1995-05-04 1998-01-13 Lsi Logic Corporation Oxide formed in semiconductor substrate by implantation of substrate with a noble gas prior to oxidation
TW388096B (en) 1996-06-10 2000-04-21 Texas Instruments Inc Integrated circuit insulator and method
JPH1187489A (ja) 1997-09-10 1999-03-30 Asahi Chem Ind Co Ltd ポーラスシリコンを用いた素子分離膜形成方法
JP3519589B2 (ja) 1997-12-24 2004-04-19 株式会社ルネサステクノロジ 半導体集積回路の製造方法
JP3178412B2 (ja) 1998-04-27 2001-06-18 日本電気株式会社 トレンチ・アイソレーション構造の形成方法
US6469390B2 (en) 1999-01-26 2002-10-22 Agere Systems Guardian Corp. Device comprising thermally stable, low dielectric constant material
JP2001144170A (ja) 1999-11-11 2001-05-25 Mitsubishi Electric Corp 半導体装置およびその製造方法
JP2002009245A (ja) 2000-06-21 2002-01-11 Nec Corp 誘電体分離型半導体装置
JP3346762B2 (ja) 2000-11-10 2002-11-18 京セラ株式会社 磁気ヘッド組立用治具
JP2003031568A (ja) 2001-07-12 2003-01-31 Toshiba Corp 半導体装置の製造方法及び半導体装置
JP2003031650A (ja) 2001-07-13 2003-01-31 Toshiba Corp 半導体装置の製造方法
TWI252565B (en) * 2002-06-24 2006-04-01 Hitachi Ltd Semiconductor device and manufacturing method thereof

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03203351A (ja) * 1989-12-29 1991-09-05 Nec Corp 半導体装置及びその製造方法
JPH09205140A (ja) * 1995-11-21 1997-08-05 Toshiba Corp 素子分離半導体基板およびその製造方法
JPH10242259A (ja) * 1997-02-27 1998-09-11 Nec Corp 半導体装置およびその製造方法
JP2000114362A (ja) * 1998-10-02 2000-04-21 Nec Corp 半導体装置の製造方法
JP2000124304A (ja) * 1998-10-20 2000-04-28 Samsung Electronics Co Ltd 半導体装置の素子分離膜形成方法
JP2000286254A (ja) * 1999-03-31 2000-10-13 Hitachi Ltd 半導体集積回路装置およびその製造方法
JP2002289681A (ja) * 2001-03-26 2002-10-04 Mitsui Chemicals Inc 半導体装置
JP2004039902A (ja) * 2002-07-04 2004-02-05 Renesas Technology Corp 半導体装置およびその製造方法
WO2004023539A1 (ja) * 2002-09-06 2004-03-18 Asahi Glass Company, Limited 半導体集積回路用絶縁膜研磨剤組成物および半導体集積回路の製造方法

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009027131A (ja) * 2007-06-20 2009-02-05 Toshiba Corp 半導体装置およびその製造方法
WO2009022719A1 (ja) * 2007-08-16 2009-02-19 National University Corporation Tohoku University 半導体装置及びその製造方法
JPWO2009022719A1 (ja) * 2007-08-16 2010-11-18 国立大学法人東北大学 半導体装置及びその製造方法
WO2010073947A1 (ja) * 2008-12-25 2010-07-01 国立大学法人東北大学 半導体装置及びその製造方法
WO2011138906A1 (ja) * 2010-05-07 2011-11-10 国立大学法人東北大学 半導体装置の製造方法
JP2012009791A (ja) * 2010-06-28 2012-01-12 Panasonic Corp 固体撮像装置及びその製造方法
WO2012060399A1 (ja) * 2010-11-05 2012-05-10 Ａｚエレクトロニックマテリアルズ株式会社 アイソレーション構造の形成方法
JP2012099753A (ja) * 2010-11-05 2012-05-24 Az Electronic Materials Kk アイソレーション構造の形成方法
US8969172B2 (en) 2010-11-05 2015-03-03 Az Electronic Materials Usa Corp. Method for forming isolation structure
KR101841907B1 (ko) 2010-11-05 2018-03-26 메르크 파텐트 게엠베하 아이솔레이션 구조의 형성 방법
JP2012134302A (ja) * 2010-12-21 2012-07-12 Jsr Corp トレンチ埋め込み方法、及びトレンチ埋め込み用組成物
JP2013074169A (ja) * 2011-09-28 2013-04-22 Kyocera Corp 薄膜配線基板

Also Published As

Publication number Publication date
TWI282141B (en) 2007-06-01
US20050269662A1 (en) 2005-12-08
CN100461414C (zh) 2009-02-11
KR20060048071A (ko) 2006-05-18
TW200605264A (en) 2006-02-01
KR100732647B1 (ko) 2007-06-27
US7279769B2 (en) 2007-10-09
CN1716607A (zh) 2006-01-04

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