JP2001196529A - 半導体装置及びその配線方法 - Google Patents

半導体装置及びその配線方法

Info

Publication number
JP2001196529A
JP2001196529A JP2000007923A JP2000007923A JP2001196529A JP 2001196529 A JP2001196529 A JP 2001196529A JP 2000007923 A JP2000007923 A JP 2000007923A JP 2000007923 A JP2000007923 A JP 2000007923A JP 2001196529 A JP2001196529 A JP 2001196529A
Authority
JP
Japan
Prior art keywords
semiconductor chip
pad electrode
circuit board
relay
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2000007923A
Other languages
English (en)
Japanese (ja)
Other versions
JP2001196529A5 (https=
Inventor
Isao Nojiri
勲 野尻
Ritsu Makabe
立 真壁
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP2000007923A priority Critical patent/JP2001196529A/ja
Priority to US09/654,875 priority patent/US7071574B1/en
Priority to KR10-2000-0059073A priority patent/KR100386995B1/ko
Priority to TW089121084A priority patent/TW462097B/zh
Publication of JP2001196529A publication Critical patent/JP2001196529A/ja
Priority to US11/402,944 priority patent/US7288837B2/en
Publication of JP2001196529A5 publication Critical patent/JP2001196529A5/ja
Priority to US11/902,827 priority patent/US20080023848A1/en
Priority to US11/902,826 priority patent/US7547963B2/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/012—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps
    • H10W72/01221—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps using local deposition
    • H10W72/01223—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps using local deposition in liquid form, e.g. by dispensing droplets or by screen printing
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H10W72/07541—Controlling the environment, e.g. atmosphere composition or temperature
    • H10W72/07554—Controlling the environment, e.g. atmosphere composition or temperature changes in dispositions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/29—Bond pads specially adapted therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/5445—Dispositions of bond wires being orthogonal to a side surface of the chip, e.g. parallel arrangements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/547—Dispositions of multiple bond wires
    • H10W72/5473—Dispositions of multiple bond wires multiple bond wires connected to a common bond pad
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/551—Materials of bond wires
    • H10W72/552—Materials of bond wires comprising metals or metalloids, e.g. silver
    • H10W72/5522—Materials of bond wires comprising metals or metalloids, e.g. silver comprising gold [Au]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/59—Bond pads specially adapted therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/931—Shapes of bond pads
    • H10W72/932—Plan-view shape, i.e. in top view
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/931—Shapes of bond pads
    • H10W72/936—Multiple bond pads having different shapes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/722—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/732—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/752—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/753—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between laterally-adjacent chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Wire Bonding (AREA)
JP2000007923A 2000-01-17 2000-01-17 半導体装置及びその配線方法 Pending JP2001196529A (ja)

Priority Applications (7)

Application Number Priority Date Filing Date Title
JP2000007923A JP2001196529A (ja) 2000-01-17 2000-01-17 半導体装置及びその配線方法
US09/654,875 US7071574B1 (en) 2000-01-17 2000-09-05 Semiconductor device and its wiring method
KR10-2000-0059073A KR100386995B1 (ko) 2000-01-17 2000-10-07 반도체 장치 및 그 배선 방법
TW089121084A TW462097B (en) 2000-01-17 2000-10-09 Semiconductor device and its wiring method
US11/402,944 US7288837B2 (en) 2000-01-17 2006-04-13 Semiconductor device and its writing method
US11/902,827 US20080023848A1 (en) 2000-01-17 2007-09-26 Semiconductor device and its wiring method
US11/902,826 US7547963B2 (en) 2000-01-17 2007-09-26 Semiconductor device and its wiring method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2000007923A JP2001196529A (ja) 2000-01-17 2000-01-17 半導体装置及びその配線方法

Publications (2)

Publication Number Publication Date
JP2001196529A true JP2001196529A (ja) 2001-07-19
JP2001196529A5 JP2001196529A5 (https=) 2007-03-01

Family

ID=18536276

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2000007923A Pending JP2001196529A (ja) 2000-01-17 2000-01-17 半導体装置及びその配線方法

Country Status (4)

Country Link
US (4) US7071574B1 (https=)
JP (1) JP2001196529A (https=)
KR (1) KR100386995B1 (https=)
TW (1) TW462097B (https=)

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1247706A2 (en) 2001-04-02 2002-10-09 Honda Giken Kogyo Kabushiki Kaisha Anti-theft device installation structure for motorcycle
US7115977B2 (en) 2000-09-28 2006-10-03 Oki Electric Industry Co., Ltd. Multi-chip package type semiconductor device
US7132752B2 (en) 2003-10-31 2006-11-07 Oki Electric Industry Co., Ltd. Semiconductor chip and semiconductor device including lamination of semiconductor chips
WO2007146307A3 (en) * 2006-06-15 2008-03-06 Marvell World Trade Ltd Stack die packages
US7420206B2 (en) 2006-07-12 2008-09-02 Genusion Inc. Interposer, semiconductor chip mounted sub-board, and semiconductor package
JP2008288450A (ja) * 2007-05-18 2008-11-27 Renesas Technology Corp 半導体装置
WO2008146426A1 (ja) * 2007-06-01 2008-12-04 Panasonic Corporation 半導体装置
US7576431B2 (en) 2003-12-25 2009-08-18 Oki Semiconductor Co., Ltd. Semiconductor chip package and multichip package
US7723835B2 (en) 2003-10-20 2010-05-25 Genusion, Inc. Semiconductor device package structure
JP2010118395A (ja) * 2008-11-11 2010-05-27 Seiko Epson Corp 半導体装置及び半導体装置の製造方法
WO2014017514A1 (ja) * 2012-07-26 2014-01-30 株式会社村田製作所 複合電子部品及びそれを備える電子装置
EP1434264A3 (en) * 2002-12-27 2017-01-18 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method using the transfer technique

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001196529A (ja) * 2000-01-17 2001-07-19 Mitsubishi Electric Corp 半導体装置及びその配線方法
US6979894B1 (en) * 2001-09-27 2005-12-27 Marvell International Ltd. Integrated chip package having intermediate substrate
DE10251527B4 (de) * 2002-11-04 2007-01-25 Infineon Technologies Ag Verfahren zur Herstellung einer Stapelanordnung eines Speichermoduls
JP2006032871A (ja) * 2004-07-22 2006-02-02 Toshiba Corp 半導体装置
US20060202317A1 (en) * 2005-03-14 2006-09-14 Farid Barakat Method for MCP packaging for balanced performance
TWI352416B (en) * 2006-09-12 2011-11-11 Chipmos Technologies Inc Stacked chip package structure with unbalanced lea
US7750450B2 (en) * 2006-12-20 2010-07-06 Intel Corporation Stacked die package with stud spacers
KR20100117977A (ko) 2009-04-27 2010-11-04 삼성전자주식회사 반도체 패키지
US20110084374A1 (en) * 2009-10-08 2011-04-14 Jen-Chung Chen Semiconductor package with sectioned bonding wire scheme
US8536716B1 (en) * 2009-12-31 2013-09-17 Micron Technology, Inc. Supply voltage or ground connections for integrated circuit device
US8531849B1 (en) 2010-03-31 2013-09-10 Micron Technology, Inc. Supply voltage or ground connections including bond pad interconnects for integrated circuit device
KR20120024099A (ko) * 2010-09-06 2012-03-14 삼성전자주식회사 멀티-칩 패키지 및 그의 제조 방법
US20120133381A1 (en) * 2010-11-30 2012-05-31 Electro Scientific Industries, Inc. Stackable semiconductor chip with edge features and methods of fabricating and processing same
KR20130019290A (ko) * 2011-08-16 2013-02-26 삼성전자주식회사 유니버설 인쇄 회로 기판 및 그것을 포함하는 메모리 카드
KR102037866B1 (ko) * 2013-02-05 2019-10-29 삼성전자주식회사 전자장치
JP2015002308A (ja) * 2013-06-18 2015-01-05 ピーエスフォー ルクスコ エスエイアールエルＰＳ４ Ｌｕｘｃｏ Ｓ．ａ．ｒ．ｌ． 半導体装置及びその製造方法
KR102108325B1 (ko) * 2013-10-14 2020-05-08 삼성전자주식회사 반도체 패키지
WO2016046339A1 (en) * 2014-09-24 2016-03-31 Koninklijke Philips N.V. Printed circuit board and printed circuit board arrangement

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JPH09186289A (ja) 1995-12-28 1997-07-15 Lucent Technol Inc 多層積層化集積回路チップ組立体
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JPH1070153A (ja) * 1996-08-26 1998-03-10 Hitachi Ltd 電子部品の接続方法
US5847445A (en) * 1996-11-04 1998-12-08 Micron Technology, Inc. Die assemblies using suspended bond wires, carrier substrates and dice having wire suspension structures, and methods of fabricating same
EP0890989A4 (en) * 1997-01-24 2006-11-02 Rohm Co Ltd SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD
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JP3481444B2 (ja) * 1998-01-14 2003-12-22 シャープ株式会社 半導体装置及びその製造方法
US6159765A (en) * 1998-03-06 2000-12-12 Microchip Technology, Incorporated Integrated circuit package having interchip bonding and method therefor
US5977640A (en) * 1998-06-26 1999-11-02 International Business Machines Corporation Highly integrated chip-on-chip packaging
US6376914B2 (en) * 1999-12-09 2002-04-23 Atmel Corporation Dual-die integrated circuit package
JP2001196529A (ja) * 2000-01-17 2001-07-19 Mitsubishi Electric Corp 半導体装置及びその配線方法
US6252305B1 (en) * 2000-02-29 2001-06-26 Advanced Semiconductor Engineering, Inc. Multichip module having a stacked chip arrangement
JP4454181B2 (ja) * 2001-05-15 2010-04-21 富士通マイクロエレクトロニクス株式会社 半導体装置

Cited By (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7115977B2 (en) 2000-09-28 2006-10-03 Oki Electric Industry Co., Ltd. Multi-chip package type semiconductor device
US8053278B2 (en) 2000-09-28 2011-11-08 Oki Semiconductor Co., Ltd. Multi-chip package type semiconductor device
EP1247706A2 (en) 2001-04-02 2002-10-09 Honda Giken Kogyo Kabushiki Kaisha Anti-theft device installation structure for motorcycle
EP1434264A3 (en) * 2002-12-27 2017-01-18 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method using the transfer technique
US7723835B2 (en) 2003-10-20 2010-05-25 Genusion, Inc. Semiconductor device package structure
US7514796B2 (en) 2003-10-31 2009-04-07 Oki Semiconductor Co., Ltd. Semiconductor chip capable of being laminated and a semiconductor device including the lamination of a plurality of semiconductor chips
US7132752B2 (en) 2003-10-31 2006-11-07 Oki Electric Industry Co., Ltd. Semiconductor chip and semiconductor device including lamination of semiconductor chips
US7868470B2 (en) 2003-12-25 2011-01-11 Oki Semiconductor Co., Ltd. Semiconductor chip package and multichip package
US7576431B2 (en) 2003-12-25 2009-08-18 Oki Semiconductor Co., Ltd. Semiconductor chip package and multichip package
US7825521B2 (en) 2006-06-15 2010-11-02 Marvell World Trade Ltd. Stack die packages
WO2007146307A3 (en) * 2006-06-15 2008-03-06 Marvell World Trade Ltd Stack die packages
US8044498B2 (en) 2006-07-12 2011-10-25 Genusion Inc. Interposer, semiconductor chip mounted sub-board, and semiconductor package
US7420206B2 (en) 2006-07-12 2008-09-02 Genusion Inc. Interposer, semiconductor chip mounted sub-board, and semiconductor package
JP2008288450A (ja) * 2007-05-18 2008-11-27 Renesas Technology Corp 半導体装置
WO2008146426A1 (ja) * 2007-06-01 2008-12-04 Panasonic Corporation 半導体装置
JP2010118395A (ja) * 2008-11-11 2010-05-27 Seiko Epson Corp 半導体装置及び半導体装置の製造方法
US8274142B2 (en) 2008-11-11 2012-09-25 Seiko Epson Corporation Semiconductor device having stacked multiple substrates and method for producing same
WO2014017514A1 (ja) * 2012-07-26 2014-01-30 株式会社村田製作所 複合電子部品及びそれを備える電子装置
JP5472557B1 (ja) * 2012-07-26 2014-04-16 株式会社村田製作所 複合電子部品及びそれを備える電子装置

Also Published As

Publication number Publication date
TW462097B (en) 2001-11-01
US20080023848A1 (en) 2008-01-31
US7547963B2 (en) 2009-06-16
US7071574B1 (en) 2006-07-04
KR20010076213A (ko) 2001-08-11
KR100386995B1 (ko) 2003-06-12
US20080023847A1 (en) 2008-01-31
US7288837B2 (en) 2007-10-30
US20060186526A1 (en) 2006-08-24

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