ITMI942324A0 - Circuito di prova di bit multipli di dispositivi di memoria a semiconduttore - Google Patents

Circuito di prova di bit multipli di dispositivi di memoria a semiconduttore

Info

Publication number
ITMI942324A0
ITMI942324A0 ITMI942324A ITMI942324A ITMI942324A0 IT MI942324 A0 ITMI942324 A0 IT MI942324A0 IT MI942324 A ITMI942324 A IT MI942324A IT MI942324 A ITMI942324 A IT MI942324A IT MI942324 A0 ITMI942324 A0 IT MI942324A0
Authority
IT
Italy
Prior art keywords
semiconductor memory
memory devices
test circuit
multiple bit
bit test
Prior art date
Application number
ITMI942324A
Other languages
English (en)
Inventor
Choong-Sun Shin
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of ITMI942324A0 publication Critical patent/ITMI942324A0/it
Publication of ITMI942324A1 publication Critical patent/ITMI942324A1/it
Application granted granted Critical
Publication of IT1275666B1 publication Critical patent/IT1275666B1/it

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G11C29/30—Accessing single arrays
    • G11C29/34—Accessing multiple bits simultaneously
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/38—Response verification devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/1201—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details comprising I/O circuitry
IT94MI002324A 1993-11-17 1994-11-16 Circuito di prova di bit multipli di dispositivi di memoria a semiconduttore IT1275666B1 (it)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR93024485A KR960008824B1 (en) 1993-11-17 1993-11-17 Multi bit test circuit and method of semiconductor memory device

Publications (3)

Publication Number Publication Date
ITMI942324A0 true ITMI942324A0 (it) 1994-11-16
ITMI942324A1 ITMI942324A1 (it) 1996-05-16
IT1275666B1 IT1275666B1 (it) 1997-10-17

Family

ID=19368293

Family Applications (1)

Application Number Title Priority Date Filing Date
IT94MI002324A IT1275666B1 (it) 1993-11-17 1994-11-16 Circuito di prova di bit multipli di dispositivi di memoria a semiconduttore

Country Status (7)

Country Link
US (1) US5483493A (it)
JP (1) JP3645294B2 (it)
KR (1) KR960008824B1 (it)
CN (1) CN1043928C (it)
DE (1) DE4441007C2 (it)
FR (1) FR2712720B1 (it)
IT (1) IT1275666B1 (it)

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3361648B2 (ja) * 1995-03-15 2003-01-07 富士通株式会社 データ圧縮試験機能を備えた半導体記憶装置及びその試験方法
KR0147632B1 (ko) * 1995-04-24 1998-11-02 김광호 반도체 메모리장치의 멀티 비트 테스트방법 및 테스트 회로
KR0172372B1 (ko) * 1995-12-22 1999-03-30 김광호 반도체 메모리 장치의 병합 데이타 출력 모드 선택 방법
US5983375A (en) * 1995-12-27 1999-11-09 Samsung Electronics, Co., Ltd. Multi-bit test circuit and method thereof
KR100192590B1 (ko) * 1996-08-09 1999-06-15 윤종용 반도체 메모리 장치의 병렬 비트 테스트회로
US5966388A (en) * 1997-01-06 1999-10-12 Micron Technology, Inc. High-speed test system for a memory device
KR100265758B1 (ko) * 1997-08-05 2000-09-15 윤종용 반도체장치의 병합된 데이터 입출력 회로 및 방법
KR100269299B1 (ko) * 1997-07-14 2000-10-16 윤종용 데이터패쓰(dq)수감소회로및감소방법과이를이용한반도체장치
JP2000076899A (ja) * 1998-08-26 2000-03-14 Oki Micro Design:Kk 半導体記憶装置
KR100307626B1 (ko) 1998-08-31 2001-11-30 윤종용 디램과버퍼메모리를갖는메모리로직복합집적회로장치
JP3322303B2 (ja) * 1998-10-28 2002-09-09 日本電気株式会社 半導体記憶装置
KR100346447B1 (ko) * 2000-06-30 2002-07-27 주식회사 하이닉스반도체 반도체 메모리 소자의 병렬 테스트 장치
KR20020049386A (ko) * 2000-12-19 2002-06-26 윤종용 테스트시 기입 데이터의 마스킹 동작이 가능한 반도체메모리 장치 및 데이터 마스킹 방법
DE10161042B4 (de) * 2001-12-12 2004-02-05 Infineon Technologies Ag Verfahren zum Betreiben eines Halbleiterspeichers und Halbleiterspeicher
CN1301464C (zh) * 2002-12-10 2007-02-21 威盛电子股份有限公司 容错存储器模块电路
DE10323413B4 (de) * 2003-05-23 2006-01-19 Infineon Technologies Ag Prüfverfahren, Prüfsockel und Prüfanordnung für Hochgeschwindigkeits- Halbleiterspeichereinrichtungen
DE10335132B3 (de) * 2003-07-31 2004-12-09 Infineon Technologies Ag Speicheranordnung eines Computersystems
DE102004027275A1 (de) * 2004-06-04 2005-12-29 Infineon Technologies Ag Integrierter Halbleiterspeicher
DE102004043051A1 (de) * 2004-09-06 2006-03-30 Infineon Technologies Ag Loop-back-Verfahren zur Vermessung des Interface-Timings von Halbleiterspeichervorrichtungen unter Verwendung des Normal-Mode-Speichers
KR20080114359A (ko) * 2007-06-27 2008-12-31 주식회사 하이닉스반도체 반도체 집적 회로 및 그의 불량 경로 검출 방법
US11145381B1 (en) 2020-09-09 2021-10-12 Powerchip Semiconductor Manufacturing Corporation Memory with test function and test method thereof

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3751002T2 (de) * 1986-10-20 1995-10-05 Nippon Telegraph & Telephone Halbleiterspeicher.
FR2607956A1 (fr) * 1986-12-05 1988-06-10 Eurotechnique Sa Procede de test des memoires integrees et memoires pour la mise en oeuvre du procede
JPH02146199A (ja) * 1988-11-28 1990-06-05 Mitsubishi Electric Corp 半導体記憶装置のテスト回路
JP2938470B2 (ja) * 1989-06-01 1999-08-23 三菱電機株式会社 半導体記憶装置
KR930008417B1 (ko) * 1990-06-18 1993-08-31 삼성전자 주식회사 반도체 메모리 장치의 다중 비트 병렬 테스트방법
JPH0419899A (ja) * 1990-05-11 1992-01-23 Mitsubishi Electric Corp 半導体記憶装置のためのテスト装置
JP2673395B2 (ja) * 1990-08-29 1997-11-05 三菱電機株式会社 半導体記憶装置およびそのテスト方法
JPH04356799A (ja) * 1990-08-29 1992-12-10 Mitsubishi Electric Corp 半導体記憶装置
DE4028819A1 (de) * 1990-09-11 1992-03-12 Siemens Ag Schaltungsanordnung zum testen eines halbleiterspeichers mittels paralleltests mit verschiedenen testbitmustern
JP2863012B2 (ja) * 1990-12-18 1999-03-03 三菱電機株式会社 半導体記憶装置
JPH04322000A (ja) * 1991-04-23 1992-11-11 Hitachi Ltd 半導体記憶装置
US5315553A (en) * 1991-06-10 1994-05-24 Texas Instruments Incorporated Memory circuit test system using separate ROM having test values stored therein
GB9116493D0 (en) * 1991-07-30 1991-09-11 Inmos Ltd Read and write circuitry for a memory
KR950001293B1 (ko) * 1992-04-22 1995-02-15 삼성전자주식회사 반도체 메모리칩의 병렬테스트 회로
JPH0636593A (ja) * 1992-07-14 1994-02-10 Mitsubishi Electric Corp 半導体記憶装置

Also Published As

Publication number Publication date
KR950015397A (ko) 1995-06-16
CN1043928C (zh) 1999-06-30
CN1111017A (zh) 1995-11-01
ITMI942324A1 (it) 1996-05-16
FR2712720A1 (fr) 1995-05-24
FR2712720B1 (fr) 1996-07-12
IT1275666B1 (it) 1997-10-17
KR960008824B1 (en) 1996-07-05
DE4441007A1 (de) 1995-05-18
DE4441007C2 (de) 1998-07-30
US5483493A (en) 1996-01-09
JP3645294B2 (ja) 2005-05-11
JPH07182897A (ja) 1995-07-21

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Legal Events

Date Code Title Description
0001 Granted
TA Fee payment date (situation as of event date), data collected since 19931001

Effective date: 19971126