IT1274305B - Dispositivo a semiconduttore di memoria - Google Patents
Dispositivo a semiconduttore di memoriaInfo
- Publication number
- IT1274305B IT1274305B ITMI941609A ITMI941609A IT1274305B IT 1274305 B IT1274305 B IT 1274305B IT MI941609 A ITMI941609 A IT MI941609A IT MI941609 A ITMI941609 A IT MI941609A IT 1274305 B IT1274305 B IT 1274305B
- Authority
- IT
- Italy
- Prior art keywords
- semiconductor device
- memory semiconductor
- memory
- semiconductor
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/24—Memory cell safety or protection circuits, e.g. arrangements for preventing inadvertent reading or writing; Status cells; Test cells
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Dram (AREA)
- Static Random-Access Memory (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5224546A JP2994534B2 (ja) | 1993-09-09 | 1993-09-09 | 半導体記憶装置 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| ITMI941609A0 ITMI941609A0 (it) | 1994-07-27 |
| ITMI941609A1 ITMI941609A1 (it) | 1996-01-27 |
| IT1274305B true IT1274305B (it) | 1997-07-17 |
Family
ID=16815492
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| ITMI941609A IT1274305B (it) | 1993-09-09 | 1994-07-27 | Dispositivo a semiconduttore di memoria |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US5557582A (it) |
| JP (1) | JP2994534B2 (it) |
| KR (1) | KR0161307B1 (it) |
| IT (1) | IT1274305B (it) |
Families Citing this family (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07210445A (ja) * | 1994-01-20 | 1995-08-11 | Mitsubishi Electric Corp | 半導体記憶装置およびコンピュータ |
| JPH09282346A (ja) * | 1996-04-12 | 1997-10-31 | Fujitsu Ltd | セル消費電流特性算出システム |
| JPH09320261A (ja) * | 1996-05-30 | 1997-12-12 | Mitsubishi Electric Corp | 半導体記憶装置および制御信号発生回路 |
| KR100431316B1 (ko) * | 1997-06-27 | 2004-10-08 | 주식회사 하이닉스반도체 | 디램패키지및그의어드레스라인및데이터라인폭변화방법 |
| JP4057125B2 (ja) * | 1998-01-23 | 2008-03-05 | 株式会社ルネサステクノロジ | 半導体記憶装置 |
| KR100343290B1 (ko) * | 2000-03-21 | 2002-07-15 | 윤종용 | 반도체 메모리 장치의 입출력 감지 증폭기 회로 |
| KR100411394B1 (ko) * | 2001-06-29 | 2003-12-18 | 주식회사 하이닉스반도체 | 메모리장치의 데이터출력회로 |
| JP2009123292A (ja) | 2007-11-15 | 2009-06-04 | Toshiba Corp | 半導体記憶装置 |
| KR102341264B1 (ko) * | 2015-02-02 | 2021-12-20 | 삼성전자주식회사 | 래치를 이용한 레이저 검출기 및 이를 포함하는 반도체 장치 |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4922461A (en) * | 1988-03-30 | 1990-05-01 | Kabushiki Kaisha Toshiba | Static random access memory with address transition detector |
-
1993
- 1993-09-09 JP JP5224546A patent/JP2994534B2/ja not_active Expired - Lifetime
-
1994
- 1994-06-22 US US08/264,076 patent/US5557582A/en not_active Expired - Lifetime
- 1994-07-01 KR KR1019940015743A patent/KR0161307B1/ko not_active IP Right Cessation
- 1994-07-27 IT ITMI941609A patent/IT1274305B/it active IP Right Grant
Also Published As
| Publication number | Publication date |
|---|---|
| ITMI941609A1 (it) | 1996-01-27 |
| US5557582A (en) | 1996-09-17 |
| ITMI941609A0 (it) | 1994-07-27 |
| JPH0778474A (ja) | 1995-03-20 |
| JP2994534B2 (ja) | 1999-12-27 |
| KR950010084A (ko) | 1995-04-26 |
| KR0161307B1 (ko) | 1999-02-01 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| 0001 | Granted | ||
| TA | Fee payment date (situation as of event date), data collected since 19931001 |
Effective date: 19970730 |