DE69406037D1 - Nicht-flüchtige Halbleiterspeicheranordnung - Google Patents

Nicht-flüchtige Halbleiterspeicheranordnung

Info

Publication number
DE69406037D1
DE69406037D1 DE69406037T DE69406037T DE69406037D1 DE 69406037 D1 DE69406037 D1 DE 69406037D1 DE 69406037 T DE69406037 T DE 69406037T DE 69406037 T DE69406037 T DE 69406037T DE 69406037 D1 DE69406037 D1 DE 69406037D1
Authority
DE
Germany
Prior art keywords
memory device
semiconductor memory
volatile semiconductor
volatile
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69406037T
Other languages
English (en)
Other versions
DE69406037T2 (de
Inventor
Toshiyuki Hayakawa
Ryouhei Kirisawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Publication of DE69406037D1 publication Critical patent/DE69406037D1/de
Application granted granted Critical
Publication of DE69406037T2 publication Critical patent/DE69406037T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
DE69406037T 1993-04-01 1994-04-05 Nicht-flüchtige Halbleiterspeicheranordnung Expired - Lifetime DE69406037T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5074886A JP2825407B2 (ja) 1993-04-01 1993-04-01 不揮発性半導体記憶装置

Publications (2)

Publication Number Publication Date
DE69406037D1 true DE69406037D1 (de) 1997-11-13
DE69406037T2 DE69406037T2 (de) 1998-02-26

Family

ID=13560303

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69406037T Expired - Lifetime DE69406037T2 (de) 1993-04-01 1994-04-05 Nicht-flüchtige Halbleiterspeicheranordnung

Country Status (5)

Country Link
US (1) US5464998A (de)
EP (1) EP0618621B1 (de)
JP (1) JP2825407B2 (de)
KR (1) KR0159325B1 (de)
DE (1) DE69406037T2 (de)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3404064B2 (ja) * 1993-03-09 2003-05-06 株式会社日立製作所 半導体装置及びその製造方法
US5666307A (en) * 1995-11-14 1997-09-09 Programmable Microelectronics Corporation PMOS flash memory cell capable of multi-level threshold voltage storage
US5687118A (en) * 1995-11-14 1997-11-11 Programmable Microelectronics Corporation PMOS memory cell with hot electron injection programming and tunnelling erasing
US5793677A (en) * 1996-06-18 1998-08-11 Hu; Chung-You Using floating gate devices as select gate devices for NAND flash memory and its bias scheme
US5912489A (en) * 1996-06-18 1999-06-15 Advanced Micro Devices, Inc. Dual source side polysilicon select gate structure utilizing single tunnel oxide for NAND array flash memory
JP3489958B2 (ja) * 1997-03-19 2004-01-26 富士通株式会社 不揮発性半導体記憶装置
US6812521B1 (en) * 1999-11-16 2004-11-02 Advanced Micro Devices, Inc. Method and apparatus for improved performance of flash memory cell devices
US6556481B1 (en) 2001-02-21 2003-04-29 Aplus Flash Technology, Inc. 3-step write operation nonvolatile semiconductor one-transistor, nor-type flash EEPROM memory cell
US6620682B1 (en) 2001-02-27 2003-09-16 Aplus Flash Technology, Inc. Set of three level concurrent word line bias conditions for a nor type flash memory array
US6862223B1 (en) * 2002-07-05 2005-03-01 Aplus Flash Technology, Inc. Monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout
US20040088474A1 (en) * 2002-10-30 2004-05-06 Lin Jin Shin NAND type flash memory disk device and method for detecting the logical address
JP4817615B2 (ja) * 2004-05-31 2011-11-16 株式会社東芝 不揮発性半導体記憶装置
US7164608B2 (en) * 2004-07-28 2007-01-16 Aplus Flash Technology, Inc. NVRAM memory cell architecture that integrates conventional SRAM and flash cells

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0639860B1 (de) * 1988-10-21 2000-06-28 Kabushiki Kaisha Toshiba Nichtflüchtiger Halbleiterspeicher
JP2772020B2 (ja) * 1989-02-22 1998-07-02 株式会社東芝 Ｍｏｓ型半導体装置
JPH04137767A (ja) * 1990-09-28 1992-05-12 Toshiba Corp 不揮発性半導体記憶装置およびその製造方法

Also Published As

Publication number Publication date
JPH06291287A (ja) 1994-10-18
US5464998A (en) 1995-11-07
EP0618621B1 (de) 1997-10-08
DE69406037T2 (de) 1998-02-26
KR0159325B1 (ko) 1998-12-01
EP0618621A1 (de) 1994-10-05
JP2825407B2 (ja) 1998-11-18

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition