DE69230750D1 - Nichtflüchtige Halbleiterspeicheranordnung - Google Patents

Nichtflüchtige Halbleiterspeicheranordnung

Info

Publication number
DE69230750D1
DE69230750D1 DE69230750T DE69230750T DE69230750D1 DE 69230750 D1 DE69230750 D1 DE 69230750D1 DE 69230750 T DE69230750 T DE 69230750T DE 69230750 T DE69230750 T DE 69230750T DE 69230750 D1 DE69230750 D1 DE 69230750D1
Authority
DE
Germany
Prior art keywords
memory device
semiconductor memory
volatile semiconductor
volatile
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69230750T
Other languages
English (en)
Other versions
DE69230750T2 (de
Inventor
Kiyokazu Hashimoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Electronics Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Publication of DE69230750D1 publication Critical patent/DE69230750D1/de
Application granted granted Critical
Publication of DE69230750T2 publication Critical patent/DE69230750T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/028—Detection or location of defective auxiliary circuits, e.g. defective refresh counters with adaption or trimming of parameters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
    • G11C16/16—Circuits for erasing electrically, e.g. erase voltage switching circuits for erasing blocks, e.g. arrays, words, groups
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing
    • G11C29/50004—Marginal testing, e.g. race, voltage or current testing of threshold voltage
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2201/00—Indexing scheme relating to error detection, to error correction, and to monitoring
    • G06F2201/81—Threshold
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
DE69230750T 1991-12-27 1992-12-21 Nichtflüchtige Halbleiterspeicheranordnung Expired - Fee Related DE69230750T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP03359813A JP3080743B2 (ja) 1991-12-27 1991-12-27 不揮発性半導体記憶装置

Publications (2)

Publication Number Publication Date
DE69230750D1 true DE69230750D1 (de) 2000-04-13
DE69230750T2 DE69230750T2 (de) 2000-10-05

Family

ID=18466426

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69230750T Expired - Fee Related DE69230750T2 (de) 1991-12-27 1992-12-21 Nichtflüchtige Halbleiterspeicheranordnung

Country Status (5)

Country Link
US (1) US5513193A (de)
EP (1) EP0548866B1 (de)
JP (1) JP3080743B2 (de)
KR (1) KR960002736B1 (de)
DE (1) DE69230750T2 (de)

Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1995024057A2 (en) * 1994-03-03 1995-09-08 Rohm Corporation Low voltage one transistor flash eeprom cell using fowler-nordheim programming and erase
FR2718559B1 (fr) * 1994-04-08 1996-06-07 Sgs Thomson Microelectronics Mémoire non volatile modifiable électriquement incorporant des fonctions de test.
DE69426818T2 (de) * 1994-06-10 2001-10-18 Stmicroelectronics S.R.L., Agrate Brianza Fehlertolerantes Speichergerät, insbesondere des Typs "flash EEPROM"
JP2780674B2 (ja) * 1995-06-20 1998-07-30 日本電気株式会社 不揮発性半導体記憶装置
JPH0935500A (ja) * 1995-07-21 1997-02-07 Toshiba Corp 不揮発性半導体記憶装置のスクリーニング方法
US5610867A (en) * 1995-09-28 1997-03-11 International Business Machines Corporation DRAM signal margin test method
KR0161867B1 (ko) * 1995-10-11 1998-12-01 문정환 반도체 소자의 가변 문턱전압 조절회로
KR100223868B1 (ko) * 1996-07-12 1999-10-15 구본준 비휘발성 메모리를 프로그램하는 방법
US6781883B1 (en) 1997-03-20 2004-08-24 Altera Corporation Apparatus and method for margin testing single polysilicon EEPROM cells
US6268623B1 (en) * 1997-03-20 2001-07-31 Altera Corporation Apparatus and method for margin testing single polysilicon EEPROM cells
US6146943A (en) * 1997-07-09 2000-11-14 Hyundai Electronics Industries Co., Ltd. Method for fabricating nonvolatile memory device
US5912836A (en) * 1997-12-01 1999-06-15 Amic Technology, Inc. Circuit for detecting both charge gain and charge loss properties in a non-volatile memory array
US5991196A (en) * 1997-12-16 1999-11-23 Microchip Technology Incorporated Reprogrammable memory device with variable page size
JP3344313B2 (ja) * 1998-03-25 2002-11-11 日本電気株式会社 不揮発性半導体メモリ装置
US6914827B2 (en) * 1999-07-28 2005-07-05 Samsung Electronics Co., Ltd. Flash memory device capable of preventing an over-erase of flash memory cells and erase method thereof
US7366020B2 (en) * 1999-07-28 2008-04-29 Samsung Electronics Co., Ltd. Flash memory device capable of preventing an overerase of flash memory cells and erase method thereof
KR100308192B1 (ko) 1999-07-28 2001-11-01 윤종용 플래시 메모리 셀들의 과소거를 방지할 수 있는 플래시 메모리장치 및 그것의 소거 방법
KR100357693B1 (ko) 1999-12-06 2002-10-25 삼성전자 주식회사 향상된 소거 알고리즘이 내장된 불휘발성 반도체 메모리장치
KR20020091581A (ko) 2001-05-31 2002-12-06 삼성전자 주식회사 진행성 결함 특성을 갖는 메모리 셀을 검사할 수 있는플래시 메모리 장치
US7885119B2 (en) * 2006-07-20 2011-02-08 Sandisk Corporation Compensating for coupling during programming
US7894269B2 (en) * 2006-07-20 2011-02-22 Sandisk Corporation Nonvolatile memory and method for compensating during programming for perturbing charges of neighboring cells
US7660166B2 (en) * 2007-01-31 2010-02-09 Sandisk Il Ltd. Method of improving programming precision in flash memory
US7652929B2 (en) * 2007-09-17 2010-01-26 Sandisk Corporation Non-volatile memory and method for biasing adjacent word line for verify during programming

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57176587A (en) * 1981-04-24 1982-10-29 Hitachi Ltd Semiconductor ram device
US4460982A (en) * 1982-05-20 1984-07-17 Intel Corporation Intelligent electrically programmable and electrically erasable ROM
JPS6258500A (ja) * 1985-09-09 1987-03-14 Fujitsu Ltd 半導体記憶装置の試験方法
JPS62114200A (ja) * 1985-11-13 1987-05-25 Mitsubishi Electric Corp 半導体メモリ装置
JPS6323297A (ja) * 1987-05-15 1988-01-30 Nec Corp 信号線駆動回路
JPS6476596A (en) * 1987-09-18 1989-03-22 Oki Electric Ind Co Ltd Error of eeprom detecting device
US4809231A (en) * 1987-11-12 1989-02-28 Motorola, Inc. Method and apparatus for post-packaging testing of one-time programmable memories
US4841482A (en) * 1988-02-17 1989-06-20 Intel Corporation Leakage verification for flash EPROM
US5053990A (en) * 1988-02-17 1991-10-01 Intel Corporation Program/erase selection for flash memory
US5268870A (en) * 1988-06-08 1993-12-07 Eliyahou Harari Flash EEPROM system and intelligent programming and erasing methods therefor
US5142495A (en) * 1989-03-10 1992-08-25 Intel Corporation Variable load for margin mode
EP0413347A3 (en) * 1989-08-18 1991-06-05 Hitachi, Ltd. Semiconductor nonvolatile memory device
US5220533A (en) * 1991-11-06 1993-06-15 Altera Corporation Method and apparatus for preventing overerasure in a flash cell

Also Published As

Publication number Publication date
US5513193A (en) 1996-04-30
JP3080743B2 (ja) 2000-08-28
DE69230750T2 (de) 2000-10-05
KR930014611A (ko) 1993-07-23
KR960002736B1 (ko) 1996-02-26
EP0548866B1 (de) 2000-03-08
EP0548866A3 (de) 1994-02-09
JPH05182499A (ja) 1993-07-23
EP0548866A2 (de) 1993-06-30

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: NEC ELECTRONICS CORP., KAWASAKI, KANAGAWA, JP

8339 Ceased/non-payment of the annual fee