DE69614919D1 - Dateneingangsschaltung einer Halbleiterspeicherschaltung - Google Patents

Dateneingangsschaltung einer Halbleiterspeicherschaltung

Info

Publication number
DE69614919D1
DE69614919D1 DE69614919T DE69614919T DE69614919D1 DE 69614919 D1 DE69614919 D1 DE 69614919D1 DE 69614919 T DE69614919 T DE 69614919T DE 69614919 T DE69614919 T DE 69614919T DE 69614919 D1 DE69614919 D1 DE 69614919D1
Authority
DE
Germany
Prior art keywords
circuit
semiconductor memory
data input
input circuit
memory circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69614919T
Other languages
English (en)
Other versions
DE69614919T2 (de
Inventor
Tetsuro Takenaka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Lapis Semiconductor Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Application granted granted Critical
Publication of DE69614919D1 publication Critical patent/DE69614919D1/de
Publication of DE69614919T2 publication Critical patent/DE69614919T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
DE69614919T 1995-05-25 1996-05-22 Dateneingangsschaltung einer Halbleiterspeicherschaltung Expired - Lifetime DE69614919T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12608895A JP3394111B2 (ja) 1995-05-25 1995-05-25 半導体記憶装置のデータ入力回路

Publications (2)

Publication Number Publication Date
DE69614919D1 true DE69614919D1 (de) 2001-10-11
DE69614919T2 DE69614919T2 (de) 2002-04-11

Family

ID=14926312

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69614919T Expired - Lifetime DE69614919T2 (de) 1995-05-25 1996-05-22 Dateneingangsschaltung einer Halbleiterspeicherschaltung

Country Status (5)

Country Link
US (1) US5724287A (de)
EP (1) EP0744749B1 (de)
JP (1) JP3394111B2 (de)
KR (1) KR100303040B1 (de)
DE (1) DE69614919T2 (de)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100206922B1 (ko) * 1996-07-22 1999-07-01 구본준 라이트 제어회로
US6075730A (en) * 1997-10-10 2000-06-13 Rambus Incorporated High performance cost optimized memory with delayed memory writes
US5963487A (en) * 1997-12-16 1999-10-05 Cypress Semiconductor Corp. Write enabling circuitry for a semiconductor memory
US6087858A (en) * 1998-06-24 2000-07-11 Cypress Semiconductor Corp. Self-timed sense amplifier evaluation scheme
US5978280A (en) * 1998-06-25 1999-11-02 Cypress Semiconductor Corp. Method, architecture and circuit for reducing and/or eliminating small signal voltage swing sensitivity
US6122203A (en) * 1998-06-29 2000-09-19 Cypress Semiconductor Corp. Method, architecture and circuit for writing to and reading from a memory during a single cycle
US5986970A (en) * 1998-06-29 1999-11-16 Cypress Semiconductor Corp. Method, architecture and circuit for writing to a memory
US5946255A (en) * 1998-07-31 1999-08-31 Cypress Semiconductor Corp. Wordline synchronized reference voltage generator
DE19843159C1 (de) * 1998-09-21 2000-02-24 Siemens Ag Integrierte Schaltung
GB2376791B (en) 2000-03-31 2004-05-12 Seagate Technology Llc Pulsed write current adapted for use with a field maintenance current in a data storage device
US6738921B2 (en) * 2001-03-20 2004-05-18 International Business Machines Corporation Clock controller for AC self-test timing analysis of logic system
DE10227618B4 (de) * 2002-06-20 2007-02-01 Infineon Technologies Ag Logikschaltung
KR100605603B1 (ko) * 2004-03-30 2006-07-31 주식회사 하이닉스반도체 데이터라인의 스큐를 줄인 반도체 메모리 소자
KR100798794B1 (ko) * 2005-09-29 2008-01-29 주식회사 하이닉스반도체 반도체메모리소자의 데이터 입력장치
JP4919333B2 (ja) 2005-09-29 2012-04-18 株式会社ハイニックスセミコンダクター 半導体メモリ素子のデータ入力装置
WO2010113752A1 (ja) * 2009-03-31 2010-10-07 日本電気株式会社 磁気ランダムアクセスメモリ（ｍｒａｍ）の制御回路、ｍｒａｍ、及びその制御方法

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2590122B2 (ja) * 1987-08-07 1997-03-12 富士通株式会社 半導体メモリ
US5028824A (en) * 1989-05-05 1991-07-02 Harris Corporation Programmable delay circuit
JP3557640B2 (ja) * 1993-12-14 2004-08-25 ソニー株式会社 同期回路
KR970001699B1 (ko) * 1994-03-03 1997-02-13 삼성전자 주식회사 자동프리차아지기능을 가진 동기식 반도체메모리장치
US5559752A (en) * 1995-08-14 1996-09-24 Alliance Semiconductor Corporation Timing control circuit for synchronous static random access memory
US5606269A (en) * 1995-10-26 1997-02-25 International Business Machines Corporation Non-delay based address transition detector (ATD)

Also Published As

Publication number Publication date
JP3394111B2 (ja) 2003-04-07
EP0744749B1 (de) 2001-09-05
EP0744749A3 (de) 1998-11-04
KR100303040B1 (ko) 2001-11-22
KR960042733A (ko) 1996-12-21
US5724287A (en) 1998-03-03
DE69614919T2 (de) 2002-04-11
JPH08321183A (ja) 1996-12-03
EP0744749A2 (de) 1996-11-27

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8328 Change in the person/name/address of the agent

Representative=s name: PUSCHMANN & BORCHERT, 82041 OBERHACHING

8327 Change in the person/name/address of the patent owner

Owner name: OKI SEMICONDUCTOR CO.,LTD., TOKYO, JP