IT1256435B - Dispositivo di memoria a semiconduttore con funzione di autoripristino di bassa potenza elettrica - Google Patents

Dispositivo di memoria a semiconduttore con funzione di autoripristino di bassa potenza elettrica

Info

Publication number
IT1256435B
IT1256435B ITMI922645A ITMI922645A IT1256435B IT 1256435 B IT1256435 B IT 1256435B IT MI922645 A ITMI922645 A IT MI922645A IT MI922645 A ITMI922645 A IT MI922645A IT 1256435 B IT1256435 B IT 1256435B
Authority
IT
Italy
Prior art keywords
signal
reverse bias
response
memory device
semiconductor memory
Prior art date
Application number
ITMI922645A
Other languages
English (en)
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of ITMI922645A0 publication Critical patent/ITMI922645A0/it
Publication of ITMI922645A1 publication Critical patent/ITMI922645A1/it
Application granted granted Critical
Publication of IT1256435B publication Critical patent/IT1256435B/it

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles

Abstract

Si descrive un dispositivo di memoria a semiconduttore avente un temporizzatore di rinfresco o ripristino per generare un impulso di orologio di ripristino, un contatore binario per generare il numero dato di segnale, le cui frequenze sono differenti una dall'altra, in risposta all'impulso di orologio di ripristino, un circuito per generare un segnale di abilitazione di autoripristino in risposta al segnale trasmesso dal contatore binario, un generatore di impulsi di orologio a polarizzazione inversa avente un primo, un secondo e un terzo selettore, di cui il, terzo selettore seleziona uno dei segnali trasmessi dal contatore binario in risposta alle uscite del segnale del primo e secondo selettore, un generatore a polarizzazione inversa avente un oscillatore ed un circuito di rivelazione di tensione di polarizzazione inversa, un circuito di selezione per ricevere il segnale di uscita del circuito di rivelazione di tensione di polarizzazione inversa e trasmettere un segnale all'oscillatore in risposta al segnale di abilitazione autoripristinante e un circuito di controllo di pilotaggio o pilota per ricevere il segnale di uscita dell'oscillatore e l'impulso di orologio di controllo della polarizzazione inversa.
ITMI922645A 1991-11-25 1992-11-19 Dispositivo di memoria a semiconduttore con funzione di autoripristino di bassa potenza elettrica IT1256435B (it)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019910021143A KR940008147B1 (ko) 1991-11-25 1991-11-25 저전력 데이타 리텐션 기능을 가지는 반도체 메모리장치

Publications (3)

Publication Number Publication Date
ITMI922645A0 ITMI922645A0 (it) 1992-11-19
ITMI922645A1 ITMI922645A1 (it) 1994-05-19
IT1256435B true IT1256435B (it) 1995-12-05

Family

ID=19323452

Family Applications (1)

Application Number Title Priority Date Filing Date
ITMI922645A IT1256435B (it) 1991-11-25 1992-11-19 Dispositivo di memoria a semiconduttore con funzione di autoripristino di bassa potenza elettrica

Country Status (8)

Country Link
US (1) US5315557A (it)
JP (1) JPH07109705B2 (it)
KR (1) KR940008147B1 (it)
DE (1) DE4238636C2 (it)
FR (1) FR2684227B1 (it)
GB (1) GB2261755B (it)
IT (1) IT1256435B (it)
TW (1) TW241364B (it)

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JP3001342B2 (ja) * 1993-02-10 2000-01-24 日本電気株式会社 記憶装置
JPH06282985A (ja) * 1993-03-30 1994-10-07 Hitachi Ltd ダイナミック型ｒａｍ
JP3140251B2 (ja) * 1993-04-28 2001-03-05 セイコーインスツルメンツ株式会社 電気的に書換え可能な不揮発性メモリ
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KR950010624B1 (ko) * 1993-07-14 1995-09-20 삼성전자주식회사 반도체 메모리장치의 셀프리프레시 주기조절회로
JP3090833B2 (ja) * 1993-12-28 2000-09-25 株式会社東芝 半導体記憶装置
KR0154167B1 (ko) * 1994-09-12 1998-10-15 김영환 백 바이어스 검출회로
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JPH08227579A (ja) * 1995-02-22 1996-09-03 Mitsubishi Electric Corp 半導体記憶装置
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US5596545A (en) * 1995-12-04 1997-01-21 Ramax, Inc. Semiconductor memory device with internal self-refreshing
JP3752288B2 (ja) * 1995-12-11 2006-03-08 株式会社ルネサステクノロジ 半導体記憶装置
US5644538A (en) * 1996-03-01 1997-07-01 Micron Technology, Inc. Circuit and method for controllng the duration of pulses in a control signal from an electronic system
KR100231602B1 (ko) * 1996-11-08 1999-11-15 김영환 복합 모드형 기판전압 발생회로
US5835401A (en) * 1996-12-05 1998-11-10 Cypress Semiconductor Corporation Dram with hidden refresh
JP3311260B2 (ja) * 1996-12-17 2002-08-05 富士通株式会社 半導体装置及び半導体記憶装置
KR100269296B1 (ko) * 1997-04-22 2000-10-16 윤종용 메모리집적회로의승압전원회로및승압전원의전하량제어방법
KR100264959B1 (ko) * 1997-04-30 2000-10-02 윤종용 반도체 장치의 고전압발생회로
US6115295A (en) * 1997-07-31 2000-09-05 Texas Instruments Incorporated Efficient back bias (VBB) detection and control scheme for low voltage DRAMS
KR100276386B1 (ko) * 1997-12-06 2001-01-15 윤종용 반도체메모리장치의리프레시방법및회로
US6194954B1 (en) 1997-12-31 2001-02-27 Hyundai Electronics Industries Co., Ltd. Voltage controlled generator for semiconductor devices
US6122214A (en) * 1998-03-23 2000-09-19 Matsushita Electric Industrial Co., Ltd. Semiconductor memory
US6411157B1 (en) 2000-06-29 2002-06-25 International Business Machines Corporation Self-refresh on-chip voltage generator
JP2002313080A (ja) * 2001-04-13 2002-10-25 Mitsubishi Electric Corp 半導体記憶装置
JP4416372B2 (ja) 2002-02-25 2010-02-17 富士通マイクロエレクトロニクス株式会社 半導体記憶装置
KR100604657B1 (ko) * 2004-05-06 2006-07-25 주식회사 하이닉스반도체 최적화된 내부전압을 공급할 수 있는 전원공급회로를구비하는 반도체 메모리 장치
JP2006146992A (ja) * 2004-11-16 2006-06-08 Elpida Memory Inc 半導体メモリ装置
KR100666170B1 (ko) * 2005-01-17 2007-01-09 삼성전자주식회사 결함 페이지 버퍼로부터의 데이터 전송이 차단되는와이어드 오어 구조의 불휘발성 반도체 메모리 장치
JP4664126B2 (ja) 2005-06-14 2011-04-06 富士通セミコンダクター株式会社 半導体メモリ
US7477097B2 (en) * 2005-09-29 2009-01-13 Hynix Semiconductor Inc. Internal voltage generating circuit
KR100689863B1 (ko) * 2005-12-22 2007-03-08 삼성전자주식회사 반도체 메모리 장치 및 그에 따른 방법
US7362640B2 (en) * 2005-12-29 2008-04-22 Mosaid Technologies Incorporated Apparatus and method for self-refreshing dynamic random access memory cells
KR100794992B1 (ko) * 2005-12-29 2008-01-16 주식회사 하이닉스반도체 기판 바이어스 전압 발생 장치 및 방법
DE102006062666A1 (de) 2006-12-29 2008-07-03 Samsung Electronics Co., Ltd., Suwon Halbleiterspeicherbauelement und Zugriffs- und Auffrischungsverfahren
KR100834404B1 (ko) * 2007-01-03 2008-06-04 주식회사 하이닉스반도체 리프레쉬신호 생성수단을 포함하는 반도체메모리소자와그의 구동방법
US8072256B2 (en) 2007-09-14 2011-12-06 Mosaid Technologies Incorporated Dynamic random access memory and boosted voltage producer therefor
KR100913958B1 (ko) * 2007-12-27 2009-08-26 주식회사 하이닉스반도체 반도체 소자
US8161356B2 (en) * 2008-03-28 2012-04-17 Intel Corporation Systems, methods, and apparatuses to save memory self-refresh power
KR102035612B1 (ko) * 2012-12-21 2019-10-24 에스케이하이닉스 주식회사 셀프 리프레쉬 제어 장치

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JPS57199335A (en) * 1981-06-02 1982-12-07 Toshiba Corp Generating circuit for substrate bias
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JPS6047295A (ja) * 1983-08-26 1985-03-14 Nec Corp 擬似スタティックメモリ
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JPH0787034B2 (ja) * 1984-05-07 1995-09-20 株式会社日立製作所 半導体集積回路装置
JPS6159688A (ja) * 1984-08-31 1986-03-27 Hitachi Ltd 半導体集積回路装置
JPS63155494A (ja) * 1986-12-19 1988-06-28 Fujitsu Ltd 擬似スタテイツクメモリ装置
JPS63247997A (ja) * 1987-04-01 1988-10-14 Mitsubishi Electric Corp 半導体記憶装置
JPS63289854A (ja) * 1987-05-21 1988-11-28 Matsushita Electric Ind Co Ltd 基板電位発生回路
JPH07107793B2 (ja) * 1987-11-10 1995-11-15 株式会社東芝 仮想型スタティック半導体記憶装置及びこの記憶装置を用いたシステム
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Also Published As

Publication number Publication date
US5315557A (en) 1994-05-24
ITMI922645A0 (it) 1992-11-19
TW241364B (it) 1995-02-21
JPH05217368A (ja) 1993-08-27
GB2261755B (en) 1995-08-30
GB2261755A (en) 1993-05-26
ITMI922645A1 (it) 1994-05-19
KR930010985A (ko) 1993-06-23
DE4238636C2 (de) 1995-07-20
DE4238636A1 (it) 1993-05-27
KR940008147B1 (ko) 1994-09-03
FR2684227B1 (fr) 1994-07-29
JPH07109705B2 (ja) 1995-11-22
GB9224459D0 (en) 1993-01-13
FR2684227A1 (fr) 1993-05-28

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Effective date: 19971126