EP1550154B1 - Feldeffekttransistor mit lokaler source-/drainisolation sowie zugehöriges herstellungsverfahren - Google Patents

Feldeffekttransistor mit lokaler source-/drainisolation sowie zugehöriges herstellungsverfahren Download PDF

Info

Publication number
EP1550154B1
EP1550154B1 EP03750362.0A EP03750362A EP1550154B1 EP 1550154 B1 EP1550154 B1 EP 1550154B1 EP 03750362 A EP03750362 A EP 03750362A EP 1550154 B1 EP1550154 B1 EP 1550154B1
Authority
EP
European Patent Office
Prior art keywords
layer
source
drain
depressions
gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
EP03750362.0A
Other languages
German (de)
English (en)
French (fr)
Other versions
EP1550154A1 (de
Inventor
Jürgen Holz
Klaus SCHRÜFER
Helmut Tews
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Priority to EP13177706.2A priority Critical patent/EP2657961B1/de
Publication of EP1550154A1 publication Critical patent/EP1550154A1/de
Application granted granted Critical
Publication of EP1550154B1 publication Critical patent/EP1550154B1/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66636—Lateral single gate silicon transistors with source or drain recessed by etching or first recessed by etching and then refilled
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604—Chemical etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41775—Source or drain electrodes for field effect devices characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
    • H01L29/41783—Raised source or drain electrodes self aligned with the gate

Definitions

  • the present invention relates to a field effect transistor with local source / drain isolation and a related manufacturing method, and more particularly to a field effect transistor having structures in the sub100nm range which can be used in so-called mixed signal circuits.
  • junction capacitors in particular causing undesirable parasitic effects in the field effect transistor.
  • Such junction capacitances are caused, in particular, at the pn junctions of the source and drain regions in the semiconductor substrate, since relatively high parasitic capacitances arise at this point due to space charge or depletion zones.
  • SOI substrates Silicon On Insulator
  • SOI substrates Silicon On Insulator
  • a disadvantage of such semiconductor circuits in an SOI substrate are the significantly increased costs and the associated disadvantages in so-called mixed-signal circuits. While a fully depleted channel region is often even desirable in short channel field effect transistors, field effect transistors with long channel regions require connectivity to avoid charging these regions and to achieve the highest possible linearity of the characteristics.
  • a connection possibility of the channel area is also for the so-called matching behavior the transistors of importance, for example, to allow the same behavior of two identical transistors in a semiconductor circuit.
  • the use of SOI substrates provides only insufficient results.
  • SOI substrates have only poor thermal binding of the active regions.
  • a field effect transistor with local source / drain isolation and a related manufacturing method wherein a source well and a drain well are formed spaced apart in a semiconductor substrate.
  • a depression insulating layer is first formed and subsequently an electrically conductive filling layer is formed for the realization of source and drain regions and for filling the source and drain recesses on the surface of the depression insulation layer.
  • a gate dielectric is formed on the substrate surface between the source and drain recesses and a gate layer is formed on the surface of the gate dielectric.
  • the pamphlets US-A-5 908 313 and US 2002/142552 A1 also show only conventional field effect transistors, wherein the channel connection regions of the respective source / drain regions are formed by ion implantation.
  • the document also shows WO 02/43109 A2 a depression which is wider in its upper region than in its lower region due to the etching processes used.
  • a diffusion barrier layer is provided, which, however, allows tunneling of electrical charge carriers.
  • the invention is therefore based on the object to provide a field effect transistor with local source / drain insulation and an associated manufacturing method, wherein junction capacitances are particularly easy to reduce and mixed signal circuits can be particularly easily implemented.
  • the source and drain recesses in the upper region may have a first depression having a predetermined depth and a second recess in the first recess and in the semiconductor substrate, wherein the recess sidewall insulating layer also extends into a region below the gate dielectric or below the channel region without touching the gate dielectric.
  • the desired shallow port regions for the channel regions can be realized very precisely and eliminates the commonly used very shallow implants, the problems of diffusion promoting effects of defects and very short RTP (Rapid Thermal Process) annealing steps with their poor reproducibility or a pre -Amorphization and defect implantations.
  • the commonly occurring high leakage currents and junction capacitances in this region can be substantially reduced. It can also be achieved by isolating short channel transistors from the substrate and by providing long channel transistors on the same wafer with a connection possibility to the substrate. Thus, the optimal devices are generated for both digital circuits and mixed-signal circuits. This is particularly advantageous for a SoC (system on chip) integration.
  • SoC system on chip
  • the pit sidewall isolation layer does not contact the gate dielectric, further reduced junction capacitances and shallow well extensions are obtained for the channel region.
  • the electrically conductive filling layer may have a seed layer, whereby very narrow and deep source and drain wells or holes can be filled sufficiently well.
  • FIG. 1 shows a simplified sectional view of a field effect transistor with local source / drain insulation according to a first example, wherein in a semiconductor substrate 1, which preferably consists of a silicon semiconductor material, active regions by means of a STI (Shallow Trench Isolation) method to form shallow trench insulations 2 are formed , These shallow trench isolations 2 may be formed, for example, in strip form in the semiconductor substrate 1, resulting in intermediate strip-shaped active regions.
  • a semiconductor substrate 1 which preferably consists of a silicon semiconductor material
  • the field-effect transistor has a gate stack G formed on the surface of the semiconductor substrate 1, which essentially has a gate dielectric, such as a gate dielectric. a gate oxide layer 3 and an actual gate or control layer 4 has.
  • a source depression SV and a drain depression DV are formed spaced apart from one another in the semiconductor substrate 1, wherein a region lying below the gate dielectric 3 represents a channel region.
  • Recesses, holes, trenches, etc. with a corresponding depth in the semiconductor substrate 1 can be formed as depressions.
  • a recess isolation layer VI is formed, which forms a local source and drain insulation to the semiconductor substrate 1 and thus substantially reduces a junction capacitance of a respective source and drain region.
  • the local source and drain insulations narrow and very accurately formed in the recess.
  • the field effect transistor has an electrically conductive filling layer F for realizing the actual source and drain regions S and D, wherein the filling layer F is formed on the surface of the depression insulating layer and fills the source and drain recesses SV and DV.
  • the source and drain recesses may have a depth of approximately 50 to 300 nm.
  • the electrical properties of the field effect transistor can be set very precisely.
  • gate dielectric silicon dioxide is used as the gate dielectric, although other dielectric layers can also be used.
  • the gate layer 4 used is preferably amorphous silicon or polysilicon, although metal gates or other materials are also used can.
  • other layer structures can also be realized for the gate stack G, as are known, for example, from the field of nonvolatile memory elements (flash EPROM, E 2 PROM, etc.).
  • FIG. 2 shows a simplified sectional view of a field effect transistor with local source / drain insulation according to a second example, wherein like reference numerals designate the same or corresponding elements or layers as in FIG. 1 and a repeated description is omitted below.
  • the recessed insulation layer VI not only has a recessed bottom insulating layer formed in the bottom region of the source and drain recesses SV and DV, but also has a recessed sidewall insulating layer which does not contact the gate dielectric 3 and thus has a defined channel connecting region KA for connecting a well under the gate dielectric 3 lying channel region allows. In this way one obtains channel connection areas KA, which have very low leakage currents and further reduced junction capacities.
  • the commonly used methods for the formation of such flat terminal regions by means of shallow implantations, pre-amorphization or defect implantation as well as short RTP annealing steps (rapid thermal process) can thus be avoided. Due to the very accurately adjustable dimensions of the source and drain wells, the electrical properties of the field effect transistors formed therewith can also be determined very precisely, as a result of which semiconductor components having significantly reduced junction capacitances are obtained.
  • the extensions or connection regions KA can be realized by means of outdiffusion, resulting in dopant profiles with maximum gradient.
  • FIGS. 3A to 3I show simplified sectional views to illustrate essential process steps in the manufacture of a field effect transistor with local source / drain insulation, again like reference numerals the same or similar layers or elements as in Figures 1 and 2 denote and a repeated description is omitted below.
  • a gate stack with a gate layer 4 and a gate dielectric 3 is formed on a semiconductor substrate 1.
  • a gate process commonly referred to as a gate process, a pad oxide (not shown) is first deposited on the surface of the semiconductor substrate 1, and then a pad nitride (not shown) is formed on the surface of the pad oxide.
  • a shallow trench isolation 2 is formed in the semiconductor substrate 1 by means of a conventional STI method (shallow trench isolation) and then at least the pad nitride layer is removed again.
  • one or more implants for the formation of well and / or channel doping regions in the semiconductor substrate 1, wherein depending on the semiconductor circuit to be formed and a multi-well structure can be realized.
  • the gate dielectric 3 preferably a thermal oxidation of the substrate surface SO, whereby, for example, a high-quality gate oxide is formed.
  • the gate layer 4 for example, a deposition of polysilicon with a thickness of, for example, 100 nm and at the surface to form a hard mask layer 5, for example, a TEOS insulating layer is deposited with a thickness of about 50 nm.
  • a photolithographic method is then first applied to the hard mask layer 5, wherein subsequently using the patterned hard mask layer 5, preferably by means of an anisotropic etching process (RIE, Reactive Ionetching) the gate layer 4 is structured.
  • RIE anisotropic etching process
  • another thermal oxidation or oxide deposition may be performed to form a gate sidewall insulating layer 6 on the sidewalls of the gate layer 4, thereby providing an approximately 6 nm thick protective layer.
  • the gate sidewall insulating layer 6 serves as an etch stop layer for subsequent etching steps and as a lateral protective layer for the relatively sensitive gate dielectric 3.
  • FIG. 3A illustrated sectional view, wherein also alternative methods for forming and patterning a gate stack with a gate layer 4 and a gate dielectric 3 on a semiconductor substrate 1 can be performed.
  • source and drain recesses are formed on the gate stack.
  • RIE Reactive Ion Etching
  • the depth of this first depression V1 serves as an optimization parameter for the production of the extension or of the channel connection region.
  • a first thin semiconductor protective layer (not shown) may be formed at least in the area of the channel connecting region KA and preferably over the whole area in order to protect the semiconductor surface (silicon) from subsequent nitride deposition, which is generally problematic for silicon semiconductor materials. Accordingly, this first semiconductor protective layer preferably consists of a silicon oxide layer.
  • Spacer 7 formed on the gate stack wherein the gate stack is composed essentially of the gate dielectric 3, the gate layer 4, the hard mask layer 5 and the (possibly present) gate sidewall insulating layer 6.
  • the spacers 7 are formed by conformal, ie uniformly thick, deposition of silicon nitride on the available surface and a subsequent anisotropic etch back, wherein for example an LPCVD process (low pressure chemical vapor deposition) is used for the deposition.
  • the thickness of the spacer 7 is an optimization parameter for the channel connection region KA, wherein preferably spacer thicknesses of about 10 to 30 nm give particularly favorable connection properties.
  • the first recesses V1 are formed using the gate stack and the shallow trench isolation 2 as a mask, thereby obtaining substantially self-adjusting processes for a first recess V1.
  • an insulation mask layer 8 takes place to form a depression insulation layer. Nitration of the exposed semiconductor material or silicon with NH 3 takes place within a temperature range of 600 to 900 ° C. Alternatively, however, it is also possible to carry out a nitride deposition to realize the insulation mask layer 8.
  • the desired silicon nitride thickness or thickness of the insulating mask layer 8 is, for example, about 1 to 5 nm.
  • an additional thin oxide buffer layer (not shown) can be produced underneath the deposited nitride to protect the semiconductor material.
  • a recessed bottom insulating layer 9 is formed respectively in the exposed bottom portions of the source and drain recesses SV and DV, for example, thermal oxidation is performed on the exposed semiconductor material.
  • a silicon oxide layer having a thickness of 20 to 40 nm is formed in the bottom region of the source and drain recesses.
  • SELOX process selective oxide deposition process
  • the depths for the source and drain recesses are to be selected depending on a respectively selected manufacturing method for the recessed bottom insulating layer 9.
  • SELOX process reference is made in particular to the reference N. Elbel, et al. "A new STI process based on selective oxide deposition" at the Symposium on VLSI Technology 1998 directed.
  • the insulating mask layer 8 not only allows the horizontal and vertical surfaces to be oxidized separately, but also reduces the mechanical stress in the channel region.
  • the remaining insulating mask layer 8 is also removed on the sidewalls of the source and drain recesses SV and DV, and recessed sidewall insulating layers 8A are formed in the exposed sidewall regions of the recesses. More specifically, to remove the thin nitride layer 8 on the sidewalls, a short-time etching step and then a thermal oxidation at a temperature of about 800 ° C. or wet oxidation are performed to form an approximately 5 to 20 nm-thick depression sidewall insulation layer 8A.
  • the recessed bottom insulating layer 9 and the recessed sidewall insulating layer 8A are formed as silicon dioxide layers.
  • a filling of the at least partially isolated source and drain recesses SV and DV is now performed with a filling layer, preferably first a seed layer or seed layer 10 is formed for the realization of a subsequent selective deposition of polysilicon.
  • a deposition of a thin doped or undoped amorphous or polycrystalline semiconductor layer takes place, wherein preferably silicon or SiGe is used, but alternative materials can also be used as the seed layer 10.
  • a seed protective layer 11 a short oxidation or nitration of the seed layer 10 takes place and finally a formation of a seed mask layer 12, wherein preferably a resist deposition is carried out over the whole area.
  • planarization of the seed mask layer 12 by means of, for example, a chemical mechanical polishing (CMP) under Use of the germ-protective layer 11 as a stop layer gives the in FIG. 3E illustrated sectional view.
  • CMP chemical mechanical polishing
  • the seed mask layer 12 is formed back into the source and drain wells SV and DV, wherein, for example, a resist etching is performed after a predetermined time.
  • a resist etching is performed after a predetermined time.
  • Such regression can be performed relatively accurately, since the height of the gate stack is usually known very accurately.
  • a partial removal of the seed protection layer 11 takes place, ie the oxide and / or nitride layer is removed except for the area covered by the seed mask layer 12.
  • the recessed seed mask layer 12 is removed, wherein preferably a resist stripe is performed.
  • the seed layer 10 is partially removed, for example, by performing a wet-chemical silicon etching process. Finally, the remaining germ-protective layer 11 is completely removed. To remove the seed protective layer 11, a nitride and / or an oxide etching process is again carried out.
  • the amorphous or polycrystalline seed layer 10 remaining in the source and drain recesses SV and DV now permits a selective deposition or growth of semiconductor material on this layer, the remaining areas covered by oxide remaining free of this growth layer 13.
  • the spacers 7 on the gate stack and the spacers 7A on the shallow trench isolation 2 are removed to expose the channel connection regions KA.
  • this is done by means of wet-chemical nitride etching.
  • a very thin interface layer may be formed, for example, of silicon dioxide or silicon nitride.
  • the growth layer 13 is formed on the seed layer 10 into a region of the substrate surface SO, wherein in particular a (to silicon dioxide) selective deposition of doped or undoped amorphous or polycrystalline semiconductor material up to a thickness of about 50 to 400 nm takes place.
  • a (to silicon dioxide) selective deposition of doped or undoped amorphous or polycrystalline semiconductor material up to a thickness of about 50 to 400 nm takes place.
  • the different process conditions for the deposition of amorphous or polycrystalline silicon on different documents are exploited. This creates a so-called "raised source / drain" structure.
  • implantation spacers 14 are formed on the sidewalls of the gate stack and the gate sidewall insulation layer 6, respectively. These implantation spacers 14 preferably again consist of a silicon nitride layer. Thereafter, the hardmask layer 5 may be removed using oxide etching, wherein the trench isolations 2 and the TEOS hardmask layer are reformed, but the gate sidewall insulating layers 6 are protected by the implantation spacers 14. Finally, an implantation I of dopants for doping the exposed gate layer 4 and the growth layer 13 and optionally the seed layer 10. This implantation is carried out as usual by means of resist mask technique, wherein for activating the dopants, a further thermal annealing step can be performed.
  • the connections of source and drain now take place via an outdiffusion from these heavily doped polysilicon layers, wherein, because of the high diffusion constant along the grain boundaries, the doped polycrystalline or amorphous semiconductor material acts like an infinite dopant source.
  • the resulting benefits are very steep diffusion flanks and high dopants. Since the implantation I of the source and drain regions S and D takes place directly into the amorphous or polycrystalline semiconductor material, the under-diffusion of the channel connection regions KA is not determined by implantation defects, since these recombine at the polysilicon grain boundaries. Due to this fact, it is possible to use larger temperature budgets to achieve better process control and higher activation of the dopants.
  • insitu-doped semiconductor material can also be deposited.
  • the wafer is covered with a masking layer and then the area for e.g. NFET transistors open. Only in this area is doped semiconductor material then deposited. For PFET transistors, the process is repeated accordingly.
  • FIG. 4 shows a simplified partial sectional view for illustrating the channel connecting regions when using undoped or doped semiconductor material according to the third embodiment described above.
  • FIGS. 5A and 5B show simplified sectional views of essential process steps in the manufacture of a field effect transistor with local source / drain insulation according to an embodiment, wherein like reference numerals the same or corresponding elements or layers as in FIGS. 1 to 4 denote and a repeated description is omitted below.
  • field effect transistors with "fully depleted” channel regions, ie completely depleted channel areas described.
  • Such field-effect transistors are particularly desirable in the realization of fast short-channel transistors, as this can realize significantly increased speeds and clock frequencies.
  • FIGS. 5A and 5B correspond to the method steps according to 3D and 3E, wherein for the realization of the completely depleted channel regions a recessed side wall insulating layer 8A is formed, which extends far into a region below the gate dielectric 3. More specifically, for example, by oxidizing the exposed sidewalls of the source and drain recesses SV and DV, a large thickness of the cavity sidewall insulating film 8A is formed, which is in a range of 20 to 30 nm. Due to this high thickness results in a constriction of the so-called body or channel region, whereby one obtains a completely depleted structure in the channel region.
  • the invention has been described above with reference to silicon semiconductor circuits. However, it is not limited thereto and likewise includes semiconductor circuits with alternative semiconductor materials. In the same way, alternative materials can be used in particular for the gate layer and the filling layer.
EP03750362.0A 2002-10-07 2003-09-19 Feldeffekttransistor mit lokaler source-/drainisolation sowie zugehöriges herstellungsverfahren Expired - Fee Related EP1550154B1 (de)

Priority Applications (1)

Application Number Priority Date Filing Date Title
EP13177706.2A EP2657961B1 (de) 2002-10-07 2003-09-19 Verfahren zur Herstellung eines Feldeffekttransistors mit lokaler Source-/Drainisolation

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE10246718 2002-10-07
DE10246718A DE10246718A1 (de) 2002-10-07 2002-10-07 Feldeffekttransistor mit lokaler Source-/Drainisolation sowie zugehöriges Herstellungsverfahren
PCT/DE2003/003130 WO2004034458A1 (de) 2002-10-07 2003-09-19 Feldeffekttransistor mit lokaler source-/drainisolation sowie zugehöriges herstellungsverfahren

Related Child Applications (2)

Application Number Title Priority Date Filing Date
EP13177706.2A Division EP2657961B1 (de) 2002-10-07 2003-09-19 Verfahren zur Herstellung eines Feldeffekttransistors mit lokaler Source-/Drainisolation
EP13177706.2A Division-Into EP2657961B1 (de) 2002-10-07 2003-09-19 Verfahren zur Herstellung eines Feldeffekttransistors mit lokaler Source-/Drainisolation

Publications (2)

Publication Number Publication Date
EP1550154A1 EP1550154A1 (de) 2005-07-06
EP1550154B1 true EP1550154B1 (de) 2015-02-18

Family

ID=32038290

Family Applications (2)

Application Number Title Priority Date Filing Date
EP03750362.0A Expired - Fee Related EP1550154B1 (de) 2002-10-07 2003-09-19 Feldeffekttransistor mit lokaler source-/drainisolation sowie zugehöriges herstellungsverfahren
EP13177706.2A Expired - Fee Related EP2657961B1 (de) 2002-10-07 2003-09-19 Verfahren zur Herstellung eines Feldeffekttransistors mit lokaler Source-/Drainisolation

Family Applications After (1)

Application Number Title Priority Date Filing Date
EP13177706.2A Expired - Fee Related EP2657961B1 (de) 2002-10-07 2003-09-19 Verfahren zur Herstellung eines Feldeffekttransistors mit lokaler Source-/Drainisolation

Country Status (8)

Country Link
US (4) US7528453B2 (ko)
EP (2) EP1550154B1 (ko)
JP (1) JP2006502573A (ko)
KR (1) KR100657098B1 (ko)
CN (1) CN100474535C (ko)
DE (1) DE10246718A1 (ko)
TW (1) TWI227563B (ko)
WO (1) WO2004034458A1 (ko)

Families Citing this family (59)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10246718A1 (de) * 2002-10-07 2004-04-22 Infineon Technologies Ag Feldeffekttransistor mit lokaler Source-/Drainisolation sowie zugehöriges Herstellungsverfahren
US7135391B2 (en) * 2004-05-21 2006-11-14 International Business Machines Corporation Polycrystalline SiGe junctions for advanced devices
US7413957B2 (en) * 2004-06-24 2008-08-19 Applied Materials, Inc. Methods for forming a transistor
US7078722B2 (en) 2004-09-20 2006-07-18 International Business Machines Corporation NFET and PFET devices and methods of fabricating same
US7335959B2 (en) * 2005-01-06 2008-02-26 Intel Corporation Device with stepped source/drain region profile
US7358025B2 (en) * 2005-03-11 2008-04-15 Shin-Etsu Chemical Co., Ltd. Photoresist undercoat-forming material and patterning process
JP4664760B2 (ja) * 2005-07-12 2011-04-06 株式会社東芝 半導体装置およびその製造方法
US7776744B2 (en) 2005-09-01 2010-08-17 Micron Technology, Inc. Pitch multiplication spacers and methods of forming the same
JP2007220808A (ja) * 2006-02-15 2007-08-30 Toshiba Corp 半導体装置及びその製造方法
TWI343625B (en) * 2006-03-09 2011-06-11 Nanya Technology Corp A semiconductor device and manufacturing method of the same
US7572691B2 (en) * 2006-05-16 2009-08-11 Macronix International Co., Ltd Non-volatile memory and method of fabricating the same
US7541239B2 (en) 2006-06-30 2009-06-02 Intel Corporation Selective spacer formation on transistors of different classes on the same device
US7855414B2 (en) * 2006-07-28 2010-12-21 Broadcom Corporation Semiconductor device with increased breakdown voltage
US20080246080A1 (en) * 2006-07-28 2008-10-09 Broadcom Corporation Shallow trench isolation (STI) based laterally diffused metal oxide semiconductor (LDMOS)
KR100843880B1 (ko) * 2007-03-20 2008-07-03 주식회사 하이닉스반도체 반도체 소자 및 그의 형성 방법
US9136329B2 (en) * 2007-04-19 2015-09-15 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor structure with dielectric-sealed doped region
US8415749B2 (en) * 2007-04-19 2013-04-09 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor structure with dielectric-sealed doped region
US7923373B2 (en) 2007-06-04 2011-04-12 Micron Technology, Inc. Pitch multiplication using self-assembling materials
US7928474B2 (en) * 2007-08-15 2011-04-19 Taiwan Semiconductor Manufacturing Company, Ltd., Forming embedded dielectric layers adjacent to sidewalls of shallow trench isolation regions
US7781838B2 (en) * 2008-04-21 2010-08-24 Qimonda Ag Integrated circuit including a body transistor and method
US7880210B2 (en) * 2008-05-23 2011-02-01 Qimonda Ag Integrated circuit including an insulating structure below a source/drain region and method
JP2010171144A (ja) * 2009-01-21 2010-08-05 Toshiba Corp 半導体装置
US8203188B2 (en) * 2009-05-22 2012-06-19 Broadcom Corporation Split gate oxides for a laterally diffused metal oxide semiconductor (LDMOS)
KR101097469B1 (ko) * 2009-07-31 2011-12-23 주식회사 하이닉스반도체 반도체 장치 및 그 제조방법
WO2011042965A1 (ja) * 2009-10-07 2011-04-14 富士通セミコンダクター株式会社 半導体装置および半導体論理回路装置
US8274114B2 (en) * 2010-01-14 2012-09-25 Broadcom Corporation Semiconductor device having a modified shallow trench isolation (STI) region and a modified well region
KR101120174B1 (ko) * 2010-02-10 2012-02-27 주식회사 하이닉스반도체 반도체 소자의 제조 방법
US8283722B2 (en) 2010-06-14 2012-10-09 Broadcom Corporation Semiconductor device having an enhanced well region
US8492234B2 (en) * 2010-06-29 2013-07-23 International Business Machines Corporation Field effect transistor device
CN102437183B (zh) * 2010-09-29 2015-02-25 中国科学院微电子研究所 半导体器件及其制造方法
US9123807B2 (en) 2010-12-28 2015-09-01 Broadcom Corporation Reduction of parasitic capacitance in a semiconductor device
JP5720244B2 (ja) * 2010-12-28 2015-05-20 富士通セミコンダクター株式会社 半導体基板の製造方法及び半導体装置の製造方法
US8361847B2 (en) * 2011-01-19 2013-01-29 International Business Machines Corporation Stressed channel FET with source/drain buffers
CN102956493A (zh) * 2011-08-24 2013-03-06 中芯国际集成电路制造(上海)有限公司 晶体管及其形成方法
JP5742631B2 (ja) 2011-09-28 2015-07-01 富士通セミコンダクター株式会社 半導体装置の製造方法
CN103137490B (zh) * 2011-12-05 2016-02-03 中芯国际集成电路制造(北京)有限公司 半导体器件及其制造方法
CN103426753B (zh) * 2012-05-14 2016-06-22 中芯国际集成电路制造(上海)有限公司 源漏区的制备方法和mos器件
CN103779224A (zh) * 2012-10-23 2014-05-07 中国科学院微电子研究所 Mosfet的制造方法
CN104701164A (zh) * 2013-12-04 2015-06-10 中芯国际集成电路制造(上海)有限公司 半导体器件和半导体器件的制作方法
US9484461B2 (en) * 2014-09-29 2016-11-01 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit structure with substrate isolation and un-doped channel
US9653570B2 (en) * 2015-02-12 2017-05-16 International Business Machines Corporation Junction interlayer dielectric for reducing leakage current in semiconductor devices
CN106328707A (zh) * 2015-07-06 2017-01-11 中芯国际集成电路制造(上海)有限公司 晶体管及其制作方法
US9536945B1 (en) 2015-07-30 2017-01-03 International Business Machines Corporation MOSFET with ultra low drain leakage
US10141426B2 (en) * 2016-02-08 2018-11-27 International Business Macahines Corporation Vertical transistor device
US10074563B2 (en) 2016-07-29 2018-09-11 Taiwan Semiconductor Manufacturing Co., Ltd. Structure and formation method of interconnection structure of semiconductor device
CN107958935B (zh) * 2016-10-18 2020-11-27 中芯国际集成电路制造(上海)有限公司 鳍式场效应管及其形成方法
KR102356492B1 (ko) 2017-03-10 2022-01-28 에스케이하이닉스 주식회사 트랜지스터를 포함하는 전자 장치 및 그 제조 방법
US10629679B2 (en) * 2017-08-31 2020-04-21 Taiwan Semiconductor Manufacturing Co., Ltd. Method of manufacturing a semiconductor device and a semiconductor device
US10431695B2 (en) 2017-12-20 2019-10-01 Micron Technology, Inc. Transistors comprising at lease one of GaP, GaN, and GaAs
US10825816B2 (en) 2017-12-28 2020-11-03 Micron Technology, Inc. Recessed access devices and DRAM constructions
US10734527B2 (en) * 2018-02-06 2020-08-04 Micron Technology, Inc. Transistors comprising a pair of source/drain regions having a channel there-between
US11869972B2 (en) * 2018-11-26 2024-01-09 Etron Technology, Inc. Reduced-form-factor transistor with self-aligned terminals and adjustable on/off-currents and manufacture method thereof
US11264499B2 (en) * 2019-09-16 2022-03-01 Globalfoundries U.S. Inc. Transistor devices with source/drain regions comprising an interface layer that comprises a non-semiconductor material
CN111341663A (zh) * 2020-03-12 2020-06-26 上海华虹宏力半导体制造有限公司 射频器件的形成方法
US11978774B2 (en) * 2020-10-05 2024-05-07 Sandisk Technologies Llc High voltage field effect transistor with vertical current paths and method of making the same
WO2022076043A1 (en) * 2020-10-05 2022-04-14 Sandisk Technologies Llc High voltage field effect transistor with vertical current paths and method of making the same
US11450768B2 (en) 2020-10-05 2022-09-20 Sandisk Technologies Llc High voltage field effect transistor with vertical current paths and method of making the same
CN113327848B (zh) * 2021-05-28 2024-03-08 上海华力微电子有限公司 闪存器件及其制造方法
CN115602648A (zh) * 2021-07-09 2023-01-13 长鑫存储技术有限公司（Cn） 半导体结构及其制作方法

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6399973B1 (en) * 2000-12-29 2002-06-04 Intel Corporation Technique to produce isolated junctions by forming an insulation layer

Family Cites Families (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US620912A (en) * 1899-03-14 Rail-fastener
JPH067596B2 (ja) * 1984-02-01 1994-01-26 株式会社日立製作所 半導体装置の製造方法
JPS62143472A (ja) 1985-12-18 1987-06-26 Hitachi Ltd 半導体装置
US5043778A (en) 1986-08-11 1991-08-27 Texas Instruments Incorporated Oxide-isolated source/drain transistor
JPH01268061A (ja) 1988-04-20 1989-10-25 Hitachi Ltd 半導体装置
JPH02128430A (ja) 1988-11-08 1990-05-16 Oki Electric Ind Co Ltd Ｍｏｓトランジスタの製造方法
KR0135147B1 (ko) 1994-07-21 1998-04-22 문정환 트랜지스터 제조방법
US5710450A (en) * 1994-12-23 1998-01-20 Intel Corporation Transistor with ultra shallow tip and method of fabrication
TW328650B (en) 1996-08-27 1998-03-21 United Microelectronics Corp The MOS device and its manufacturing method
US5908313A (en) * 1996-12-31 1999-06-01 Intel Corporation Method of forming a transistor
JPH10326837A (ja) * 1997-03-25 1998-12-08 Toshiba Corp 半導体集積回路装置の製造方法、半導体集積回路装置、半導体装置、及び、半導体装置の製造方法
JPH118379A (ja) 1997-06-16 1999-01-12 Toshiba Corp 半導体装置及びその製造方法
DE19749378B4 (de) 1997-11-07 2006-10-26 Infineon Technologies Ag MOS-Transistor und Verfahren zu dessen Herstellung
DE19812643C1 (de) 1998-03-23 1999-07-08 Siemens Ag Schaltungsstruktur mit einem MOS-Transistor und Verfahren zu deren Herstellung
KR100261170B1 (ko) * 1998-05-06 2000-07-01 김영환 반도체소자 및 그 제조방법
US6207515B1 (en) * 1998-05-27 2001-03-27 Taiwan Semiconductor Manufacturing Company Method of fabricating buried source to shrink chip size in memory array
US6071783A (en) 1998-08-13 2000-06-06 Taiwan Semiconductor Manufacturing Company Pseudo silicon on insulator MOSFET device
US6541343B1 (en) 1999-12-30 2003-04-01 Intel Corporation Methods of making field effect transistor structure with partially isolated source/drain junctions
US7391087B2 (en) * 1999-12-30 2008-06-24 Intel Corporation MOS transistor structure and method of fabrication
US6403482B1 (en) 2000-06-28 2002-06-11 International Business Machines Corporation Self-aligned junction isolation
JP2002016246A (ja) 2000-06-28 2002-01-18 Sharp Corp Ｍｏｓ型半導体トランジスタの製造方法
WO2002043109A2 (de) 2000-11-21 2002-05-30 Infineon Technologies Ag Verfahren zum herstellen eines planaren feldeffekttransistors und planarer feldeffekttransistor
US6649481B2 (en) 2001-03-30 2003-11-18 Silicon-Based Technology Corp. Methods of fabricating a semiconductor device structure for manufacturing high-density and high-performance integrated-circuits
US6649460B2 (en) * 2001-10-25 2003-11-18 International Business Machines Corporation Fabricating a substantially self-aligned MOSFET
US6621131B2 (en) * 2001-11-01 2003-09-16 Intel Corporation Semiconductor transistor having a stressed channel
TW506064B (en) * 2001-12-10 2002-10-11 Macronix Int Co Ltd Structure of semiconductor device and its manufacturing method
US6812103B2 (en) * 2002-06-20 2004-11-02 Micron Technology, Inc. Methods of fabricating a dielectric plug in MOSFETS to suppress short-channel effects
US6794313B1 (en) * 2002-09-20 2004-09-21 Taiwan Semiconductor Manufacturing Company, Ltd. Oxidation process to improve polysilicon sidewall roughness
DE10246718A1 (de) * 2002-10-07 2004-04-22 Infineon Technologies Ag Feldeffekttransistor mit lokaler Source-/Drainisolation sowie zugehöriges Herstellungsverfahren

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6399973B1 (en) * 2000-12-29 2002-06-04 Intel Corporation Technique to produce isolated junctions by forming an insulation layer

Also Published As

Publication number Publication date
WO2004034458A1 (de) 2004-04-22
EP2657961A1 (de) 2013-10-30
TW200408129A (en) 2004-05-16
US7824993B2 (en) 2010-11-02
US7528453B2 (en) 2009-05-05
US20050280052A1 (en) 2005-12-22
EP2657961B1 (de) 2016-03-23
DE10246718A1 (de) 2004-04-22
KR100657098B1 (ko) 2006-12-13
US20110012208A1 (en) 2011-01-20
TWI227563B (en) 2005-02-01
US20090227083A1 (en) 2009-09-10
JP2006502573A (ja) 2006-01-19
US20160118477A1 (en) 2016-04-28
CN100474535C (zh) 2009-04-01
US9240462B2 (en) 2016-01-19
KR20050048675A (ko) 2005-05-24
EP1550154A1 (de) 2005-07-06
CN1689149A (zh) 2005-10-26

Similar Documents

Publication Publication Date Title
EP1550154B1 (de) Feldeffekttransistor mit lokaler source-/drainisolation sowie zugehöriges herstellungsverfahren
DE102012206478B4 (de) Extrem-dünner-Halbleiter-auf-Isolator(ETSOI)-FET mit einem Rück-Gate und verringerter Parasitärkapazität sowie Verfahren zu dessen Herstellung
DE112012004824B4 (de) Verfahren und Struktur zum Bilden von ETSOI-Kondensatoren, -Dioden, -Widerständen und -Back-Gate-Kontakten
DE112012005166B4 (de) Verfahren und Struktur zum Bilden von On-Chip-Kondensatoren hoher Qualität mit ETSOI-Transistoren
DE112005000704B4 (de) Nicht-planarer Bulk-Transistor mit verspanntem Kanal mit erhöhter Mobilität und Verfahren zur Herstellung
DE112012000310B4 (de) SILICIUM-NANORÖHREN-MOSFET und HERSTELLUNGSVERFAHREN
DE4212829C2 (de) Verfahren zur Herstellung von Metall-Oxid-Halbleiter-Feldeffekttransistoren
DE60036410T2 (de) Methoden zur herstellung einer feldeffekttransistor-struktur mit teilweise isolierten source/drain-übergängen
DE10131276B4 (de) Feldeffekttransistor und Verfahren zu seiner Herstellung
DE102006062862B4 (de) Verfahren zum Herstellen von Feldeffekttransistoren mit vertikal ausgerichteten Gate-Elektroden
DE112004001922B4 (de) Flash-Architektur mit abgesenktem Kanal für geringere Kurzkanaleffekte
DE102006016550B4 (de) Feldeffekttransistoren mit vertikal ausgerichteten Gate-Elektroden und Verfahren zum Herstellen derselben
EP1770784A1 (de) Halbleiteranordnung und Verfahren zur Herstellung einer Halbleiteranordnung
DE102011088584B4 (de) Halbleiterbauelement und Verfahren zu seiner Herstellung
DE102013103470A1 (de) Struktur und Verfahren für einen Feldeffekttransistor
DE10131237B4 (de) Feldeffekttrasistor und Verfahren zu seiner Herstellung
EP1631990B1 (de) Herstellungsverfahren für einen feldeffekttransistor
DE102009034405B4 (de) Halbleitervorrichtungen und Verfahren zum Herstellen einer Halbleitervorrichtung
DE19749378B4 (de) MOS-Transistor und Verfahren zu dessen Herstellung
DE69834886T2 (de) Vertikaler Transistor implementiert in einer Speicherzelle mit Grabenkondensator
DE102015205458B3 (de) Verfahren zum Herstellen einer Halbleitervorrichtungsstruktur
DE102005016925B4 (de) Verfahren zum Herstellen eines Transistors mit einem high-k-Gate-Dielektrikum
DE102012206998B4 (de) Verfahren zur Herstellung einer Halbleiterbauelementstruktur und Halbleiterbauelementstruktur
DE19957540A1 (de) Verfahren zum Herstellen eines Feldeffekttransistors mit Anti-Punch-Through-Implantationsgebiet
WO2000041238A1 (de) Elektrisch programmierbare speicherzellenanordnung und verfahren zu deren herstellung

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

17P Request for examination filed

Effective date: 20050316

AK Designated contracting states

Kind code of ref document: A1

Designated state(s): AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IT LI LU MC NL PT RO SE SI SK TR

RBV Designated contracting states (corrected)

Designated state(s): DE FR IT

RIN1 Information on inventor provided before grant (corrected)

Inventor name: TEWS, HELMUT

Inventor name: SCHRUEFER, KLAUS

Inventor name: HOLZ, JUERGEN

17Q First examination report despatched

Effective date: 20090626

RAP1 Party data changed (applicant data changed or rights of an application transferred)

Owner name: INFINEON TECHNOLOGIES AG

GRAP Despatch of communication of intention to grant a patent

Free format text: ORIGINAL CODE: EPIDOSNIGR1

RIC1 Information provided on ipc code assigned before grant

Ipc: H01L 29/06 20060101ALI20141023BHEP

Ipc: H01L 29/78 20060101ALI20141023BHEP

Ipc: H01L 21/336 20060101AFI20141023BHEP

INTG Intention to grant announced

Effective date: 20141117

GRAS Grant fee paid

Free format text: ORIGINAL CODE: EPIDOSNIGR3

GRAA (expected) grant

Free format text: ORIGINAL CODE: 0009210

AK Designated contracting states

Kind code of ref document: B1

Designated state(s): DE FR IT

REG Reference to a national code

Ref country code: DE

Ref legal event code: R096

Ref document number: 50315205

Country of ref document: DE

Effective date: 20150402

REG Reference to a national code

Ref country code: DE

Ref legal event code: R097

Ref document number: 50315205

Country of ref document: DE

PLBE No opposition filed within time limit

Free format text: ORIGINAL CODE: 0009261

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: NO OPPOSITION FILED WITHIN TIME LIMIT

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: IT

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20150218

26N No opposition filed

Effective date: 20151119

REG Reference to a national code

Ref country code: FR

Ref legal event code: ST

Effective date: 20160531

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: FR

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20150930

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: DE

Payment date: 20171129

Year of fee payment: 15

REG Reference to a national code

Ref country code: DE

Ref legal event code: R119

Ref document number: 50315205

Country of ref document: DE

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: DE

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20190402