DE69942628D1 - Halbleiterspeichersystem und Zugriffverfahren für Halbleiterspeicher und Halbleiterspeicher - Google Patents
Halbleiterspeichersystem und Zugriffverfahren für Halbleiterspeicher und HalbleiterspeicherInfo
- Publication number
- DE69942628D1 DE69942628D1 DE69942628T DE69942628T DE69942628D1 DE 69942628 D1 DE69942628 D1 DE 69942628D1 DE 69942628 T DE69942628 T DE 69942628T DE 69942628 T DE69942628 T DE 69942628T DE 69942628 D1 DE69942628 D1 DE 69942628D1
- Authority
- DE
- Germany
- Prior art keywords
- semiconductor memory
- access method
- memory system
- semiconductor
- access
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4094—Bit-line management or control circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1072—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
- G11C2207/002—Isolation gates, i.e. gates coupling bit lines to the sense amplifier
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Dram (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP12436798A JP4226686B2 (ja) | 1998-05-07 | 1998-05-07 | 半導体メモリシステム及び半導体メモリのアクセス制御方法及び半導体メモリ |
Publications (1)
Publication Number | Publication Date |
---|---|
DE69942628D1 true DE69942628D1 (de) | 2010-09-09 |
Family
ID=14883656
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69942628T Expired - Lifetime DE69942628D1 (de) | 1998-05-07 | 1999-05-07 | Halbleiterspeichersystem und Zugriffverfahren für Halbleiterspeicher und Halbleiterspeicher |
Country Status (6)
Country | Link |
---|---|
US (4) | US5973991A (de) |
EP (1) | EP0955639B1 (de) |
JP (1) | JP4226686B2 (de) |
KR (1) | KR100326575B1 (de) |
DE (1) | DE69942628D1 (de) |
TW (1) | TW409394B (de) |
Families Citing this family (48)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3782227B2 (ja) * | 1997-03-11 | 2006-06-07 | 株式会社東芝 | 半導体記憶装置 |
KR100323254B1 (ko) * | 1998-04-24 | 2002-02-04 | 아끼구사 나오유끼 | 반도체 집적 회로 |
US6295231B1 (en) | 1998-07-17 | 2001-09-25 | Kabushiki Kaisha Toshiba | High-speed cycle clock-synchronous memory device |
JP4043151B2 (ja) * | 1998-08-26 | 2008-02-06 | 富士通株式会社 | 高速ランダムアクセス可能なメモリデバイス |
JP2000137983A (ja) * | 1998-08-26 | 2000-05-16 | Toshiba Corp | 半導体記憶装置 |
US6044032A (en) * | 1998-12-03 | 2000-03-28 | Micron Technology, Inc. | Addressing scheme for a double data rate SDRAM |
US6081477A (en) * | 1998-12-03 | 2000-06-27 | Micron Technology, Inc. | Write scheme for a double data rate SDRAM |
JP4034923B2 (ja) * | 1999-05-07 | 2008-01-16 | 富士通株式会社 | 半導体記憶装置の動作制御方法および半導体記憶装置 |
JP3706772B2 (ja) * | 1999-07-12 | 2005-10-19 | 富士通株式会社 | 半導体集積回路 |
US6191988B1 (en) * | 1999-07-22 | 2001-02-20 | International Business Machines Corporation | Floating bitline timer allowing a shared equalizer DRAM sense amplifier |
JP2001143464A (ja) * | 1999-11-11 | 2001-05-25 | Nec Ic Microcomput Syst Ltd | 半導体記憶装置 |
DE19956829A1 (de) * | 1999-11-25 | 2001-06-07 | Siemens Ag | Speichereinrichtung für Prozessorsysteme |
JP4083944B2 (ja) | 1999-12-13 | 2008-04-30 | 東芝マイクロエレクトロニクス株式会社 | 半導体記憶装置 |
US6373778B1 (en) | 2000-01-28 | 2002-04-16 | Mosel Vitelic, Inc. | Burst operations in memories |
US6191997B1 (en) | 2000-03-10 | 2001-02-20 | Mosel Vitelic Inc. | Memory burst operations in which address count bits are used as column address bits for one, but not both, of the odd and even columns selected in parallel. |
JP4552258B2 (ja) * | 2000-03-29 | 2010-09-29 | エルピーダメモリ株式会社 | 半導体記憶装置 |
US7088604B2 (en) * | 2001-03-15 | 2006-08-08 | Micron Technology, Inc. | Multi-bank memory |
US6404689B1 (en) * | 2001-03-30 | 2002-06-11 | International Business Machines Corporation | Method and structure for hiding a refresh operation in a DRAM having an interlocked pipeline |
KR100401508B1 (ko) | 2001-05-25 | 2003-10-17 | 주식회사 하이닉스반도체 | 램버스 디램의 뱅크 제어회로 |
US6445611B1 (en) * | 2001-09-28 | 2002-09-03 | International Business Machines Corporation | Method and arrangement for preconditioning in a destructive read memory |
US6791859B2 (en) * | 2001-11-20 | 2004-09-14 | Micron Technology, Inc. | Complementary bit PCRAM sense amplifier and method of operation |
US6501695B1 (en) * | 2002-01-11 | 2002-12-31 | Lsi Logic Corporation | Technique for the reduction of memory access time variation |
JP2003233989A (ja) * | 2002-02-07 | 2003-08-22 | Fujitsu Ltd | 半導体記憶装置及びプリチャージ方法 |
KR100412142B1 (ko) * | 2002-02-26 | 2003-12-31 | 주식회사 하이닉스반도체 | 패킷 전송 방식의 반도체 메모리 장치에서 스페셜 모드를구현하는 회로 |
US6917552B2 (en) * | 2002-03-05 | 2005-07-12 | Renesas Technology Corporation | Semiconductor device using high-speed sense amplifier |
US6590819B1 (en) * | 2002-03-14 | 2003-07-08 | Micron Technology, Inc. | Digit line equilibration using time-multiplexed isolation |
JP4544808B2 (ja) * | 2002-04-09 | 2010-09-15 | 富士通セミコンダクター株式会社 | 半導体記憶装置の制御方法、および半導体記憶装置 |
JP2003331578A (ja) * | 2002-05-14 | 2003-11-21 | Toshiba Corp | メモリシステム及びそのデータ書き込み方法 |
KR100486260B1 (ko) * | 2002-09-11 | 2005-05-03 | 삼성전자주식회사 | 동기식 디램의 고주파수 동작을 위한 비트라인 센스앰프구동 제어회로 및 그 구동 제어방법 |
KR100506448B1 (ko) * | 2002-12-27 | 2005-08-08 | 주식회사 하이닉스반도체 | 불휘발성 강유전체 메모리를 이용한 인터리브 제어 장치 |
KR100525460B1 (ko) * | 2003-05-23 | 2005-10-31 | (주)실리콘세븐 | 2개의 메모리 블락 사이에 3개의 센스앰프를 가지며,인출과 기입 동작 구간이 분리되는 리프레쉬 동작을수행하는 에스램 호환 메모리 및 그 구동방법 |
JP4278438B2 (ja) * | 2003-05-27 | 2009-06-17 | 三洋電機株式会社 | 不揮発性半導体記憶装置及びその制御方法 |
US7215595B2 (en) * | 2003-11-26 | 2007-05-08 | Infineon Technologies Ag | Memory device and method using a sense amplifier as a cache |
EP3001321B1 (de) | 2004-02-05 | 2018-07-11 | BlackBerry Limited | Speichersteuerungsschnittstelle |
KR100706232B1 (ko) * | 2004-07-08 | 2007-04-11 | 삼성전자주식회사 | 결함 셀을 스크린할 수 있는 반도체 메모리 장치 및스크린 방법 |
JP2006059046A (ja) * | 2004-08-19 | 2006-03-02 | Nec Computertechno Ltd | メモリの制御方式およびメモリ制御回路 |
US7203102B2 (en) * | 2004-10-27 | 2007-04-10 | Infineon Technologies, Ag | Semiconductor memory having tri-state driver device |
US7362651B2 (en) * | 2006-05-12 | 2008-04-22 | International Business Machines Corporation | Using common mode differential data signals of DDR2 SDRAM for control signal transmission |
JP4808070B2 (ja) * | 2006-05-18 | 2011-11-02 | 富士通セミコンダクター株式会社 | 半導体メモリおよび半導体メモリの動作方法 |
KR100867636B1 (ko) * | 2007-02-13 | 2008-11-10 | 엠텍비젼 주식회사 | 고속 동작이 가능한 스택 뱅크 메모리 |
KR101286237B1 (ko) | 2007-07-10 | 2013-07-15 | 삼성전자주식회사 | 반도체 메모리 장치의 비트라인 센스앰프회로 및 그에 따른제어방법. |
KR101455253B1 (ko) | 2007-11-15 | 2014-10-28 | 삼성전자주식회사 | 메모리 컨트롤러 |
US8149643B2 (en) | 2008-10-23 | 2012-04-03 | Cypress Semiconductor Corporation | Memory device and method |
KR101673233B1 (ko) | 2010-05-11 | 2016-11-17 | 삼성전자주식회사 | 트랜잭션 분할 장치 및 방법 |
WO2013033016A1 (en) * | 2011-08-30 | 2013-03-07 | Rambus Inc | Distributed sub-page selection |
US10373665B2 (en) * | 2016-03-10 | 2019-08-06 | Micron Technology, Inc. | Parallel access techniques within memory sections through section independence |
TWI734781B (zh) * | 2016-05-20 | 2021-08-01 | 日商半導體能源研究所股份有限公司 | 半導體裝置、電子構件及電子裝置 |
US11170841B2 (en) * | 2020-02-26 | 2021-11-09 | Micron Technology, Inc. | Apparatus with extended digit lines and methods for operating the same |
Family Cites Families (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4924375A (en) * | 1987-10-23 | 1990-05-08 | Chips And Technologies, Inc. | Page interleaved memory access |
JPH0212541A (ja) * | 1988-04-29 | 1990-01-17 | Internatl Business Mach Corp <Ibm> | コンピユーテイング・システム及びその動作方法 |
IL96808A (en) * | 1990-04-18 | 1996-03-31 | Rambus Inc | Introductory / Origin Circuit Agreed Using High-Performance Brokerage |
US5594704A (en) * | 1992-04-27 | 1997-01-14 | Mitsubishi Denki Kabushiki Kaisha | Synchronous semiconductor memory device |
JPH07130175A (ja) * | 1993-09-10 | 1995-05-19 | Toshiba Corp | 半導体記憶装置 |
US5438548A (en) * | 1993-12-10 | 1995-08-01 | Texas Instruments Incorporated | Synchronous memory with reduced power access mode |
JPH07326192A (ja) * | 1994-05-31 | 1995-12-12 | Toshiba Micro Comput Eng Corp | 半導体記憶装置 |
JP2817679B2 (ja) * | 1995-09-20 | 1998-10-30 | 日本電気株式会社 | 半導体メモリ |
US5654932A (en) * | 1995-10-04 | 1997-08-05 | Cirrus Logic, Inc. | Memory devices with selectable access type and methods using the same |
JP4084428B2 (ja) * | 1996-02-02 | 2008-04-30 | 富士通株式会社 | 半導体記憶装置 |
US5815463A (en) * | 1997-06-12 | 1998-09-29 | Etron Technology, Inc | Flexible time write operation |
KR100274591B1 (ko) * | 1997-07-29 | 2001-01-15 | 윤종용 | 동기형 버스트 매스크 롬 및 그것의 데이터 독출 방법 |
US5875141A (en) * | 1997-08-14 | 1999-02-23 | Micron Technology, Inc. | Circuit and method for a memory device with P-channel isolation gates |
JPH11162174A (ja) * | 1997-11-25 | 1999-06-18 | Mitsubishi Electric Corp | 同期型半導体記憶装置 |
US6275435B1 (en) * | 1999-03-31 | 2001-08-14 | Vanguard International Semiconductor Corp. | Bi-directional sense amplifier stage for memory datapath |
-
1998
- 1998-05-07 JP JP12436798A patent/JP4226686B2/ja not_active Expired - Fee Related
-
1999
- 1999-05-03 TW TW088107155A patent/TW409394B/zh not_active IP Right Cessation
- 1999-05-06 US US09/305,752 patent/US5973991A/en not_active Expired - Lifetime
- 1999-05-07 KR KR1019990016250A patent/KR100326575B1/ko not_active IP Right Cessation
- 1999-05-07 DE DE69942628T patent/DE69942628D1/de not_active Expired - Lifetime
- 1999-05-07 EP EP99108592A patent/EP0955639B1/de not_active Expired - Lifetime
- 1999-10-04 US US09/411,373 patent/US6256258B1/en not_active Expired - Fee Related
-
2001
- 2001-05-10 US US09/852,037 patent/US6335904B1/en not_active Expired - Fee Related
- 2001-11-09 US US09/986,658 patent/US6442088B1/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
EP0955639A2 (de) | 1999-11-10 |
US6335904B1 (en) | 2002-01-01 |
US20020027830A1 (en) | 2002-03-07 |
US6442088B1 (en) | 2002-08-27 |
JPH11317072A (ja) | 1999-11-16 |
EP0955639A3 (de) | 2000-05-10 |
JP4226686B2 (ja) | 2009-02-18 |
KR19990088093A (ko) | 1999-12-27 |
US5973991A (en) | 1999-10-26 |
TW409394B (en) | 2000-10-21 |
EP0955639B1 (de) | 2010-07-28 |
KR100326575B1 (ko) | 2002-03-12 |
US6256258B1 (en) | 2001-07-03 |
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