DE602005025976D1 - Herstellungsverfahren für ein siliziumcarbidhalbleiterbauelement - Google Patents

Herstellungsverfahren für ein siliziumcarbidhalbleiterbauelement

Info

Publication number
DE602005025976D1
DE602005025976D1 DE602005025976T DE602005025976T DE602005025976D1 DE 602005025976 D1 DE602005025976 D1 DE 602005025976D1 DE 602005025976 T DE602005025976 T DE 602005025976T DE 602005025976 T DE602005025976 T DE 602005025976T DE 602005025976 D1 DE602005025976 D1 DE 602005025976D1
Authority
DE
Germany
Prior art keywords
silicon carbide
carbide substrate
manufacturing
semiconductor element
carbon layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
DE602005025976T
Other languages
English (en)
Inventor
Kunimasa Takahashi
Makoto Kitabatake
Kenya Yamashita
Masao Uchida
Osamu Kusumoto
Ryoko Miyanaga
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Corp
Original Assignee
Panasonic Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Panasonic Corp filed Critical Panasonic Corp
Publication of DE602005025976D1 publication Critical patent/DE602005025976D1/de
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/1608Silicon carbide
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/0445Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising crystalline silicon carbide
    • H01L21/0455Making n or p doped regions or layers, e.g. using diffusion
    • H01L21/046Making n or p doped regions or layers, e.g. using diffusion using ion implantation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66053Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
    • H01L29/66068Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Ceramic Engineering (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Carbon And Carbon Compounds (AREA)
  • Bipolar Transistors (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
  • Junction Field-Effect Transistors (AREA)
DE602005025976T 2004-02-06 2005-01-28 Herstellungsverfahren für ein siliziumcarbidhalbleiterbauelement Active DE602005025976D1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2004030972 2004-02-06
PCT/JP2005/001240 WO2005076327A1 (ja) 2004-02-06 2005-01-28 炭化珪素半導体素子及びその製造方法

Publications (1)

Publication Number Publication Date
DE602005025976D1 true DE602005025976D1 (de) 2011-03-03

Family

ID=34836022

Family Applications (1)

Application Number Title Priority Date Filing Date
DE602005025976T Active DE602005025976D1 (de) 2004-02-06 2005-01-28 Herstellungsverfahren für ein siliziumcarbidhalbleiterbauelement

Country Status (8)

Country Link
US (1) US7462540B2 (de)
EP (1) EP1713117B1 (de)
JP (1) JP4418794B2 (de)
KR (1) KR20060125700A (de)
CN (1) CN100490077C (de)
AT (1) ATE496392T1 (de)
DE (1) DE602005025976D1 (de)
WO (1) WO2005076327A1 (de)

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WO2008016619A1 (en) * 2006-07-31 2008-02-07 Vishay-Siliconix Molybdenum barrier metal for sic schottky diode and process of manufacture
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JP5518326B2 (ja) * 2008-12-26 2014-06-11 昭和電工株式会社 炭化珪素半導体装置の製造方法
JP5406279B2 (ja) * 2009-03-26 2014-02-05 キヤノンアネルバ株式会社 基板処理方法および結晶性炭化ケイ素(SiC)基板の製造方法
JP5525940B2 (ja) * 2009-07-21 2014-06-18 ローム株式会社 半導体装置および半導体装置の製造方法
US8242030B2 (en) * 2009-09-25 2012-08-14 International Business Machines Corporation Activation of graphene buffer layers on silicon carbide by ultra low temperature oxidation
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JP5220049B2 (ja) * 2010-03-09 2013-06-26 三菱電機株式会社 炭化珪素半導体装置の製造方法
JP5766495B2 (ja) * 2010-05-18 2015-08-19 株式会社日立ハイテクノロジーズ 熱処理装置
JP2010239152A (ja) * 2010-06-23 2010-10-21 Mitsubishi Electric Corp 炭化珪素半導体装置
JP5954856B2 (ja) 2011-02-01 2016-07-20 ルネサスエレクトロニクス株式会社 縦チャネル型ノーマリオフ型パワーjfetの製造方法
JP5799458B2 (ja) * 2011-03-29 2015-10-28 学校法人関西学院 半導体素子の製造方法
WO2012157679A1 (ja) * 2011-05-18 2012-11-22 ローム株式会社 半導体装置およびその製造方法
JP5759293B2 (ja) * 2011-07-20 2015-08-05 住友電気工業株式会社 半導体装置の製造方法
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JP2015065316A (ja) * 2013-09-25 2015-04-09 住友電気工業株式会社 炭化珪素半導体装置の製造方法
WO2015072210A1 (ja) * 2013-11-13 2015-05-21 三菱電機株式会社 半導体装置の製造方法
WO2015146161A1 (ja) * 2014-03-24 2015-10-01 キヤノンアネルバ株式会社 半導体基板の熱処理方法、半導体基板の製造方法、熱処理装置、及び基板処理システム
US10403509B2 (en) * 2014-04-04 2019-09-03 The Government Of The United States Of America, As Represented By The Secretary Of The Navy Basal plane dislocation elimination in 4H—SiC by pulsed rapid thermal annealing
US20160045881A1 (en) * 2014-08-15 2016-02-18 Rec Silicon Inc High-purity silicon to form silicon carbide for use in a fluidized bed reactor
JP6472016B2 (ja) * 2014-09-25 2019-02-20 国立研究開発法人産業技術総合研究所 炭化珪素半導体装置の製造方法
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Also Published As

Publication number Publication date
CN100490077C (zh) 2009-05-20
WO2005076327A1 (ja) 2005-08-18
US7462540B2 (en) 2008-12-09
EP1713117B1 (de) 2011-01-19
CN1788335A (zh) 2006-06-14
JP4418794B2 (ja) 2010-02-24
EP1713117A4 (de) 2009-07-22
KR20060125700A (ko) 2006-12-06
ATE496392T1 (de) 2011-02-15
US20060220027A1 (en) 2006-10-05
JPWO2005076327A1 (ja) 2007-08-02
EP1713117A1 (de) 2006-10-18

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