ATE486366T1 - Verfahren zum herstellen einer halbleiter-auf- isolator-struktur - Google Patents

Verfahren zum herstellen einer halbleiter-auf- isolator-struktur

Info

Publication number
ATE486366T1
ATE486366T1 AT06842379T AT06842379T ATE486366T1 AT E486366 T1 ATE486366 T1 AT E486366T1 AT 06842379 T AT06842379 T AT 06842379T AT 06842379 T AT06842379 T AT 06842379T AT E486366 T1 ATE486366 T1 AT E486366T1
Authority
AT
Austria
Prior art keywords
semiconductor
oxide layer
making
oxide
optoelectronics
Prior art date
Application number
AT06842379T
Other languages
English (en)
Inventor
Oleg Kononchuk
Original Assignee
Soitec Silicon On Insulator
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Soitec Silicon On Insulator filed Critical Soitec Silicon On Insulator
Application granted granted Critical
Publication of ATE486366T1 publication Critical patent/ATE486366T1/de

Links

Classifications

    • H10P90/1916—
    • H10W10/181—

Landscapes

  • Recrystallisation Techniques (AREA)
  • Element Separation (AREA)
  • Bipolar Transistors (AREA)
  • Formation Of Insulating Films (AREA)
AT06842379T 2006-12-26 2006-12-26 Verfahren zum herstellen einer halbleiter-auf- isolator-struktur ATE486366T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/IB2006/003958 WO2008078133A1 (en) 2006-12-26 2006-12-26 Method for producing a semiconductor-on-insulator structure

Publications (1)

Publication Number Publication Date
ATE486366T1 true ATE486366T1 (de) 2010-11-15

Family

ID=38109562

Family Applications (1)

Application Number Title Priority Date Filing Date
AT06842379T ATE486366T1 (de) 2006-12-26 2006-12-26 Verfahren zum herstellen einer halbleiter-auf- isolator-struktur

Country Status (6)

Country Link
US (1) US7531430B2 (de)
EP (1) EP2095415B1 (de)
JP (1) JP5185284B2 (de)
AT (1) ATE486366T1 (de)
DE (1) DE602006017906D1 (de)
WO (1) WO2008078133A1 (de)

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101548369B (zh) * 2006-12-26 2012-07-18 硅绝缘体技术有限公司 制造绝缘体上半导体结构的方法
FR2933233B1 (fr) * 2008-06-30 2010-11-26 Soitec Silicon On Insulator Substrat de haute resistivite bon marche et procede de fabrication associe
FR2933234B1 (fr) * 2008-06-30 2016-09-23 S O I Tec Silicon On Insulator Tech Substrat bon marche a structure double et procede de fabrication associe
FR2933235B1 (fr) * 2008-06-30 2010-11-26 Soitec Silicon On Insulator Substrat bon marche et procede de fabrication associe
FR2933534B1 (fr) * 2008-07-03 2011-04-01 Soitec Silicon On Insulator Procede de fabrication d'une structure comprenant une couche de germanium sur un substrat
FR2935067B1 (fr) 2008-08-14 2011-02-25 Commissariat Energie Atomique Procede de fabrication d'une structure semi-conductrice plan de masse enterre
FR2983342B1 (fr) * 2011-11-30 2016-05-20 Soitec Silicon On Insulator Procede de fabrication d'une heterostructure limitant la formation de defauts et heterostructure ainsi obtenue
FR2987166B1 (fr) 2012-02-16 2017-05-12 Soitec Silicon On Insulator Procede de transfert d'une couche
FR3003684B1 (fr) * 2013-03-25 2015-03-27 Soitec Silicon On Insulator Procede de dissolution d'une couche de dioxyde de silicium.
FR3027451B1 (fr) * 2014-10-21 2016-11-04 Soitec Silicon On Insulator Substrat et procede de fabrication d'un substrat
FR3036200B1 (fr) * 2015-05-13 2017-05-05 Soitec Silicon On Insulator Methode de calibration pour equipements de traitement thermique
JP6353814B2 (ja) * 2015-06-09 2018-07-04 信越半導体株式会社 貼り合わせｓｏｉウェーハの製造方法
US9870940B2 (en) 2015-08-03 2018-01-16 Samsung Electronics Co., Ltd. Methods of forming nanosheets on lattice mismatched substrates
US10026642B2 (en) 2016-03-07 2018-07-17 Sunedison Semiconductor Limited (Uen201334164H) Semiconductor on insulator structure comprising a sacrificial layer and method of manufacture thereof
US9892920B1 (en) * 2017-01-05 2018-02-13 Lam Research Corporation Low stress bonding of silicon or germanium parts
JP7034186B2 (ja) * 2017-07-14 2022-03-11 サンエディソン・セミコンダクター・リミテッド 絶縁体上半導体構造の製造方法
EP3774256A4 (de) * 2018-04-05 2022-03-09 ExxonMobil Chemical Patents Inc. Verbesserung der vernetzten kautschukdispersion bei thermoplastischen vulkanisaten
KR102287003B1 (ko) * 2018-06-22 2021-08-09 엔지케이 인슐레이터 엘티디 접합체 및 탄성파 소자
FR3098985B1 (fr) 2019-07-15 2022-04-08 Soitec Silicon On Insulator Procédé de collage hydrophile de substrats
FR3106235B1 (fr) * 2020-01-09 2021-12-10 Soitec Silicon On Insulator Procede d’assemblage de deux substrats semi-conducteurs
CN115777139A (zh) * 2020-07-28 2023-03-10 索泰克公司 将薄层转移到设有电荷俘获层的载体衬底的方法

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EP1583143B1 (de) 2004-03-29 2011-10-05 Imec Methode zur Herstellung von selbst-justierten Source/Drain-Kontakten in einem Doppel-Gate-FET unter kontrollierter Herstellung eines dünnen Si- oder Nicht-Si-Kanals
JP4631347B2 (ja) 2004-08-06 2011-02-16 株式会社Sumco 部分ｓｏｉ基板およびその製造方法
JP4830290B2 (ja) * 2004-11-30 2011-12-07 信越半導体株式会社 直接接合ウェーハの製造方法
US8138061B2 (en) * 2005-01-07 2012-03-20 International Business Machines Corporation Quasi-hydrophobic Si-Si wafer bonding using hydrophilic Si surfaces and dissolution of interfacial bonding oxide

Also Published As

Publication number Publication date
JP2010515254A (ja) 2010-05-06
EP2095415A1 (de) 2009-09-02
DE602006017906D1 (de) 2010-12-09
WO2008078133A1 (en) 2008-07-03
US20080153313A1 (en) 2008-06-26
US7531430B2 (en) 2009-05-12
JP5185284B2 (ja) 2013-04-17
EP2095415B1 (de) 2010-10-27

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