ATE486366T1 - Verfahren zum herstellen einer halbleiter-auf- isolator-struktur - Google Patents
Verfahren zum herstellen einer halbleiter-auf- isolator-strukturInfo
- Publication number
- ATE486366T1 ATE486366T1 AT06842379T AT06842379T ATE486366T1 AT E486366 T1 ATE486366 T1 AT E486366T1 AT 06842379 T AT06842379 T AT 06842379T AT 06842379 T AT06842379 T AT 06842379T AT E486366 T1 ATE486366 T1 AT E486366T1
- Authority
- AT
- Austria
- Prior art keywords
- semiconductor
- oxide layer
- making
- oxide
- optoelectronics
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title abstract 5
- 238000000034 method Methods 0.000 title abstract 4
- 239000012212 insulator Substances 0.000 title 1
- 238000010438 heat treatment Methods 0.000 abstract 2
- 239000000463 material Substances 0.000 abstract 2
- 230000005693 optoelectronics Effects 0.000 abstract 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 abstract 1
- 230000007423 decrease Effects 0.000 abstract 1
- 238000004519 manufacturing process Methods 0.000 abstract 1
- 229910052760 oxygen Inorganic materials 0.000 abstract 1
- 239000001301 oxygen Substances 0.000 abstract 1
- 239000000758 substrate Substances 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Recrystallisation Techniques (AREA)
- Element Separation (AREA)
- Bipolar Transistors (AREA)
- Formation Of Insulating Films (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| PCT/IB2006/003958 WO2008078133A1 (en) | 2006-12-26 | 2006-12-26 | Method for producing a semiconductor-on-insulator structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| ATE486366T1 true ATE486366T1 (de) | 2010-11-15 |
Family
ID=38109562
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| AT06842379T ATE486366T1 (de) | 2006-12-26 | 2006-12-26 | Verfahren zum herstellen einer halbleiter-auf- isolator-struktur |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US7531430B2 (de) |
| EP (1) | EP2095415B1 (de) |
| JP (1) | JP5185284B2 (de) |
| AT (1) | ATE486366T1 (de) |
| DE (1) | DE602006017906D1 (de) |
| WO (1) | WO2008078133A1 (de) |
Families Citing this family (21)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP2095406A1 (de) * | 2006-12-26 | 2009-09-02 | S.O.I.Tec Silicon on Insulator Technologies | Verfahren zum herstellen einer halbleiter-auf-isolator-struktur |
| FR2933235B1 (fr) * | 2008-06-30 | 2010-11-26 | Soitec Silicon On Insulator | Substrat bon marche et procede de fabrication associe |
| FR2933234B1 (fr) * | 2008-06-30 | 2016-09-23 | S O I Tec Silicon On Insulator Tech | Substrat bon marche a structure double et procede de fabrication associe |
| FR2933233B1 (fr) * | 2008-06-30 | 2010-11-26 | Soitec Silicon On Insulator | Substrat de haute resistivite bon marche et procede de fabrication associe |
| FR2933534B1 (fr) * | 2008-07-03 | 2011-04-01 | Soitec Silicon On Insulator | Procede de fabrication d'une structure comprenant une couche de germanium sur un substrat |
| FR2935067B1 (fr) * | 2008-08-14 | 2011-02-25 | Commissariat Energie Atomique | Procede de fabrication d'une structure semi-conductrice plan de masse enterre |
| FR2983342B1 (fr) * | 2011-11-30 | 2016-05-20 | Soitec Silicon On Insulator | Procede de fabrication d'une heterostructure limitant la formation de defauts et heterostructure ainsi obtenue |
| FR2987166B1 (fr) | 2012-02-16 | 2017-05-12 | Soitec Silicon On Insulator | Procede de transfert d'une couche |
| FR3003684B1 (fr) * | 2013-03-25 | 2015-03-27 | Soitec Silicon On Insulator | Procede de dissolution d'une couche de dioxyde de silicium. |
| FR3027451B1 (fr) * | 2014-10-21 | 2016-11-04 | Soitec Silicon On Insulator | Substrat et procede de fabrication d'un substrat |
| FR3036200B1 (fr) * | 2015-05-13 | 2017-05-05 | Soitec Silicon On Insulator | Methode de calibration pour equipements de traitement thermique |
| JP6353814B2 (ja) * | 2015-06-09 | 2018-07-04 | 信越半導体株式会社 | 貼り合わせｓｏｉウェーハの製造方法 |
| US9870940B2 (en) | 2015-08-03 | 2018-01-16 | Samsung Electronics Co., Ltd. | Methods of forming nanosheets on lattice mismatched substrates |
| US10026642B2 (en) | 2016-03-07 | 2018-07-17 | Sunedison Semiconductor Limited (Uen201334164H) | Semiconductor on insulator structure comprising a sacrificial layer and method of manufacture thereof |
| US9892920B1 (en) * | 2017-01-05 | 2018-02-13 | Lam Research Corporation | Low stress bonding of silicon or germanium parts |
| KR102390772B1 (ko) * | 2017-07-14 | 2022-04-25 | 썬에디슨 세미컨덕터 리미티드 | 반도체 온 절연체 구조의 제조 방법 |
| WO2019195578A1 (en) * | 2018-04-05 | 2019-10-10 | Exxonmobil Chemical Patents Inc. | Improving crosslinked rubber dispersion in thermoplastic vulcanizates |
| KR102287003B1 (ko) * | 2018-06-22 | 2021-08-09 | 엔지케이 인슐레이터 엘티디 | 접합체 및 탄성파 소자 |
| FR3098985B1 (fr) * | 2019-07-15 | 2022-04-08 | Soitec Silicon On Insulator | Procédé de collage hydrophile de substrats |
| FR3106235B1 (fr) * | 2020-01-09 | 2021-12-10 | Soitec Silicon On Insulator | Procede d’assemblage de deux substrats semi-conducteurs |
| EP4189734B1 (de) * | 2020-07-28 | 2024-06-26 | Soitec | Verfahren zum übertragen einer dünnen schicht auf ein trägersubstrat mit ladungseinfangschicht |
Family Cites Families (20)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4786608A (en) * | 1986-12-30 | 1988-11-22 | Harris Corp. | Technique for forming electric field shielding layer in oxygen-implanted silicon substrate |
| JPH05259418A (ja) * | 1992-03-09 | 1993-10-08 | Nippon Telegr & Teleph Corp <Ntt> | 半導体基板とその製造方法 |
| US5589407A (en) * | 1995-09-06 | 1996-12-31 | Implanted Material Technology, Inc. | Method of treating silicon to obtain thin, buried insulating layer |
| JP3358550B2 (ja) * | 1998-07-07 | 2002-12-24 | 信越半導体株式会社 | Ｓｏｉウエーハの製造方法ならびにこの方法で製造されるｓｏｉウエーハ |
| JP4273540B2 (ja) | 1998-07-21 | 2009-06-03 | 株式会社Ｓｕｍｃｏ | 貼り合わせ半導体基板及びその製造方法 |
| US6944465B2 (en) | 1998-09-22 | 2005-09-13 | Polaris Wireless, Inc. | Estimating the location of a mobile unit based on the elimination of improbable locations |
| US5936261A (en) | 1998-11-18 | 1999-08-10 | Hewlett-Packard Company | Elevated image sensor array which includes isolation between the image sensors and a unique interconnection |
| US6328796B1 (en) | 1999-02-01 | 2001-12-11 | The United States Of America As Represented By The Secretary Of The Navy | Single-crystal material on non-single-crystalline substrate |
| US6368938B1 (en) * | 1999-10-05 | 2002-04-09 | Silicon Wafer Technologies, Inc. | Process for manufacturing a silicon-on-insulator substrate and semiconductor devices on said substrate |
| JP4507395B2 (ja) * | 2000-11-30 | 2010-07-21 | セイコーエプソン株式会社 | 電気光学装置用素子基板の製造方法 |
| KR100476901B1 (ko) * | 2002-05-22 | 2005-03-17 | 삼성전자주식회사 | 소이 반도체기판의 형성방법 |
| JP4407127B2 (ja) * | 2003-01-10 | 2010-02-03 | 信越半導体株式会社 | Ｓｏｉウエーハの製造方法 |
| KR100947815B1 (ko) | 2003-02-19 | 2010-03-15 | 신에쯔 한도타이 가부시키가이샤 | Ｓｏｉ 웨이퍼의 제조 방법 및 ｓｏｉ 웨이퍼 |
| US6861320B1 (en) * | 2003-04-04 | 2005-03-01 | Silicon Wafer Technologies, Inc. | Method of making starting material for chip fabrication comprising a buried silicon nitride layer |
| JP4828230B2 (ja) * | 2004-01-30 | 2011-11-30 | 株式会社Ｓｕｍｃｏ | Ｓｏｉウェーハの製造方法 |
| EP1583143B1 (de) | 2004-03-29 | 2011-10-05 | Imec | Methode zur Herstellung von selbst-justierten Source/Drain-Kontakten in einem Doppel-Gate-FET unter kontrollierter Herstellung eines dünnen Si- oder Nicht-Si-Kanals |
| TWI248681B (en) | 2004-03-29 | 2006-02-01 | Imec Inter Uni Micro Electr | Method for fabricating self-aligned source and drain contacts in a double gate FET with controlled manufacturing of a thin Si or non-Si channel |
| JP4631347B2 (ja) | 2004-08-06 | 2011-02-16 | 株式会社Sumco | 部分ｓｏｉ基板およびその製造方法 |
| JP4830290B2 (ja) * | 2004-11-30 | 2011-12-07 | 信越半導体株式会社 | 直接接合ウェーハの製造方法 |
| US8138061B2 (en) | 2005-01-07 | 2012-03-20 | International Business Machines Corporation | Quasi-hydrophobic Si-Si wafer bonding using hydrophilic Si surfaces and dissolution of interfacial bonding oxide |
-
2006
- 2006-12-26 DE DE602006017906T patent/DE602006017906D1/de active Active
- 2006-12-26 AT AT06842379T patent/ATE486366T1/de not_active IP Right Cessation
- 2006-12-26 JP JP2009543523A patent/JP5185284B2/ja active Active
- 2006-12-26 WO PCT/IB2006/003958 patent/WO2008078133A1/en not_active Ceased
- 2006-12-26 EP EP06842379A patent/EP2095415B1/de active Active
-
2007
- 2007-02-21 US US11/677,179 patent/US7531430B2/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| EP2095415B1 (de) | 2010-10-27 |
| US20080153313A1 (en) | 2008-06-26 |
| US7531430B2 (en) | 2009-05-12 |
| WO2008078133A1 (en) | 2008-07-03 |
| JP5185284B2 (ja) | 2013-04-17 |
| JP2010515254A (ja) | 2010-05-06 |
| DE602006017906D1 (de) | 2010-12-09 |
| EP2095415A1 (de) | 2009-09-02 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| RER | Ceased as to paragraph 5 lit. 3 law introducing patent treaties |