DE602006017906D1 - Verfahren zum herstellen einer halbleiter-auf-isolator-struktur - Google Patents

Verfahren zum herstellen einer halbleiter-auf-isolator-struktur

Info

Publication number
DE602006017906D1
DE602006017906D1 DE602006017906T DE602006017906T DE602006017906D1 DE 602006017906 D1 DE602006017906 D1 DE 602006017906D1 DE 602006017906 T DE602006017906 T DE 602006017906T DE 602006017906 T DE602006017906 T DE 602006017906T DE 602006017906 D1 DE602006017906 D1 DE 602006017906D1
Authority
DE
Germany
Prior art keywords
semiconductor
oxide layer
producing
oxide
optoelectronics
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
DE602006017906T
Other languages
English (en)
Inventor
Oleg Kononchuk
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Soitec SA
Original Assignee
Soitec SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Soitec SA filed Critical Soitec SA
Publication of DE602006017906D1 publication Critical patent/DE602006017906D1/de
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Recrystallisation Techniques (AREA)
  • Element Separation (AREA)
  • Formation Of Insulating Films (AREA)
  • Bipolar Transistors (AREA)
DE602006017906T 2006-12-26 2006-12-26 Verfahren zum herstellen einer halbleiter-auf-isolator-struktur Active DE602006017906D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/IB2006/003958 WO2008078133A1 (en) 2006-12-26 2006-12-26 Method for producing a semiconductor-on-insulator structure

Publications (1)

Publication Number Publication Date
DE602006017906D1 true DE602006017906D1 (de) 2010-12-09

Family

ID=38109562

Family Applications (1)

Application Number Title Priority Date Filing Date
DE602006017906T Active DE602006017906D1 (de) 2006-12-26 2006-12-26 Verfahren zum herstellen einer halbleiter-auf-isolator-struktur

Country Status (6)

Country Link
US (1) US7531430B2 (de)
EP (1) EP2095415B1 (de)
JP (1) JP5185284B2 (de)
AT (1) ATE486366T1 (de)
DE (1) DE602006017906D1 (de)
WO (1) WO2008078133A1 (de)

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101548369B (zh) * 2006-12-26 2012-07-18 硅绝缘体技术有限公司 制造绝缘体上半导体结构的方法
FR2933235B1 (fr) * 2008-06-30 2010-11-26 Soitec Silicon On Insulator Substrat bon marche et procede de fabrication associe
FR2933233B1 (fr) * 2008-06-30 2010-11-26 Soitec Silicon On Insulator Substrat de haute resistivite bon marche et procede de fabrication associe
FR2933234B1 (fr) * 2008-06-30 2016-09-23 S O I Tec Silicon On Insulator Tech Substrat bon marche a structure double et procede de fabrication associe
FR2933534B1 (fr) * 2008-07-03 2011-04-01 Soitec Silicon On Insulator Procede de fabrication d'une structure comprenant une couche de germanium sur un substrat
FR2935067B1 (fr) * 2008-08-14 2011-02-25 Commissariat Energie Atomique Procede de fabrication d'une structure semi-conductrice plan de masse enterre
FR2983342B1 (fr) * 2011-11-30 2016-05-20 Soitec Silicon On Insulator Procede de fabrication d'une heterostructure limitant la formation de defauts et heterostructure ainsi obtenue
FR2987166B1 (fr) 2012-02-16 2017-05-12 Soitec Silicon On Insulator Procede de transfert d'une couche
FR3003684B1 (fr) * 2013-03-25 2015-03-27 Soitec Silicon On Insulator Procede de dissolution d'une couche de dioxyde de silicium.
FR3027451B1 (fr) * 2014-10-21 2016-11-04 Soitec Silicon On Insulator Substrat et procede de fabrication d'un substrat
FR3036200B1 (fr) * 2015-05-13 2017-05-05 Soitec Silicon On Insulator Methode de calibration pour equipements de traitement thermique
JP6353814B2 (ja) * 2015-06-09 2018-07-04 信越半導体株式会社 貼り合わせｓｏｉウェーハの製造方法
US9870940B2 (en) 2015-08-03 2018-01-16 Samsung Electronics Co., Ltd. Methods of forming nanosheets on lattice mismatched substrates
US10026642B2 (en) 2016-03-07 2018-07-17 Sunedison Semiconductor Limited (Uen201334164H) Semiconductor on insulator structure comprising a sacrificial layer and method of manufacture thereof
US9892920B1 (en) * 2017-01-05 2018-02-13 Lam Research Corporation Low stress bonding of silicon or germanium parts
WO2019013904A1 (en) * 2017-07-14 2019-01-17 Globalwafers Co., Ltd. METHOD FOR MANUFACTURING SEMICONDUCTOR STRUCTURE ON INSULATION
CN112135723A (zh) * 2018-04-05 2020-12-25 埃克森美孚化学专利公司 改进热塑性硫化橡胶中交联橡胶的分散
WO2019244461A1 (ja) * 2018-06-22 2019-12-26 日本碍子株式会社 接合体および弾性波素子
FR3098985B1 (fr) * 2019-07-15 2022-04-08 Soitec Silicon On Insulator Procédé de collage hydrophile de substrats

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US4786608A (en) * 1986-12-30 1988-11-22 Harris Corp. Technique for forming electric field shielding layer in oxygen-implanted silicon substrate
JPH05259418A (ja) * 1992-03-09 1993-10-08 Nippon Telegr & Teleph Corp <Ntt> 半導体基板とその製造方法
US5589407A (en) * 1995-09-06 1996-12-31 Implanted Material Technology, Inc. Method of treating silicon to obtain thin, buried insulating layer
JP3358550B2 (ja) * 1998-07-07 2002-12-24 信越半導体株式会社 Ｓｏｉウエーハの製造方法ならびにこの方法で製造されるｓｏｉウエーハ
JP4273540B2 (ja) 1998-07-21 2009-06-03 株式会社Ｓｕｍｃｏ 貼り合わせ半導体基板及びその製造方法
US6944465B2 (en) * 1998-09-22 2005-09-13 Polaris Wireless, Inc. Estimating the location of a mobile unit based on the elimination of improbable locations
US5936261A (en) * 1998-11-18 1999-08-10 Hewlett-Packard Company Elevated image sensor array which includes isolation between the image sensors and a unique interconnection
US6328796B1 (en) * 1999-02-01 2001-12-11 The United States Of America As Represented By The Secretary Of The Navy Single-crystal material on non-single-crystalline substrate
US6368938B1 (en) * 1999-10-05 2002-04-09 Silicon Wafer Technologies, Inc. Process for manufacturing a silicon-on-insulator substrate and semiconductor devices on said substrate
JP4507395B2 (ja) * 2000-11-30 2010-07-21 セイコーエプソン株式会社 電気光学装置用素子基板の製造方法
KR100476901B1 (ko) * 2002-05-22 2005-03-17 삼성전자주식회사 소이 반도체기판의 형성방법
JP4407127B2 (ja) * 2003-01-10 2010-02-03 信越半導体株式会社 Ｓｏｉウエーハの製造方法
JP4442560B2 (ja) * 2003-02-19 2010-03-31 信越半導体株式会社 Ｓｏｉウエーハの製造方法
US6861320B1 (en) * 2003-04-04 2005-03-01 Silicon Wafer Technologies, Inc. Method of making starting material for chip fabrication comprising a buried silicon nitride layer
EP1710836A4 (de) * 2004-01-30 2010-08-18 Sumco Corp Verfahren zur herstellung eines soi-wafers
TWI248681B (en) * 2004-03-29 2006-02-01 Imec Inter Uni Micro Electr Method for fabricating self-aligned source and drain contacts in a double gate FET with controlled manufacturing of a thin Si or non-Si channel
EP1583143B1 (de) 2004-03-29 2011-10-05 Imec Methode zur Herstellung von selbst-justierten Source/Drain-Kontakten in einem Doppel-Gate-FET unter kontrollierter Herstellung eines dünnen Si- oder Nicht-Si-Kanals
JP4631347B2 (ja) 2004-08-06 2011-02-16 株式会社Ｓｕｍｃｏ 部分ｓｏｉ基板およびその製造方法
JP4830290B2 (ja) * 2004-11-30 2011-12-07 信越半導体株式会社 直接接合ウェーハの製造方法
US8138061B2 (en) * 2005-01-07 2012-03-20 International Business Machines Corporation Quasi-hydrophobic Si-Si wafer bonding using hydrophilic Si surfaces and dissolution of interfacial bonding oxide

Also Published As

Publication number Publication date
US20080153313A1 (en) 2008-06-26
WO2008078133A1 (en) 2008-07-03
JP2010515254A (ja) 2010-05-06
JP5185284B2 (ja) 2013-04-17
ATE486366T1 (de) 2010-11-15
EP2095415A1 (de) 2009-09-02
US7531430B2 (en) 2009-05-12
EP2095415B1 (de) 2010-10-27

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