WO2008105136A1 - シリコン単結晶ウエーハの製造方法 - Google Patents

シリコン単結晶ウエーハの製造方法 Download PDF

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Publication number
WO2008105136A1
WO2008105136A1 PCT/JP2008/000070 JP2008000070W WO2008105136A1 WO 2008105136 A1 WO2008105136 A1 WO 2008105136A1 JP 2008000070 W JP2008000070 W JP 2008000070W WO 2008105136 A1 WO2008105136 A1 WO 2008105136A1
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WO
WIPO (PCT)
Prior art keywords
single crystal
silicon single
crystal wafer
atmosphere
wafer
Prior art date
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PCT/JP2008/000070
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English (en)
French (fr)
Inventor
Yoshinori Hayamizu
Hiroyasu Kikuchi
Original Assignee
Shin-Etsu Handotai Co., Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shin-Etsu Handotai Co., Ltd. filed Critical Shin-Etsu Handotai Co., Ltd.
Priority to DE112008000486.2T priority Critical patent/DE112008000486B4/de
Priority to US12/449,200 priority patent/US8187954B2/en
Priority to KR1020097017325A priority patent/KR101416094B1/ko
Publication of WO2008105136A1 publication Critical patent/WO2008105136A1/ja

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    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B15/00—Single-crystal growth by pulling from a melt, e.g. Czochralski method
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
    • C30B29/02—Elements
    • C30B29/06—Silicon
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B33/00—After-treatment of single crystals or homogeneous polycrystalline material with defined structure
    • C30B33/005—Oxydation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/322—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/322—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
    • H01L21/3221—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering
    • H01L21/3225—Thermally inducing defects using oxygen present in the silicon body for intrinsic gettering

Landscapes

  • Chemical & Material Sciences (AREA)
  • Engineering & Computer Science (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Materials Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Toxicology (AREA)
  • Health & Medical Sciences (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
  • Liquid Deposition Of Substances Of Which Semiconductor Devices Are Composed (AREA)

Abstract

　本発明は、シリコン単結晶ウエーハの製造方法であって、チョクラルスキー法により作製した径方向の全面がＮ領域のシリコン単結晶ウエーハを酸化性雰囲気下で急速熱処理し、該酸化性雰囲気下の急速熱処理で形成された酸化膜を除去してから、窒化性雰囲気、Ａｒ雰囲気、またはこれらの混合雰囲気下で急速熱処理するシリコン単結晶ウエーハの製造方法である。これにより、ウエーハ表層にＤＺ層が形成されてデバイス特性が優れていると同時に、ゲッタリングサイトとして機能する酸素析出物をバルク領域内に十分に形成できるシリコン単結晶ウエーハを安価に製造することが可能な製造方法が提供される。
PCT/JP2008/000070 2007-02-26 2008-01-24 シリコン単結晶ウエーハの製造方法 WO2008105136A1 (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
DE112008000486.2T DE112008000486B4 (de) 2007-02-26 2008-01-24 Verfahren zur Herstellung eines Einkristall-Siliziumwafers
US12/449,200 US8187954B2 (en) 2007-02-26 2008-01-24 Method for manufacturing silicon single crystal wafer
KR1020097017325A KR101416094B1 (ko) 2007-02-26 2008-01-24 실리콘 단결정 웨이퍼의 제조방법

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2007-045956 2007-02-26
JP2007045956A JP5167654B2 (ja) 2007-02-26 2007-02-26 シリコン単結晶ウエーハの製造方法

Publications (1)

Publication Number Publication Date
WO2008105136A1 true WO2008105136A1 (ja) 2008-09-04

Family

ID=39720979

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2008/000070 WO2008105136A1 (ja) 2007-02-26 2008-01-24 シリコン単結晶ウエーハの製造方法

Country Status (7)

Country Link
US (1) US8187954B2 (ja)
JP (1) JP5167654B2 (ja)
KR (1) KR101416094B1 (ja)
CN (1) CN101622381A (ja)
DE (1) DE112008000486B4 (ja)
TW (1) TWI402919B (ja)
WO (1) WO2008105136A1 (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2020213230A1 (ja) * 2019-04-16 2020-10-22 信越半導体株式会社 シリコン単結晶ウェーハの製造方法及びシリコン単結晶ウェーハ

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5251137B2 (ja) * 2008-01-16 2013-07-31 株式会社Ｓｕｍｃｏ 単結晶シリコンウェーハおよびその製造方法
JP5512137B2 (ja) * 2009-01-30 2014-06-04 グローバルウェーハズ・ジャパン株式会社 シリコンウェーハの熱処理方法
JP5515406B2 (ja) 2009-05-15 2014-06-11 株式会社Ｓｕｍｃｏ シリコンウェーハおよびその製造方法
JP5997552B2 (ja) * 2011-09-27 2016-09-28 グローバルウェーハズ・ジャパン株式会社 シリコンウェーハの熱処理方法
KR101472349B1 (ko) * 2013-05-21 2014-12-12 주식회사 엘지실트론 반도체용 실리콘 단결정 잉곳 및 웨이퍼
US10177008B2 (en) * 2014-01-14 2019-01-08 Sumco Corporation Silicon wafer and method for manufacturing the same
JP6118765B2 (ja) * 2014-07-03 2017-04-19 信越半導体株式会社 シリコン単結晶ウェーハの熱処理方法
JP6100226B2 (ja) * 2014-11-26 2017-03-22 信越半導体株式会社 シリコン単結晶ウェーハの熱処理方法
JP6044660B2 (ja) * 2015-02-19 2016-12-14 信越半導体株式会社 シリコンウェーハの製造方法
JP6317700B2 (ja) * 2015-04-01 2018-04-25 グローバルウェーハズ・ジャパン株式会社 シリコンウェーハの製造方法
JP6471710B2 (ja) * 2016-02-24 2019-02-20 信越半導体株式会社 単結晶ウェーハの評価方法
DE102016225138A1 (de) 2016-12-15 2018-06-21 Siltronic Ag Halbleiterscheibe aus einkristallinem Silizium und Verfahren zur Herstellung einer Halbleiterscheibe aus einkristallinem Silizium
US10453703B2 (en) * 2016-12-28 2019-10-22 Sunedison Semiconductor Limited (Uen201334164H) Method of treating silicon wafers to have intrinsic gettering and gate oxide integrity yield
DE102017219255A1 (de) * 2017-10-26 2019-05-02 Siltronic Ag Halbleiterscheibe aus einkristallinem Silizium
SG11202009989YA (en) 2018-04-27 2020-11-27 Globalwafers Co Ltd Light assisted platelet formation facilitating layer transfer from a semiconductor donor substrate
JP6988737B2 (ja) * 2018-08-21 2022-01-05 株式会社Sumco シリコンウェーハの製造方法及びシリコンウェーハ
JP7090295B2 (ja) * 2020-06-24 2022-06-24 グローバルウェーハズ・ジャパン株式会社 シリコンウェーハ、及び、シリコンウェーハの製造方法

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62293727A (ja) * 1986-06-13 1987-12-21 Matsushita Electric Ind Co Ltd 半導体装置の製造方法
JPH06163531A (ja) * 1992-11-27 1994-06-10 Oki Electric Ind Co Ltd 半導体装置における素子分離領域の形成方法
JPH0851144A (ja) * 1994-05-31 1996-02-20 Sgs Thomson Microelectron Inc 半導体集積回路の一部の構成体及びその製造方法
JPH11150112A (ja) * 1997-11-19 1999-06-02 Sony Corp 半導体製造装置および半導体装置の製造方法
JP2000294470A (ja) * 1999-04-09 2000-10-20 Shin Etsu Handotai Co Ltd Ｓｏｉウエーハおよびｓｏｉウエーハの製造方法
JP2001007217A (ja) * 1999-06-17 2001-01-12 Nec Corp 半導体装置の製造方法
JP2001151597A (ja) * 1999-11-26 2001-06-05 Mitsubishi Materials Silicon Corp 点欠陥の凝集体が存在しないシリコンウェーハの製造方法
JP2001308101A (ja) * 2000-04-19 2001-11-02 Mitsubishi Materials Silicon Corp シリコンウェーハの熱処理方法及びシリコンウェーハ

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS541669A (en) 1977-06-06 1979-01-08 Kobe Steel Ltd Electronic integrating wattmeter
JP2758226B2 (ja) 1989-08-29 1998-05-28 株式会社東芝 超音波診断装置
US5401669A (en) * 1993-05-13 1995-03-28 Memc Electronic Materials, Spa Process for the preparation of silicon wafers having controlled distribution of oxygen precipitate nucleation centers
US5543343A (en) * 1993-12-22 1996-08-06 Sgs-Thomson Microelectronics, Inc. Method fabricating an integrated circuit
US5811865A (en) * 1993-12-22 1998-09-22 Stmicroelectronics, Inc. Dielectric in an integrated circuit
JP3085146B2 (ja) * 1995-05-31 2000-09-04 住友金属工業株式会社 シリコン単結晶ウェーハおよびその製造方法
DE69841714D1 (de) 1997-04-09 2010-07-22 Memc Electronic Materials Silicium mit niedriger Fehlerdichte und idealem Sauerstoffniederschlag
JPH1179889A (ja) 1997-07-09 1999-03-23 Shin Etsu Handotai Co Ltd 結晶欠陥が少ないシリコン単結晶の製造方法、製造装置並びにこの方法、装置で製造されたシリコン単結晶とシリコンウエーハ
JP3711199B2 (ja) * 1998-07-07 2005-10-26 信越半導体株式会社 シリコン基板の熱処理方法
JP3534001B2 (ja) 1999-07-30 2004-06-07 信越半導体株式会社 シリコン酸化膜およびシリコン窒化酸化膜の形成方法ならびにシリコンウエーハ
KR100378184B1 (ko) 1999-11-13 2003-03-29 삼성전자주식회사 제어된 결함 분포를 갖는 실리콘 웨이퍼, 그의 제조공정및 단결정 실리콘 잉곳의 제조를 위한 초크랄스키 풀러
US20020179006A1 (en) * 2001-04-20 2002-12-05 Memc Electronic Materials, Inc. Method for the preparation of a semiconductor substrate with a non-uniform distribution of stabilized oxygen precipitates
JP4207577B2 (ja) * 2003-01-17 2009-01-14 信越半導体株式会社 Ｐドープシリコン単結晶の製造方法
KR100398505B1 (ko) * 2003-02-05 2003-09-19 코닉 시스템 주식회사 단결정 실리콘 웨이퍼의 ｃｏｐ 제거방법
JP4806975B2 (ja) * 2005-06-20 2011-11-02 株式会社Ｓｕｍｃｏ シリコン単結晶の育成方法
FR2899380B1 (fr) * 2006-03-31 2008-08-29 Soitec Sa Procede de revelation de defauts cristallins dans un substrat massif.

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62293727A (ja) * 1986-06-13 1987-12-21 Matsushita Electric Ind Co Ltd 半導体装置の製造方法
JPH06163531A (ja) * 1992-11-27 1994-06-10 Oki Electric Ind Co Ltd 半導体装置における素子分離領域の形成方法
JPH0851144A (ja) * 1994-05-31 1996-02-20 Sgs Thomson Microelectron Inc 半導体集積回路の一部の構成体及びその製造方法
JPH11150112A (ja) * 1997-11-19 1999-06-02 Sony Corp 半導体製造装置および半導体装置の製造方法
JP2000294470A (ja) * 1999-04-09 2000-10-20 Shin Etsu Handotai Co Ltd Ｓｏｉウエーハおよびｓｏｉウエーハの製造方法
JP2001007217A (ja) * 1999-06-17 2001-01-12 Nec Corp 半導体装置の製造方法
JP2001151597A (ja) * 1999-11-26 2001-06-05 Mitsubishi Materials Silicon Corp 点欠陥の凝集体が存在しないシリコンウェーハの製造方法
JP2001308101A (ja) * 2000-04-19 2001-11-02 Mitsubishi Materials Silicon Corp シリコンウェーハの熱処理方法及びシリコンウェーハ

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2020213230A1 (ja) * 2019-04-16 2020-10-22 信越半導体株式会社 シリコン単結晶ウェーハの製造方法及びシリコン単結晶ウェーハ
JPWO2020213230A1 (ja) * 2019-04-16 2020-10-22
JP7388434B2 (ja) 2019-04-16 2023-11-29 信越半導体株式会社 シリコン単結晶ウェーハの製造方法及びシリコン単結晶ウェーハ
US11959191B2 (en) 2019-04-16 2024-04-16 Shin-Etsu Handotai Co., Ltd. Method for manufacturing silicon single crystal wafer and silicon single crystal wafer

Also Published As

Publication number Publication date
KR101416094B1 (ko) 2014-07-08
DE112008000486T5 (de) 2010-01-21
TWI402919B (zh) 2013-07-21
TW200845223A (en) 2008-11-16
CN101622381A (zh) 2010-01-06
JP5167654B2 (ja) 2013-03-21
DE112008000486B4 (de) 2017-03-16
US8187954B2 (en) 2012-05-29
KR20090116748A (ko) 2009-11-11
US20100105191A1 (en) 2010-04-29
JP2008207991A (ja) 2008-09-11

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