DE3588247D1 - Dynamischer Halbleiterspeicher mit einer statischen Datenspeicherzelle - Google Patents

Dynamischer Halbleiterspeicher mit einer statischen Datenspeicherzelle

Info

Publication number
DE3588247D1
DE3588247D1 DE3588247T DE3588247T DE3588247D1 DE 3588247 D1 DE3588247 D1 DE 3588247D1 DE 3588247 T DE3588247 T DE 3588247T DE 3588247 T DE3588247 T DE 3588247T DE 3588247 D1 DE3588247 D1 DE 3588247D1
Authority
DE
Germany
Prior art keywords
data storage
semiconductor memory
storage cell
static data
dynamic semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE3588247T
Other languages
English (en)
Other versions
DE3588247T2 (de
Inventor
Koji Sakui
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Application granted granted Critical
Publication of DE3588247D1 publication Critical patent/DE3588247D1/de
Publication of DE3588247T2 publication Critical patent/DE3588247T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/106—Data output latches
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/005—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor comprising combined but independently operative RAM-ROM, RAM-PROM, RAM-EPROM cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1087—Data input latches

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Databases & Information Systems (AREA)
  • Dram (AREA)
DE3588247T 1984-12-13 1985-12-13 Dynamischer Halbleiterspeicher mit einer statischen Datenspeicherzelle Expired - Lifetime DE3588247T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP59263304A JPH0793009B2 (ja) 1984-12-13 1984-12-13 半導体記憶装置
JP26330484 1984-12-13

Publications (2)

Publication Number Publication Date
DE3588247D1 true DE3588247D1 (de) 2003-08-14
DE3588247T2 DE3588247T2 (de) 2004-04-22

Family

ID=17387614

Family Applications (2)

Application Number Title Priority Date Filing Date
DE3588042T Expired - Fee Related DE3588042T2 (de) 1984-12-13 1985-12-13 Dynamischer Halbleiterspeicher mit einer statischen Datenspeicherzelle.
DE3588247T Expired - Lifetime DE3588247T2 (de) 1984-12-13 1985-12-13 Dynamischer Halbleiterspeicher mit einer statischen Datenspeicherzelle

Family Applications Before (1)

Application Number Title Priority Date Filing Date
DE3588042T Expired - Fee Related DE3588042T2 (de) 1984-12-13 1985-12-13 Dynamischer Halbleiterspeicher mit einer statischen Datenspeicherzelle.

Country Status (5)

Country Link
US (1) US4758987A (de)
EP (2) EP0640977B1 (de)
JP (1) JPH0793009B2 (de)
KR (1) KR910004188B1 (de)
DE (2) DE3588042T2 (de)

Families Citing this family (45)

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JPS6240698A (ja) * 1985-08-16 1987-02-21 Fujitsu Ltd 半導体記憶装置
JPS62146491A (ja) * 1985-12-20 1987-06-30 Sanyo Electric Co Ltd 半導体メモリ
JPS62245593A (ja) * 1986-04-17 1987-10-26 Sanyo Electric Co Ltd ダイナミツクメモリのデ−タ書き込み方法
DE3884859T2 (de) * 1987-06-04 1994-02-03 Nec Corp Dynamische Speicherschaltung mit einem Abfühlschema.
US4875196A (en) * 1987-09-08 1989-10-17 Sharp Microelectronic Technology, Inc. Method of operating data buffer apparatus
JP2713929B2 (ja) * 1987-11-25 1998-02-16 株式会社東芝 半導体記憶装置
JPH01138680A (ja) * 1987-11-25 1989-05-31 Toshiba Corp 半導体記憶装置
US4943944A (en) * 1987-11-25 1990-07-24 Kabushiki Kaisha Toshiba Semiconductor memory using dynamic ram cells
US5173878A (en) * 1987-11-25 1992-12-22 Kabushiki Kaisha Toshiba Semiconductor memory including address multiplexing circuitry for changing the order of supplying row and column addresses between read and write cycles
JP2599747B2 (ja) * 1988-03-10 1997-04-16 沖電気工業株式会社 半導体メモリの制御方法
JP2633645B2 (ja) * 1988-09-13 1997-07-23 株式会社東芝 半導体メモリ装置
JPH07101554B2 (ja) * 1988-11-29 1995-11-01 三菱電機株式会社 半導体記憶装置およびそのデータ転送方法
JP2860403B2 (ja) * 1988-12-22 1999-02-24 リチャード・チャールズ・フォス ダイナミック型半導体記憶装置
JP2646032B2 (ja) * 1989-10-14 1997-08-25 三菱電機株式会社 Ｌｉｆｏ方式の半導体記憶装置およびその制御方法
JPH03252988A (ja) * 1990-03-02 1991-11-12 Nec Corp ダイナミック型半導体メモリ
JP2662822B2 (ja) * 1990-03-20 1997-10-15 三菱電機株式会社 半導体記憶装置
JPH0834257B2 (ja) * 1990-04-20 1996-03-29 株式会社東芝 半導体メモリセル
JPH0457282A (ja) * 1990-06-22 1992-02-25 Mitsubishi Electric Corp 半導体メモリ装置
JPH07122989B2 (ja) * 1990-06-27 1995-12-25 株式会社東芝 半導体記憶装置
JP2604276B2 (ja) * 1990-11-20 1997-04-30 三菱電機株式会社 半導体記憶装置
EP0492776B1 (de) * 1990-12-25 1998-05-13 Mitsubishi Denki Kabushiki Kaisha Halbleiterspeichervorrichtung mit einem grossen Speicher und einem Hochgeschwindigkeitsspeicher
JPH04255989A (ja) 1991-02-07 1992-09-10 Mitsubishi Electric Corp 半導体記憶装置および内部電圧発生方法
JP2564046B2 (ja) * 1991-02-13 1996-12-18 株式会社東芝 半導体記憶装置
JP2660111B2 (ja) * 1991-02-13 1997-10-08 株式会社東芝 半導体メモリセル
DE69222793T2 (de) * 1991-03-14 1998-03-12 Toshiba Kawasaki Kk Halbleiterspeicheranordnung
JP3181311B2 (ja) * 1991-05-29 2001-07-03 株式会社東芝 半導体記憶装置
US5297091A (en) * 1991-10-31 1994-03-22 International Business Machines Corporation Early row address strobe (RAS) precharge
JP3464803B2 (ja) * 1991-11-27 2003-11-10 株式会社東芝 半導体メモリセル
US5291444A (en) * 1991-12-23 1994-03-01 Texas Instruments Incorporated Combination DRAM and SRAM memory array
US5291437A (en) * 1992-06-25 1994-03-01 Texas Instruments Incorporated Shared dummy cell
US5617093A (en) * 1994-09-30 1997-04-01 Imp, Inc. Switched capacitor analog circuits with low input capacitance
US5836007A (en) * 1995-09-14 1998-11-10 International Business Machines Corporation Methods and systems for improving memory component size and access speed including splitting bit lines and alternate pre-charge/access cycles
US6167486A (en) 1996-11-18 2000-12-26 Nec Electronics, Inc. Parallel access virtual channel memory system with cacheable channels
US5936874A (en) * 1997-06-19 1999-08-10 Micron Technology, Inc. High density semiconductor memory and method of making
US5978307A (en) * 1998-05-21 1999-11-02 Integrated Device Technology, Inc. Integrated circuit memory devices having partitioned multi-port memory arrays therein for increasing data bandwidth and methods of operating same
US5982700A (en) * 1998-05-21 1999-11-09 Integrated Device Technology, Inc. Buffer memory arrays having nonlinear columns for providing parallel data access capability and methods of operating same
US5999478A (en) * 1998-05-21 1999-12-07 Integrated Device Technology, Inc. Highly integrated tri-port memory buffers having fast fall-through capability and methods of operating same
US6216205B1 (en) 1998-05-21 2001-04-10 Integrated Device Technology, Inc. Methods of controlling memory buffers having tri-port cache arrays therein
JP2000011640A (ja) * 1998-06-23 2000-01-14 Nec Corp 半導体記憶装置
US6072746A (en) 1998-08-14 2000-06-06 International Business Machines Corporation Self-timed address decoder for register file and compare circuit of a multi-port CAM
JP2000293984A (ja) 1999-04-01 2000-10-20 Toshiba Microelectronics Corp 半導体記憶装置
US6708254B2 (en) 1999-11-10 2004-03-16 Nec Electronics America, Inc. Parallel access virtual channel memory system
KR100368133B1 (ko) 2000-03-28 2003-01-15 한국과학기술원 메모리 셀 정보 저장 방법
US6546461B1 (en) 2000-11-22 2003-04-08 Integrated Device Technology, Inc. Multi-port cache memory devices and FIFO memory devices having multi-port cache memory devices therein
US7042792B2 (en) * 2004-01-14 2006-05-09 Integrated Device Technology, Inc. Multi-port memory cells for use in FIFO applications that support data transfers between cache and supplemental memory arrays

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3646525A (en) * 1970-01-12 1972-02-29 Ibm Data regeneration scheme without using memory sense amplifiers
JPS5032090B2 (de) * 1972-06-20 1975-10-17
US4004284A (en) * 1975-03-05 1977-01-18 Teletype Corporation Binary voltage-differential sensing circuits, and sense/refresh amplifier circuits for random-access memories
JPS51113545A (en) * 1975-03-31 1976-10-06 Hitachi Ltd Memory
US4508980A (en) * 1976-11-11 1985-04-02 Signetics Corporation Sense and refresh amplifier circuit
US4106109A (en) * 1977-02-01 1978-08-08 Ncr Corporation Random access memory system providing high-speed digital data output
US4354255A (en) * 1980-04-29 1982-10-12 Rca Corporation Random access memory with volatile and non-volatile storage
US4351034A (en) * 1980-10-10 1982-09-21 Inmos Corporation Folded bit line-shared sense amplifiers
US4363110A (en) * 1980-12-22 1982-12-07 International Business Machines Corp. Non-volatile dynamic RAM cell
JPS57167186A (en) * 1981-04-08 1982-10-14 Nec Corp Memory circuit
JPS5940397A (ja) * 1982-08-31 1984-03-06 Toshiba Corp デ−タ読み出し回路
JPS5960794A (ja) * 1982-09-29 1984-04-06 Fujitsu Ltd ダイナミツク型半導体記憶装置
JPS59119591A (ja) * 1982-12-27 1984-07-10 Toshiba Corp 半導体メモリ装置
JPH069114B2 (ja) * 1983-06-24 1994-02-02 株式会社東芝 半導体メモリ
JPS60209996A (ja) * 1984-03-31 1985-10-22 Toshiba Corp 半導体記憶装置
JPS6190396A (ja) * 1984-10-09 1986-05-08 Nec Corp ダイナミツクｍｏｓメモリ回路

Also Published As

Publication number Publication date
EP0185529A2 (de) 1986-06-25
DE3588042T2 (de) 1995-12-21
KR910004188B1 (ko) 1991-06-24
KR860005370A (ko) 1986-07-21
DE3588247T2 (de) 2004-04-22
EP0640977B1 (de) 2003-07-09
EP0185529B1 (de) 1995-07-19
EP0185529A3 (en) 1988-08-17
JPS61142592A (ja) 1986-06-30
JPH0793009B2 (ja) 1995-10-09
DE3588042D1 (de) 1995-08-24
EP0640977A1 (de) 1995-03-01
US4758987A (en) 1988-07-19

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Legal Events

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8364 No opposition during term of opposition