DE3578253D1 - Halbleiterspeicher mit einer hohen datenlesegeschwindigkeit und einem hohen stoerabstand. - Google Patents

Halbleiterspeicher mit einer hohen datenlesegeschwindigkeit und einem hohen stoerabstand.

Info

Publication number
DE3578253D1
DE3578253D1 DE8585116577T DE3578253T DE3578253D1 DE 3578253 D1 DE3578253 D1 DE 3578253D1 DE 8585116577 T DE8585116577 T DE 8585116577T DE 3578253 T DE3578253 T DE 3578253T DE 3578253 D1 DE3578253 D1 DE 3578253D1
Authority
DE
Germany
Prior art keywords
semiconductor memory
data reading
reading speed
interference
high data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE8585116577T
Other languages
English (en)
Inventor
Yasuo Kobayashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Electronics Corp
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Application granted granted Critical
Publication of DE3578253D1 publication Critical patent/DE3578253D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/18—Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Static Random-Access Memory (AREA)
  • Dram (AREA)
DE8585116577T 1984-12-27 1985-12-27 Halbleiterspeicher mit einer hohen datenlesegeschwindigkeit und einem hohen stoerabstand. Expired - Lifetime DE3578253D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP27735684 1984-12-27

Publications (1)

Publication Number Publication Date
DE3578253D1 true DE3578253D1 (de) 1990-07-19

Family

ID=17582381

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8585116577T Expired - Lifetime DE3578253D1 (de) 1984-12-27 1985-12-27 Halbleiterspeicher mit einer hohen datenlesegeschwindigkeit und einem hohen stoerabstand.

Country Status (4)

Country Link
US (1) US4766572A (de)
EP (1) EP0186906B1 (de)
JP (1) JPH0650599B2 (de)
DE (1) DE3578253D1 (de)

Families Citing this family (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0831275B2 (ja) * 1986-09-09 1996-03-27 日本電気株式会社 メモリ回路
US4947374A (en) * 1987-05-12 1990-08-07 Mitsubishi Denki Kabushiki Kaisha Semiconductor memeory device in which writing is inhibited in address skew period and controlling method thereof
JP2569554B2 (ja) * 1987-05-13 1997-01-08 三菱電機株式会社 ダイナミツクｒａｍ
JP2585602B2 (ja) * 1987-06-10 1997-02-26 株式会社日立製作所 半導体記憶装置
JP2530012B2 (ja) * 1988-11-18 1996-09-04 株式会社東芝 半導体集積回路
JPH07118195B2 (ja) * 1988-10-07 1995-12-18 株式会社東芝 半導体集積回路
NL8800872A (nl) * 1988-04-06 1989-11-01 Philips Nv Geintegreerde schakeling.
US5327392A (en) * 1989-01-13 1994-07-05 Kabushiki Kaisha Toshiba Semiconductor integrated circuit capable of preventing occurrence of erroneous operation due to noise
JPH0778989B2 (ja) * 1989-06-21 1995-08-23 株式会社東芝 半導体メモリ装置
EP0405411B1 (de) * 1989-06-26 1995-11-15 Nec Corporation Halbleiterspeicher mit einem verbesserten Datenleseschema
US5146427A (en) * 1989-08-30 1992-09-08 Hitachi Ltd. High speed semiconductor memory having a direct-bypass signal path
KR100240523B1 (ko) * 1989-08-30 2000-01-15 미다 가쓰시게 반도체 집적 회로 장치
JP2534782B2 (ja) * 1989-11-10 1996-09-18 株式会社東芝 半導体装置
US5625593A (en) * 1990-03-28 1997-04-29 Mitsubishi Denki Kabushiki Kaisha Memory card circuit with separate buffer chips
JP2519580B2 (ja) * 1990-06-19 1996-07-31 三菱電機株式会社 半導体集積回路
JPH0799630B2 (ja) * 1990-09-11 1995-10-25 株式会社東芝 スタティック型半導体記憶装置
US5305277A (en) * 1991-04-24 1994-04-19 International Business Machines Corporation Data processing apparatus having address decoder supporting wide range of operational frequencies
JPH05144273A (ja) * 1991-11-18 1993-06-11 Mitsubishi Electric Corp 半導体集積回路装置
US6026052A (en) 1994-05-03 2000-02-15 Fujitsu Limited Programmable semiconductor memory device
US5661694A (en) * 1993-05-14 1997-08-26 Fujitsu Limited Programmable semiconductor memory device
US5592425A (en) * 1995-12-20 1997-01-07 Intel Corporation Method and apparatus for testing a memory where data is passed through the memory for comparison with data read from the memory
DE69631242D1 (de) * 1996-04-29 2004-02-05 St Microelectronics Srl Speicherarchitektur für flexibele Leseverwaltung, insbesondere für nichtflüchtige Speicher, mit Rauschunempfindlichkeitsmerkmalen, mit Anlageleistungsanpassung und mit optimiertem Durchfluss
KR100230747B1 (ko) * 1996-11-22 1999-11-15 김영환 반도체 메모리장치의 저전력 감지증폭기(Low power sense amplifier in a semiconductor device)
KR100226254B1 (ko) * 1996-12-28 1999-10-15 김영환 반도체 메모리소자의 감지증폭기 인에이블신호 발생회로
US5917768A (en) * 1997-04-24 1999-06-29 Sgs-Thomson Microelectronics S.R.L. Memory architecture for flexible reading management, particularly for non-volatile memories, having noise-immunity features, matching device performance, and having optimized throughout
JPH11134224A (ja) * 1997-10-29 1999-05-21 Fujitsu Ltd 信号観測方法及び信号観測装置
US6262920B1 (en) * 1999-08-25 2001-07-17 Micron Technology, Inc. Program latch with charge sharing immunity

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3428951A (en) * 1963-02-28 1969-02-18 Ampex Memory addressing apparatus
US4060794A (en) * 1976-03-31 1977-11-29 Honeywell Information Systems Inc. Apparatus and method for generating timing signals for latched type memories
JPS5423337A (en) * 1977-07-22 1979-02-21 Mitsubishi Electric Corp Semiconductor memory unit
JPS6057156B2 (ja) * 1978-05-24 1985-12-13 株式会社日立製作所 半導体メモリ装置
FR2443723A1 (fr) * 1978-12-06 1980-07-04 Cii Honeywell Bull Dispositif de reduction du temps d'acces aux informations contenues dans une memoire d'un systeme de traitement de l'information
GB2084361B (en) * 1980-09-19 1984-11-21 Sony Corp Random access memory arrangements
JPS58169383A (ja) * 1982-03-30 1983-10-05 Fujitsu Ltd 半導体記憶装置
JPS5952492A (ja) * 1982-09-17 1984-03-27 Fujitsu Ltd スタテイツク型半導体記憶装置
EP0125699A3 (de) * 1983-05-17 1986-10-08 Kabushiki Kaisha Toshiba Datenausgabeanordnung für einen dynamischen Speicher
US4616341A (en) * 1983-06-30 1986-10-07 International Business Machines Corporation Directory memory system having simultaneous write and comparison data bypass capabilities

Also Published As

Publication number Publication date
US4766572A (en) 1988-08-23
EP0186906A3 (en) 1987-09-02
EP0186906B1 (de) 1990-06-13
JPS61267993A (ja) 1986-11-27
JPH0650599B2 (ja) 1994-06-29
EP0186906A2 (de) 1986-07-09

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: NEC CORP., TOKIO/TOKYO, JP

Owner name: NEC ELECTRONICS CORP., KAWASAKI, KANAGAWA, JP