DE3883865D1 - Halbleiterspeicheranordnung mit einem Register. - Google Patents

Halbleiterspeicheranordnung mit einem Register.

Info

Publication number
DE3883865D1
DE3883865D1 DE88110117T DE3883865T DE3883865D1 DE 3883865 D1 DE3883865 D1 DE 3883865D1 DE 88110117 T DE88110117 T DE 88110117T DE 3883865 T DE3883865 T DE 3883865T DE 3883865 D1 DE3883865 D1 DE 3883865D1
Authority
DE
Germany
Prior art keywords
register
memory device
semiconductor memory
semiconductor
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE88110117T
Other languages
English (en)
Other versions
DE3883865T2 (de
Inventor
Fumio Baba
Kazuya Kobayashi
Seiji Enomoto
Hiroaki Ogawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu VLSI Ltd
Fujitsu Ltd
Original Assignee
Fujitsu VLSI Ltd
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu VLSI Ltd, Fujitsu Ltd filed Critical Fujitsu VLSI Ltd
Publication of DE3883865D1 publication Critical patent/DE3883865D1/de
Application granted granted Critical
Publication of DE3883865T2 publication Critical patent/DE3883865T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1093—Input synchronization
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1087—Data input latches
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1096—Write circuits, e.g. I/O line write drivers
DE88110117T 1987-06-25 1988-06-24 Halbleiterspeicheranordnung mit einem Register. Expired - Fee Related DE3883865T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62158575A JPH0760594B2 (ja) 1987-06-25 1987-06-25 半導体記憶装置

Publications (2)

Publication Number Publication Date
DE3883865D1 true DE3883865D1 (de) 1993-10-14
DE3883865T2 DE3883865T2 (de) 1994-04-21

Family

ID=15674684

Family Applications (1)

Application Number Title Priority Date Filing Date
DE88110117T Expired - Fee Related DE3883865T2 (de) 1987-06-25 1988-06-24 Halbleiterspeicheranordnung mit einem Register.

Country Status (5)

Country Link
US (1) US4899310A (de)
EP (1) EP0296615B1 (de)
JP (1) JPH0760594B2 (de)
KR (1) KR910003382B1 (de)
DE (1) DE3883865T2 (de)

Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2632093B1 (fr) * 1988-05-25 1990-08-10 Bull Sa Memoire modulaire
JPH07101554B2 (ja) * 1988-11-29 1995-11-01 三菱電機株式会社 半導体記憶装置およびそのデータ転送方法
KR930007185B1 (ko) * 1989-01-13 1993-07-31 가부시키가이샤 도시바 레지스터뱅크회로
DE69023258T2 (de) * 1989-03-15 1996-05-15 Matsushita Electronics Corp Halbleiter-Speichereinrichtung.
US5257235A (en) * 1989-04-25 1993-10-26 Kabushiki Kaisha Toshiba Semiconductor memory device having serial access mode
JPH07109703B2 (ja) * 1989-11-15 1995-11-22 株式会社東芝 半導体メモリ装置
KR920003269B1 (ko) * 1990-05-04 1992-04-27 삼성전자 주식회사 듀얼 포트 메모리소자의 모우드 전환방법
JP2596208B2 (ja) * 1990-10-19 1997-04-02 日本電気株式会社 メモリ装置
JP2680475B2 (ja) * 1990-11-30 1997-11-19 株式会社東芝 半導体メモリ装置
JP2549209B2 (ja) * 1991-01-23 1996-10-30 株式会社東芝 半導体記憶装置
US5263003A (en) * 1991-11-12 1993-11-16 Allen-Bradley Company, Inc. Flash memory circuit and method of operation
JPH05342855A (ja) * 1992-06-04 1993-12-24 Nec Corp 半導体メモリ回路
JP3594626B2 (ja) * 1993-03-04 2004-12-02 株式会社ルネサステクノロジ 不揮発性メモリ装置
WO1994029871A1 (en) * 1993-06-14 1994-12-22 Rambus, Inc. Method and apparatus for writing to memory components
JP3435783B2 (ja) * 1994-03-17 2003-08-11 株式会社日立製作所 複数組のデータバッファを備える記憶素子及び記憶素子を用いたデータ処理システム
US5598569A (en) * 1994-10-17 1997-01-28 Motorola Inc. Data processor having operating modes selected by at least one mask option bit and method therefor
JP3577119B2 (ja) 1994-11-01 2004-10-13 株式会社ルネサステクノロジ 半導体記憶装置
US5892982A (en) * 1995-11-29 1999-04-06 Matsushita Electric Industrial Co., Ltd. External expansion bus interface circuit for connecting a micro control unit, and a digital recording and reproducing apparatus incorporating said interface circuit
DE69625327D1 (de) 1996-03-20 2003-01-23 St Microelectronics Srl Zeitzuteilender interner Bus, insbesondere für nichtflüchtige Speicher
US5983314A (en) * 1997-07-22 1999-11-09 Micron Technology, Inc. Output buffer having inherently precise data masking
US6940496B1 (en) * 1998-06-04 2005-09-06 Silicon, Image, Inc. Display module driving system and digital to analog converter for driving display
JP2000029778A (ja) * 1998-07-14 2000-01-28 Hitachi Ltd 記憶素子
JP2001084791A (ja) * 1999-07-12 2001-03-30 Mitsubishi Electric Corp 半導体記憶装置

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57150190A (en) * 1981-02-27 1982-09-16 Hitachi Ltd Monolithic storage device
JPS60140924A (ja) * 1983-12-27 1985-07-25 Nec Corp 半導体回路
US4747081A (en) * 1983-12-30 1988-05-24 Texas Instruments Incorporated Video display system using memory with parallel and serial access employing serial shift registers selected by column address
US4745577A (en) * 1984-11-20 1988-05-17 Fujitsu Limited Semiconductor memory device with shift registers for high speed reading and writing
US4683555A (en) * 1985-01-22 1987-07-28 Texas Instruments Incorporated Serial accessed semiconductor memory with reconfigureable shift registers
JPS61239491A (ja) * 1985-04-13 1986-10-24 Fujitsu Ltd 電子装置
US4740923A (en) * 1985-11-19 1988-04-26 Hitachi, Ltd Memory circuit and method of controlling the same
US4758988A (en) * 1985-12-12 1988-07-19 Motorola, Inc. Dual array EEPROM for high endurance capability
US4807189A (en) * 1987-08-05 1989-02-21 Texas Instruments Incorporated Read/write memory having a multiple column select mode

Also Published As

Publication number Publication date
US4899310A (en) 1990-02-06
KR910003382B1 (ko) 1991-05-28
EP0296615A2 (de) 1988-12-28
EP0296615A3 (en) 1990-11-07
JPS643897A (en) 1989-01-09
KR890001085A (ko) 1989-03-18
JPH0760594B2 (ja) 1995-06-28
EP0296615B1 (de) 1993-09-08
DE3883865T2 (de) 1994-04-21

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee