DE3280349D1 - Halbleiterspeicheranlage. - Google Patents
Halbleiterspeicheranlage.Info
- Publication number
- DE3280349D1 DE3280349D1 DE8282302774T DE3280349T DE3280349D1 DE 3280349 D1 DE3280349 D1 DE 3280349D1 DE 8282302774 T DE8282302774 T DE 8282302774T DE 3280349 T DE3280349 T DE 3280349T DE 3280349 D1 DE3280349 D1 DE 3280349D1
- Authority
- DE
- Germany
- Prior art keywords
- storage system
- semiconductor storage
- semiconductor
- storage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 title 1
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/408—Address circuits
- G11C11/4087—Address decoders, e.g. bit - or word line decoders; Multiple line decoders
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4097—Bit-line organisation, e.g. bit-line layout, folded bit lines
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
- G11C5/063—Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Databases & Information Systems (AREA)
- Dram (AREA)
- Static Random-Access Memory (AREA)
- Semiconductor Memories (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56081042A JPS57198592A (en) | 1981-05-29 | 1981-05-29 | Semiconductor memory device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| DE3280349D1 true DE3280349D1 (de) | 1991-09-26 |
Family
ID=13735376
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| DE8282302774T Expired - Lifetime DE3280349D1 (de) | 1981-05-29 | 1982-05-28 | Halbleiterspeicheranlage. |
Country Status (5)
| Country | Link |
|---|---|
| US (4) | US4675845A (enExample) |
| EP (1) | EP0068645B1 (enExample) |
| JP (1) | JPS57198592A (enExample) |
| CA (1) | CA1199724A (enExample) |
| DE (1) | DE3280349D1 (enExample) |
Families Citing this family (63)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57198592A (en) * | 1981-05-29 | 1982-12-06 | Hitachi Ltd | Semiconductor memory device |
| JPS6054471A (ja) * | 1983-09-05 | 1985-03-28 | Hitachi Ltd | 半導体メモリ |
| JPS59231852A (ja) * | 1983-06-15 | 1984-12-26 | Hitachi Ltd | 半導体装置 |
| JPH073862B2 (ja) * | 1983-07-27 | 1995-01-18 | 株式会社日立製作所 | 半導体記憶装置 |
| JPS60224333A (ja) * | 1984-04-23 | 1985-11-08 | Seiko Epson Corp | パラレル・シリアル変換回路 |
| EP0166642A3 (en) * | 1984-05-30 | 1989-02-22 | Fujitsu Limited | Block-divided semiconductor memory device having divided bit lines |
| EP0169460B1 (en) * | 1984-07-26 | 1991-05-15 | Texas Instruments Incorporated | Dynamic memory array with segmented and quasi-folded bit lines |
| US4908797A (en) * | 1984-07-26 | 1990-03-13 | Texas Instruments Incorporated | Dynamic memory array with quasi-folded bit lines |
| EP0180054A3 (en) * | 1984-10-31 | 1988-05-11 | Texas Instruments Incorporated | Dual ended adaptive folded bitline scheme |
| JPS61110459A (ja) * | 1984-11-02 | 1986-05-28 | Nippon Telegr & Teleph Corp <Ntt> | 半導体メモリ |
| US4730280A (en) * | 1984-11-20 | 1988-03-08 | Fujitsu Limited | Semiconductor memory device having sense amplifiers with different driving abilities |
| EP0523759B1 (en) * | 1985-01-22 | 1998-05-20 | Texas Instruments Incorporated | Serial accessed semiconductor memory |
| JPS61227289A (ja) * | 1985-03-30 | 1986-10-09 | Fujitsu Ltd | 半導体記憶装置 |
| JPS6299989A (ja) * | 1985-10-25 | 1987-05-09 | Hitachi Ltd | 半導体メモリ |
| JPS62169471A (ja) * | 1986-01-22 | 1987-07-25 | Hitachi Ltd | 半導体集積回路装置 |
| JPH073856B2 (ja) * | 1986-02-18 | 1995-01-18 | 日本電気株式会社 | 半導体記憶装置 |
| JPS62153700U (enExample) * | 1986-03-20 | 1987-09-29 | ||
| US4907201A (en) * | 1986-05-07 | 1990-03-06 | Mitsubishi Denki Kabushiki Kaisha | MOS transistor circuit |
| JPH0625015Y2 (ja) * | 1986-06-13 | 1994-06-29 | シャープ株式会社 | 半導体装置 |
| JPS63153792A (ja) * | 1986-12-17 | 1988-06-27 | Sharp Corp | 半導体メモリ装置 |
| JPS63183691A (ja) * | 1987-01-26 | 1988-07-29 | Mitsubishi Electric Corp | 半導体記憶装置 |
| JPH0740431B2 (ja) * | 1987-01-30 | 1995-05-01 | 三菱電機株式会社 | 半導体記憶装置 |
| JPS63225991A (ja) * | 1987-03-16 | 1988-09-20 | Hitachi Ltd | 半導体記憶装置 |
| US4797858A (en) * | 1987-03-30 | 1989-01-10 | Motorola, Inc. | Semiconductor memory with divided word lines and shared sense amplifiers |
| US5249159A (en) * | 1987-05-27 | 1993-09-28 | Hitachi, Ltd. | Semiconductor memory |
| US5204842A (en) * | 1987-08-05 | 1993-04-20 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor memory with memory unit comprising a plurality of memory blocks |
| US5018101A (en) * | 1987-09-16 | 1991-05-21 | Hitachi, Ltd. | Semiconductor memory |
| US4956811A (en) * | 1987-09-16 | 1990-09-11 | Hitachi, Ltd. | Semiconductor memory |
| JP2618938B2 (ja) * | 1987-11-25 | 1997-06-11 | 株式会社東芝 | 半導体記憶装置 |
| JPH01184787A (ja) * | 1988-01-19 | 1989-07-24 | Toshiba Corp | 半導体メモリ |
| JP2547615B2 (ja) * | 1988-06-16 | 1996-10-23 | 三菱電機株式会社 | 読出専用半導体記憶装置および半導体記憶装置 |
| JP2633645B2 (ja) * | 1988-09-13 | 1997-07-23 | 株式会社東芝 | 半導体メモリ装置 |
| US5617365A (en) | 1988-10-07 | 1997-04-01 | Hitachi, Ltd. | Semiconductor device having redundancy circuit |
| US4969123A (en) * | 1988-10-31 | 1990-11-06 | Texas Instruments Incorporated | Distributed signal transmission to an integrated circuit array |
| DE3937068C2 (de) * | 1988-11-07 | 1994-10-06 | Toshiba Kawasaki Kk | Dynamische Halbleiterspeicheranordnung |
| JPH07101554B2 (ja) * | 1988-11-29 | 1995-11-01 | 三菱電機株式会社 | 半導体記憶装置およびそのデータ転送方法 |
| JPH02156497A (ja) * | 1988-12-07 | 1990-06-15 | Mitsubishi Electric Corp | 半導体記憶装置 |
| JP2761515B2 (ja) * | 1989-03-08 | 1998-06-04 | 株式会社日立製作所 | 半導体記憶装置 |
| JPH0814985B2 (ja) * | 1989-06-06 | 1996-02-14 | 富士通株式会社 | 半導体記憶装置 |
| JP2953708B2 (ja) * | 1989-07-31 | 1999-09-27 | 株式会社東芝 | ダイナミック型半導体記憶装置 |
| EP0450159A3 (en) * | 1990-03-28 | 1992-06-03 | Siemens Aktiengesellschaft | Dram cell field architecture with superposed bitline switches and bitlines |
| GB2246001B (en) * | 1990-04-11 | 1994-06-15 | Digital Equipment Corp | Array architecture for high speed cache memory |
| JP2982920B2 (ja) * | 1990-07-10 | 1999-11-29 | 三菱電機株式会社 | 半導体記憶装置 |
| JP2624569B2 (ja) * | 1990-10-22 | 1997-06-25 | シャープ株式会社 | 読出し専用メモリ |
| JP2664810B2 (ja) * | 1991-03-07 | 1997-10-22 | 株式会社東芝 | メモリセルアレイ分割型半導体記憶装置 |
| JP3226579B2 (ja) * | 1991-12-24 | 2001-11-05 | 沖電気工業株式会社 | 半導体記憶装置 |
| JP2775552B2 (ja) * | 1991-12-26 | 1998-07-16 | 三菱電機株式会社 | 半導体記憶装置 |
| KR950009234B1 (ko) * | 1992-02-19 | 1995-08-18 | 삼성전자주식회사 | 반도체 메모리장치의 비트라인 분리클럭 발생장치 |
| US5475642A (en) * | 1992-06-23 | 1995-12-12 | Taylor; David L. | Dynamic random access memory with bit line preamp/driver |
| KR970004460B1 (ko) * | 1992-06-30 | 1997-03-27 | 니뽄 덴끼 가부시끼가이샤 | 반도체 메모리 회로 |
| JP3279681B2 (ja) * | 1992-09-03 | 2002-04-30 | 株式会社日立製作所 | 半導体装置 |
| US5325336A (en) * | 1992-09-10 | 1994-06-28 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor memory device having power line arranged in a meshed shape |
| JP3364810B2 (ja) * | 1993-09-14 | 2003-01-08 | 三菱電機株式会社 | 半導体記憶装置 |
| JPH07272480A (ja) * | 1994-03-30 | 1995-10-20 | Mitsubishi Electric Corp | 半導体記憶装置 |
| JP3413298B2 (ja) * | 1994-12-02 | 2003-06-03 | 三菱電機株式会社 | 半導体記憶装置 |
| US5719890A (en) * | 1995-06-01 | 1998-02-17 | Micron Technology, Inc. | Method and circuit for transferring data with dynamic parity generation and checking scheme in multi-port DRAM |
| US5561630A (en) * | 1995-09-28 | 1996-10-01 | International Business Machines Coporation | Data sense circuit for dynamic random access memories |
| JP2879772B2 (ja) * | 1996-04-25 | 1999-04-05 | 三菱電機株式会社 | 半導体記憶装置 |
| US6487207B1 (en) | 1997-02-26 | 2002-11-26 | Micron Technology, Inc. | Shared buffer memory architecture for asynchronous transfer mode switching and multiplexing technology |
| US5892703A (en) * | 1997-06-13 | 1999-04-06 | Micron Technology, Inc, | Memory architecture and decoder addressing |
| JP3703655B2 (ja) * | 1999-08-11 | 2005-10-05 | 株式会社東芝 | タイミング信号発生回路 |
| US6563743B2 (en) * | 2000-11-27 | 2003-05-13 | Hitachi, Ltd. | Semiconductor device having dummy cells and semiconductor device having dummy cells for redundancy |
| KR100769796B1 (ko) * | 2006-05-12 | 2007-10-25 | 주식회사 하이닉스반도체 | 저전압용 롬 |
Family Cites Families (18)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3789371A (en) * | 1972-11-20 | 1974-01-29 | Lockheed Electronics Co | Mosfet memory cell |
| US3848237A (en) * | 1973-02-20 | 1974-11-12 | Advanced Memory Syst | High speed mos random access read/write memory device |
| US3942164A (en) * | 1975-01-30 | 1976-03-02 | Semi, Inc. | Sense line coupling reduction system |
| JPS596067B2 (ja) * | 1975-03-14 | 1984-02-08 | 株式会社日立製作所 | 半導体メモリ |
| JPS596069B2 (ja) * | 1975-12-10 | 1984-02-08 | 株式会社日立製作所 | ハンドウタイメモリ |
| US4056811A (en) * | 1976-02-13 | 1977-11-01 | Baker Roger T | Circuit for the improvement of semiconductor memories |
| DE2647394C2 (de) * | 1976-10-20 | 1978-11-16 | Siemens Ag, 1000 Berlin Und 8000 Muenchen | MOS-Halbleiterspeicherbaustein |
| DE2740113A1 (de) * | 1977-09-06 | 1979-03-15 | Siemens Ag | Monolithisch integrierter halbleiterspeicher |
| JPS6044750B2 (ja) * | 1978-01-24 | 1985-10-05 | 日本電気株式会社 | 集積化メモリ |
| DE2919166C2 (de) * | 1978-05-12 | 1986-01-02 | Nippon Electric Co., Ltd., Tokio/Tokyo | Speichervorrichtung |
| JPS5575899U (enExample) * | 1978-11-20 | 1980-05-24 | ||
| IT1224062B (it) * | 1979-09-28 | 1990-09-26 | Ates Componenti Elettron | Metodo di programmazione per una memoria a semiconduttore non volatile elettricamente alterabile |
| JPS5693178A (en) * | 1979-12-26 | 1981-07-28 | Toshiba Corp | Semiconductor memory device |
| JPS57100689A (en) * | 1980-12-15 | 1982-06-22 | Fujitsu Ltd | Semiconductor storage device |
| JPS57198592A (en) * | 1981-05-29 | 1982-12-06 | Hitachi Ltd | Semiconductor memory device |
| US4408305A (en) * | 1981-09-28 | 1983-10-04 | Motorola, Inc. | Memory with permanent array division capability |
| EP0101884A3 (en) * | 1982-07-21 | 1987-09-02 | Hitachi, Ltd. | Monolithic semiconductor memory |
| US4808305A (en) * | 1986-10-09 | 1989-02-28 | Arnold James D | Apparatus for sludge pond treatment |
-
1981
- 1981-05-29 JP JP56081042A patent/JPS57198592A/ja active Granted
-
1982
- 1982-05-28 DE DE8282302774T patent/DE3280349D1/de not_active Expired - Lifetime
- 1982-05-28 EP EP82302774A patent/EP0068645B1/en not_active Expired
- 1982-05-28 CA CA000404001A patent/CA1199724A/en not_active Expired
-
1985
- 1985-03-29 US US06/717,490 patent/US4675845A/en not_active Expired - Lifetime
-
1987
- 1987-04-14 US US07/038,370 patent/US4748591A/en not_active Expired - Lifetime
-
1988
- 1988-03-22 US US07/171,772 patent/US4825418A/en not_active Expired - Lifetime
-
1989
- 1989-04-25 US US07/342,903 patent/US4992986A/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| CA1199724A (en) | 1986-01-21 |
| JPS57198592A (en) | 1982-12-06 |
| US4825418A (en) | 1989-04-25 |
| US4675845A (en) | 1987-06-23 |
| JPH0243279B2 (enExample) | 1990-09-27 |
| EP0068645A3 (en) | 1985-01-09 |
| EP0068645A2 (en) | 1983-01-05 |
| EP0068645B1 (en) | 1991-08-21 |
| US4748591A (en) | 1988-05-31 |
| US4992986A (en) | 1991-02-12 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| 8364 | No opposition during term of opposition |