DE3381653D1 - Hierarchisches speichersystem. - Google Patents

Hierarchisches speichersystem.

Info

Publication number
DE3381653D1
DE3381653D1 DE8383107191T DE3381653T DE3381653D1 DE 3381653 D1 DE3381653 D1 DE 3381653D1 DE 8383107191 T DE8383107191 T DE 8383107191T DE 3381653 T DE3381653 T DE 3381653T DE 3381653 D1 DE3381653 D1 DE 3381653D1
Authority
DE
Germany
Prior art keywords
storage system
hierarchical storage
hierarchical
storage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE8383107191T
Other languages
English (en)
Inventor
Russell William Lavallee
Philip Meade Ryan
Sollitto, Jr
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Application granted granted Critical
Publication of DE3381653D1 publication Critical patent/DE3381653D1/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
    • G06F12/0855—Overlapped cache accessing, e.g. pipeline
    • G06F12/0859—Overlapped cache accessing, e.g. pipeline with reload from main memory

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
DE8383107191T 1982-08-06 1983-07-22 Hierarchisches speichersystem. Expired - Fee Related DE3381653D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/405,812 US4489381A (en) 1982-08-06 1982-08-06 Hierarchical memories having two ports at each subordinate memory level

Publications (1)

Publication Number Publication Date
DE3381653D1 true DE3381653D1 (de) 1990-07-19

Family

ID=23605346

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8383107191T Expired - Fee Related DE3381653D1 (de) 1982-08-06 1983-07-22 Hierarchisches speichersystem.

Country Status (4)

Country Link
US (1) US4489381A (de)
EP (1) EP0100943B1 (de)
JP (1) JPS5930289A (de)
DE (1) DE3381653D1 (de)

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JPH0652530B2 (ja) * 1982-10-25 1994-07-06 株式会社日立製作所 ベクトル・プロセッサ
US4636942A (en) * 1983-04-25 1987-01-13 Cray Research, Inc. Computer vector multiprocessing control
US4630230A (en) * 1983-04-25 1986-12-16 Cray Research, Inc. Solid state storage device
US4661900A (en) * 1983-04-25 1987-04-28 Cray Research, Inc. Flexible chaining in vector processor with selective use of vector registers as operand and result registers
US4901230A (en) * 1983-04-25 1990-02-13 Cray Research, Inc. Computer vector multiprocessing control with multiple access memory and priority conflict resolution method
US4755928A (en) * 1984-03-05 1988-07-05 Storage Technology Corporation Outboard back-up and recovery system with transfer of randomly accessible data sets between cache and host and cache and tape simultaneously
EP0166192B1 (de) * 1984-06-29 1991-10-09 International Business Machines Corporation Hochgeschwindigkeitspufferspeicheranordnung für schnelle Datenübertragung
US4718039A (en) * 1984-06-29 1988-01-05 International Business Machines Intermediate memory array with a parallel port and a buffered serial port
US4823259A (en) * 1984-06-29 1989-04-18 International Business Machines Corporation High speed buffer store arrangement for quick wide transfer of data
US4633440A (en) * 1984-12-31 1986-12-30 International Business Machines Multi-port memory chip in a hierarchical memory
US4755930A (en) * 1985-06-27 1988-07-05 Encore Computer Corporation Hierarchical cache memory system and method
US4754398A (en) * 1985-06-28 1988-06-28 Cray Research, Inc. System for multiprocessor communication using local and common semaphore and information registers
US4745545A (en) * 1985-06-28 1988-05-17 Cray Research, Inc. Memory reference control in a multiprocessor
JPS6221357A (ja) * 1985-07-22 1987-01-29 Toshiba Corp メモリシステム
US4720780A (en) * 1985-09-17 1988-01-19 The Johns Hopkins University Memory-linked wavefront array processor
US4881163A (en) * 1986-09-19 1989-11-14 Amdahl Corporation Computer system architecture employing cache data line move-out queue buffer
ATE63011T1 (de) * 1987-02-16 1991-05-15 Siemens Ag Verfahren zur steuerung des datenaustausches zwischen verarbeitungseinheiten und einem speichersystem mit cachespeicher in datenverarbeitungsanlagen, sowie ein entsprechend arbeitender cachespeicher.
JPH01163852A (ja) * 1987-10-02 1989-06-28 Computer Consoles Inc データ処理システム内のサブシステムおよびその動作方法
US4905188A (en) * 1988-02-22 1990-02-27 International Business Machines Corporation Functional cache memory chip architecture for improved cache access
JPH0743676B2 (ja) * 1988-03-11 1995-05-15 株式会社日立製作所 バツクアツプデータダンプ制御方法及び装置
JPH01280860A (ja) * 1988-05-06 1989-11-13 Hitachi Ltd マルチポートキヤツシユメモリを有するマルチプロセツサシステム
US5247649A (en) * 1988-05-06 1993-09-21 Hitachi, Ltd. Multi-processor system having a multi-port cache memory
DE68926783T2 (de) * 1988-10-07 1996-11-28 Martin Marietta Corp Paralleler datenprozessor
US5166903A (en) * 1988-10-25 1992-11-24 International Business Machines Corporation Memory organization with arrays having an alternate data port facility
US5150328A (en) * 1988-10-25 1992-09-22 Internation Business Machines Corporation Memory organization with arrays having an alternate data port facility
US5142638A (en) * 1989-02-07 1992-08-25 Cray Research, Inc. Apparatus for sharing memory in a multiprocessor system
US5526487A (en) * 1989-02-09 1996-06-11 Cray Research, Inc. System for multiprocessor communication
US4951246A (en) * 1989-08-08 1990-08-21 Cray Research, Inc. Nibble-mode dram solid state storage device
US5224213A (en) * 1989-09-05 1993-06-29 International Business Machines Corporation Ping-pong data buffer for transferring data from one data bus to another data bus
US5247637A (en) * 1990-06-01 1993-09-21 Cray Research, Inc. Method and apparatus for sharing memory in a multiprocessor system
EP0552426A1 (de) * 1992-01-24 1993-07-28 International Business Machines Corporation Mehrstufiges Speichersystem
US6073185A (en) * 1993-08-27 2000-06-06 Teranex, Inc. Parallel data processor
US6067609A (en) * 1998-04-09 2000-05-23 Teranex, Inc. Pattern generation and shift plane operations for a mesh connected computer
US6212628B1 (en) 1998-04-09 2001-04-03 Teranex, Inc. Mesh connected computer
US6173388B1 (en) 1998-04-09 2001-01-09 Teranex Inc. Directly accessing local memories of array processors for improved real-time corner turning processing
US6185667B1 (en) 1998-04-09 2001-02-06 Teranex, Inc. Input/output support for processing in a mesh connected computer
US6504550B1 (en) 1998-05-21 2003-01-07 Mitsubishi Electric & Electronics Usa, Inc. System for graphics processing employing semiconductor device
US6559851B1 (en) 1998-05-21 2003-05-06 Mitsubishi Electric & Electronics Usa, Inc. Methods for semiconductor systems for graphics processing
US6535218B1 (en) 1998-05-21 2003-03-18 Mitsubishi Electric & Electronics Usa, Inc. Frame buffer memory for graphic processing
US6661421B1 (en) 1998-05-21 2003-12-09 Mitsubishi Electric & Electronics Usa, Inc. Methods for operation of semiconductor memory
US6920510B2 (en) * 2002-06-05 2005-07-19 Lsi Logic Corporation Time sharing a single port memory among a plurality of ports
US7739460B1 (en) 2004-08-30 2010-06-15 Integrated Device Technology, Inc. Integrated circuit memory systems having write-back buffers therein that support read-write-modify (RWM) operations within high capacity memory devices

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL264882A (de) * 1960-05-18
US3471838A (en) * 1965-06-21 1969-10-07 Magnavox Co Simultaneous read and write memory configuration
US3675218A (en) * 1970-01-15 1972-07-04 Ibm Independent read-write monolithic memory array
JPS4830168A (de) * 1971-08-23 1973-04-20
US3806888A (en) * 1972-12-04 1974-04-23 Ibm Hierarchial memory system
US4020466A (en) * 1974-07-05 1977-04-26 Ibm Corporation Memory hierarchy system with journaling and copy back
US4125877A (en) * 1976-11-26 1978-11-14 Motorola, Inc. Dual port random access memory storage cell
US4253144A (en) * 1978-12-21 1981-02-24 Burroughs Corporation Multi-processor communication network
US4193127A (en) * 1979-01-02 1980-03-11 International Business Machines Corporation Simultaneous read/write cell
JPS5837633B2 (ja) * 1979-07-23 1983-08-17 富士通株式会社 バッフア・メモリ記憶制御方式
US4317168A (en) * 1979-11-23 1982-02-23 International Business Machines Corporation Cache organization enabling concurrent line castout and line fetch transfers with main storage
DE2948159C2 (de) * 1979-11-29 1983-10-27 Siemens AG, 1000 Berlin und 8000 München Integrierter Speicherbaustein mit wählbaren Betriebsfunktionen
JPS5750381A (en) * 1980-09-12 1982-03-24 Nec Corp Information processor
US4412313A (en) * 1981-01-19 1983-10-25 Bell Telephone Laboratories, Incorporated Random access memory system having high-speed serial data paths

Also Published As

Publication number Publication date
JPS5930289A (ja) 1984-02-17
EP0100943A2 (de) 1984-02-22
EP0100943A3 (en) 1986-10-01
EP0100943B1 (de) 1990-06-13
US4489381A (en) 1984-12-18

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee