DE3484419D1 - Fifo-speichersystem. - Google Patents
Fifo-speichersystem.Info
- Publication number
- DE3484419D1 DE3484419D1 DE8484306913T DE3484419T DE3484419D1 DE 3484419 D1 DE3484419 D1 DE 3484419D1 DE 8484306913 T DE8484306913 T DE 8484306913T DE 3484419 T DE3484419 T DE 3484419T DE 3484419 D1 DE3484419 D1 DE 3484419D1
- Authority
- DE
- Germany
- Prior art keywords
- storage system
- fifo storage
- fifo
- storage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
- G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
- G06F5/16—Multiplexed systems, i.e. using two or more similar devices which are alternately accessed for enqueue and dequeue operations, e.g. ping-pong buffers
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Communication Control (AREA)
- Dram (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US06/551,735 US4642797A (en) | 1983-11-10 | 1983-11-10 | High speed first-in-first-out memory |
Publications (1)
Publication Number | Publication Date |
---|---|
DE3484419D1 true DE3484419D1 (de) | 1991-05-16 |
Family
ID=24202462
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE8484306913T Expired - Lifetime DE3484419D1 (de) | 1983-11-10 | 1984-10-10 | Fifo-speichersystem. |
DE198484306913T Pending DE142263T1 (de) | 1983-11-10 | 1984-10-10 | Fifo-speichersystem. |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE198484306913T Pending DE142263T1 (de) | 1983-11-10 | 1984-10-10 | Fifo-speichersystem. |
Country Status (4)
Country | Link |
---|---|
US (1) | US4642797A (de) |
EP (1) | EP0142263B1 (de) |
JP (1) | JPS60231994A (de) |
DE (2) | DE3484419D1 (de) |
Families Citing this family (23)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2552916B1 (fr) * | 1983-09-29 | 1988-06-10 | Thomas Alain | File d'attente asynchrone a empilement de registres |
US4862419A (en) * | 1983-11-10 | 1989-08-29 | Advanced Micro Devices, Inc. | High speed pointer based first-in-first-out memory |
GB8414109D0 (en) * | 1984-06-02 | 1984-07-04 | Int Computers Ltd | Data reorganisation apparatus |
US4833655A (en) * | 1985-06-28 | 1989-05-23 | Wang Laboratories, Inc. | FIFO memory with decreased fall-through delay |
US4727312A (en) * | 1985-12-23 | 1988-02-23 | Genrad, Inc. | Circuit tester |
US5133062A (en) * | 1986-03-06 | 1992-07-21 | Advanced Micro Devices, Inc. | RAM buffer controller for providing simulated first-in-first-out (FIFO) buffers in a random access memory |
US4949301A (en) * | 1986-03-06 | 1990-08-14 | Advanced Micro Devices, Inc. | Improved pointer FIFO controller for converting a standard RAM into a simulated dual FIFO by controlling the RAM's address inputs |
US4894797A (en) * | 1986-11-17 | 1990-01-16 | Amp Incorporated | FIFO data storage system using PLA controlled multiplexer for concurrent reading and writing of registers by different controllers |
US4907186A (en) * | 1987-02-09 | 1990-03-06 | The United States Of America As Represented By The Secretary Of Commerce | Data direct ingest system |
US4817058A (en) * | 1987-05-21 | 1989-03-28 | Texas Instruments Incorporated | Multiple input/output read/write memory having a multiple-cycle write mask |
US5179688A (en) * | 1987-06-30 | 1993-01-12 | Tandem Computers Incorporated | Queue system with uninterrupted transfer of data through intermediate locations to selected queue location |
US5121479A (en) * | 1988-01-27 | 1992-06-09 | Storage Technology Corporation | Early start mode data transfer apparatus |
EP0353942A3 (de) * | 1988-08-02 | 1991-01-16 | Advanced Micro Devices, Inc. | Durchlauf-FIFO-Speicher |
US5099450A (en) * | 1988-09-22 | 1992-03-24 | Syracuse University | Computer for reducing lambda calculus expressions employing variable containing applicative language code |
DE68929288T2 (de) * | 1988-12-19 | 2001-11-15 | Nec Corp., Tokio/Tokyo | Datenübertragungsvorrichtung |
GB2232797B (en) * | 1989-06-16 | 1993-12-08 | Samsung Semiconductor Inc | RAM based serial memory with pipelined look-ahead reading |
US5122988A (en) * | 1989-09-21 | 1992-06-16 | Schlumberger Tecnologies, Inc. | Data stream smoothing using a FIFO memory |
US5255242A (en) * | 1990-12-17 | 1993-10-19 | Texas Instruments Incorporated | Sequential memory |
US5278957A (en) * | 1991-04-16 | 1994-01-11 | Zilog, Inc. | Data transfer circuit for interfacing two bus systems that operate asynchronously with respect to each other |
US5343435A (en) * | 1991-06-14 | 1994-08-30 | Integrated Device Technology, Inc. | Use of a data register to effectively increase the efficiency of an on-chip write buffer |
US5473755A (en) * | 1992-06-01 | 1995-12-05 | Intel Corporation | System for controlling data stream by changing fall through FIFO last cell state of first component whenever data read out of second component last latch |
US5956492A (en) * | 1996-03-29 | 1999-09-21 | Lsi Logic Corporation | N-deep fixed latency fall-through FIFO architecture |
US6067267A (en) * | 1998-08-12 | 2000-05-23 | Toshiba America Electronic Components, Inc. | Four-way interleaved FIFO architecture with look ahead conditional decoder for PCI applications |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3883854A (en) * | 1973-11-30 | 1975-05-13 | Ibm | Interleaved memory control signal and data handling apparatus using pipelining techniques |
US3976842A (en) * | 1975-03-10 | 1976-08-24 | Hayward Research, Inc. | Analog rate changer |
JPS5320825A (en) * | 1976-08-11 | 1978-02-25 | Hitachi Ltd | Memory control system |
US4151609A (en) * | 1977-10-11 | 1979-04-24 | Monolithic Memories, Inc. | First in first out (FIFO) memory |
US4152781A (en) * | 1978-06-30 | 1979-05-01 | International Business Machines Corporation | Multiplexed and interlaced charge-coupled serial-parallel-serial memory device |
US4259719A (en) * | 1979-06-13 | 1981-03-31 | Ford Motor Company | Binary input processing in a computer using a stack |
US4288860A (en) * | 1979-08-02 | 1981-09-08 | Sperry Corporation | Dynamic storage synchronizer using variable oscillator and FIFO buffer |
US4374428A (en) * | 1979-11-05 | 1983-02-15 | Rca Corporation | Expandable FIFO system |
-
1983
- 1983-11-10 US US06/551,735 patent/US4642797A/en not_active Expired - Lifetime
-
1984
- 1984-10-10 DE DE8484306913T patent/DE3484419D1/de not_active Expired - Lifetime
- 1984-10-10 DE DE198484306913T patent/DE142263T1/de active Pending
- 1984-10-10 EP EP84306913A patent/EP0142263B1/de not_active Expired
- 1984-11-10 JP JP59237412A patent/JPS60231994A/ja active Granted
Also Published As
Publication number | Publication date |
---|---|
JPH0441439B2 (de) | 1992-07-08 |
EP0142263A2 (de) | 1985-05-22 |
DE142263T1 (de) | 1985-10-10 |
US4642797A (en) | 1987-02-10 |
EP0142263A3 (en) | 1987-06-03 |
EP0142263B1 (de) | 1991-04-10 |
JPS60231994A (ja) | 1985-11-18 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8339 | Ceased/non-payment of the annual fee |