DE10231385B4 - Halbleiterchip mit Bondkontaktstellen und zugehörige Mehrchippackung - Google Patents

Halbleiterchip mit Bondkontaktstellen und zugehörige Mehrchippackung Download PDF

Info

Publication number
DE10231385B4
DE10231385B4 DE10231385A DE10231385A DE10231385B4 DE 10231385 B4 DE10231385 B4 DE 10231385B4 DE 10231385 A DE10231385 A DE 10231385A DE 10231385 A DE10231385 A DE 10231385A DE 10231385 B4 DE10231385 B4 DE 10231385B4
Authority
DE
Germany
Prior art keywords
chip
semiconductor
pad
chips
further characterized
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE10231385A
Other languages
German (de)
English (en)
Other versions
DE10231385A1 (de
Inventor
Young-Hee Yongin Song
Ill-Heung Suwon Choi
Jung-Jin Cheonan Kim
Hai-Jeong Suwon Sohn
Chung-Woo Suwon Lee
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Electronics Co Ltd
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from KR1020020003030A external-priority patent/KR100567225B1/ko
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Priority to DE20221707U priority Critical patent/DE20221707U1/de
Publication of DE10231385A1 publication Critical patent/DE10231385A1/de
Application granted granted Critical
Publication of DE10231385B4 publication Critical patent/DE10231385B4/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00Interconnections in chips, wafers or substrates
    • H10W20/40Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/49Adaptable interconnections, e.g. fuses or antifuses
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/40Leadframes
    • H10W70/411Chip-supporting parts, e.g. die pads
    • H10W70/415Leadframe inner leads serving as die pads
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/01Manufacture or treatment
    • H10W72/019Manufacture or treatment of bond pads
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/90Bond pads, in general
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00Encapsulations, e.g. protective coatings
    • H10W74/10Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H10W74/114Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations
    • H10W74/117Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations the substrate having spherical bumps for external connection
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/811Multiple chips on leadframes
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01Manufacture or treatment
    • H10W70/05Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/611Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together
    • H10W70/614Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together the multiple chips being integrally enclosed
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/01Manufacture or treatment
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/071Connecting or disconnecting
    • H10W72/075Connecting or disconnecting of bond wires
    • H10W72/07541Controlling the environment, e.g. atmosphere composition or temperature
    • H10W72/07551Controlling the environment, e.g. atmosphere composition or temperature characterised by changes in properties of the bond wires during the connecting
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/20Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/29Bond pads specially adapted therefor
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/50Bond wires
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/50Bond wires
    • H10W72/531Shapes of wire connectors
    • H10W72/536Shapes of wire connectors the connected ends being ball-shaped
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/50Bond wires
    • H10W72/531Shapes of wire connectors
    • H10W72/5363Shapes of wire connectors the connected ends being wedge-shaped
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/50Bond wires
    • H10W72/531Shapes of wire connectors
    • H10W72/5366Shapes of wire connectors the bond wires having kinks
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/50Bond wires
    • H10W72/541Dispositions of bond wires
    • H10W72/547Dispositions of multiple bond wires
    • H10W72/5473Dispositions of multiple bond wires multiple bond wires connected to a common bond pad
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/50Bond wires
    • H10W72/59Bond pads specially adapted therefor
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/851Dispositions of multiple connectors or interconnections
    • H10W72/853On the same surface
    • H10W72/865Die-attach connectors and bond wires
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/851Dispositions of multiple connectors or interconnections
    • H10W72/874On different surfaces
    • H10W72/884Die-attach connectors and bond wires
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/90Bond pads, in general
    • H10W72/921Structures or relative sizes of bond pads
    • H10W72/923Bond pads having multiple stacked layers
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/90Bond pads, in general
    • H10W72/931Shapes of bond pads
    • H10W72/932Plan-view shape, i.e. in top view
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/90Bond pads, in general
    • H10W72/931Shapes of bond pads
    • H10W72/934Cross-sectional shape, i.e. in side view
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/90Bond pads, in general
    • H10W72/951Materials of bond pads
    • H10W72/952Materials of bond pads comprising metals or metalloids, e.g. PbSn, Ag or Cu
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/90Bond pads, in general
    • H10W72/981Auxiliary members, e.g. spacers
    • H10W72/983Reinforcing structures, e.g. collars
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00Encapsulations, e.g. protective coatings
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/20Configurations of stacked chips
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/20Configurations of stacked chips
    • H10W90/231Configurations of stacked chips the stacked chips being on both top and bottom sides of an auxiliary carrier having no electrical connection structure
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/20Configurations of stacked chips
    • H10W90/271Configurations of stacked chips the chips having passive surfaces facing each other, i.e. in a back-to-back arrangement
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/20Configurations of stacked chips
    • H10W90/291Configurations of stacked chips characterised by containers, encapsulations, or other housings for the stacked chips
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/732Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between stacked chips
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/736Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked lead frame, conducting package substrate or heat sink
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Wire Bonding (AREA)
DE10231385A 2001-07-10 2002-07-08 Halbleiterchip mit Bondkontaktstellen und zugehörige Mehrchippackung Expired - Lifetime DE10231385B4 (de)

Priority Applications (1)

Application Number Priority Date Filing Date Title
DE20221707U DE20221707U1 (de) 2001-07-10 2002-07-08 Halbleiterchip mit Bondkontaktstellen und zugehörige Mehrchippackung

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
KR2001/41154 2001-07-10
KR20010041154 2001-07-10
KR1020020003030A KR100567225B1 (ko) 2001-07-10 2002-01-18 칩 패드가 셀 영역 위에 형성된 집적회로 칩과 그 제조방법 및 멀티 칩 패키지
KR2002/3030 2002-01-18

Publications (2)

Publication Number Publication Date
DE10231385A1 DE10231385A1 (de) 2003-01-30
DE10231385B4 true DE10231385B4 (de) 2007-02-22

Family

ID=26639226

Family Applications (1)

Application Number Title Priority Date Filing Date
DE10231385A Expired - Lifetime DE10231385B4 (de) 2001-07-10 2002-07-08 Halbleiterchip mit Bondkontaktstellen und zugehörige Mehrchippackung

Country Status (3)

Country Link
US (7) US6642627B2 (https=)
JP (1) JP2003100894A (https=)
DE (1) DE10231385B4 (https=)

Families Citing this family (51)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10231385B4 (de) * 2001-07-10 2007-02-22 Samsung Electronics Co., Ltd., Suwon Halbleiterchip mit Bondkontaktstellen und zugehörige Mehrchippackung
KR100475740B1 (ko) * 2003-02-25 2005-03-10 삼성전자주식회사 신호 완결성 개선 및 칩 사이즈 감소를 위한 패드배치구조를 갖는 반도체 집적 회로장치
US6984881B2 (en) * 2003-06-16 2006-01-10 Sandisk Corporation Stackable integrated circuit package and method therefor
US7309923B2 (en) * 2003-06-16 2007-12-18 Sandisk Corporation Integrated circuit package having stacked integrated circuits and method therefor
DE10333465B4 (de) * 2003-07-22 2008-07-24 Infineon Technologies Ag Elektronisches Bauteil mit Halbleiterchip, Verfahren zur Herstellung desselben sowie Verfahren zur Herstellung eines Halbleiterwafers mit Kontaktflecken
KR100547354B1 (ko) * 2003-09-04 2006-01-26 삼성전기주식회사 에지 본딩용 메탈 패턴이 형성된 반도체 칩을 구비한bga 패키지 및 그 제조 방법
US7422930B2 (en) * 2004-03-02 2008-09-09 Infineon Technologies Ag Integrated circuit with re-route layer and stacked die assembly
KR100583966B1 (ko) * 2004-06-08 2006-05-26 삼성전자주식회사 재배치된 금속 배선들을 갖는 집적회로 패키지들 및 그제조방법들
WO2006016198A1 (en) * 2004-08-02 2006-02-16 Infineon Technologies Ag Electronic component with stacked semiconductor chips and heat dissipating means
JP2006286688A (ja) * 2005-03-31 2006-10-19 Elpida Memory Inc 半導体装置
US7348210B2 (en) * 2005-04-27 2008-03-25 International Business Machines Corporation Post bump passivation for soft error protection
JP2006318987A (ja) * 2005-05-10 2006-11-24 Rohm Co Ltd 半導体チップの電極構造およびその形成方法ならびに半導体チップ
US20060267173A1 (en) * 2005-05-26 2006-11-30 Sandisk Corporation Integrated circuit package having stacked integrated circuits and method therefor
US7466013B2 (en) * 2005-12-15 2008-12-16 Etron Technology, Inc. Semiconductor die structure featuring a triple pad organization
KR100780691B1 (ko) * 2006-03-29 2007-11-30 주식회사 하이닉스반도체 폴딩 칩 플래나 스택 패키지
KR100713931B1 (ko) * 2006-03-29 2007-05-07 주식회사 하이닉스반도체 고속 및 고성능의 반도체 패키지
US9202776B2 (en) * 2006-06-01 2015-12-01 Stats Chippac Ltd. Stackable multi-chip package system
JP4969934B2 (ja) 2006-07-19 2012-07-04 株式会社東芝 半導体装置
TWI301663B (en) * 2006-08-02 2008-10-01 Phoenix Prec Technology Corp Circuit board structure with embedded semiconductor chip and fabrication method thereof
US7719122B2 (en) * 2007-01-11 2010-05-18 Taiwan Semiconductor Manufacturing Co., Ltd. System-in-package packaging for minimizing bond wire contamination and yield loss
US8174127B2 (en) * 2007-06-21 2012-05-08 Stats Chippac Ltd. Integrated circuit package system employing device stacking
US7830020B2 (en) * 2007-06-21 2010-11-09 Stats Chippac Ltd. Integrated circuit package system employing device stacking
KR101185886B1 (ko) 2007-07-23 2012-09-25 삼성전자주식회사 유니버설 배선 라인들을 포함하는 반도체 칩, 반도체패키지, 카드 및 시스템
US7972902B2 (en) * 2007-07-23 2011-07-05 Samsung Electronics Co., Ltd. Method of manufacturing a wafer including providing electrical conductors isolated from circuitry
WO2009096987A1 (en) * 2008-02-01 2009-08-06 Hewlett-Packard Development Company, L.P. Teeth locating and whitening in a digital image
US9059074B2 (en) * 2008-03-26 2015-06-16 Stats Chippac Ltd. Integrated circuit package system with planar interconnect
US7786557B2 (en) * 2008-05-19 2010-08-31 Mediatek Inc. QFN Semiconductor package
US20110042794A1 (en) * 2008-05-19 2011-02-24 Tung-Hsien Hsieh Qfn semiconductor package and circuit board structure adapted for the same
TWI372453B (en) * 2008-09-01 2012-09-11 Advanced Semiconductor Eng Copper bonding wire, wire bonding structure and method for processing and bonding a wire
US8043894B2 (en) * 2008-08-26 2011-10-25 Stats Chippac Ltd. Integrated circuit package system with redistribution layer
US8115286B2 (en) * 2008-10-22 2012-02-14 Honeywell International Inc. Integrated sensor including sensing and processing die mounted on opposite sides of package substrate
KR101539402B1 (ko) * 2008-10-23 2015-07-27 삼성전자주식회사 반도체 패키지
US20100148218A1 (en) * 2008-12-10 2010-06-17 Panasonic Corporation Semiconductor integrated circuit device and method for designing the same
TW201030916A (en) * 2009-02-11 2010-08-16 Advanced Semiconductor Eng Pad and package structure using the same
US7994615B2 (en) * 2009-08-28 2011-08-09 International Rectifier Corporation Direct contact leadless package for high current devices
US8093695B2 (en) * 2009-09-04 2012-01-10 International Rectifier Corporation Direct contact leadless flip chip package for high current devices
US8222722B2 (en) * 2009-09-11 2012-07-17 St-Ericsson Sa Integrated circuit package and device
KR101563630B1 (ko) * 2009-09-17 2015-10-28 에스케이하이닉스 주식회사 반도체 패키지
US8895440B2 (en) 2010-08-06 2014-11-25 Stats Chippac, Ltd. Semiconductor die and method of forming Fo-WLCSP vertical interconnect using TSV and TMV
KR20120062366A (ko) * 2010-12-06 2012-06-14 삼성전자주식회사 멀티칩 패키지의 제조 방법
CN103151316B (zh) * 2011-12-06 2017-10-20 北京大学深圳研究生院 一种基于mcp封装形式的可重构算子阵列结构的规模扩展方法
KR20130113032A (ko) * 2012-04-05 2013-10-15 에스케이하이닉스 주식회사 반도체 기판, 이를 갖는 반도체 칩 및 적층 반도체 패키지
US8698323B2 (en) * 2012-06-18 2014-04-15 Invensas Corporation Microelectronic assembly tolerant to misplacement of microelectronic elements therein
KR102053349B1 (ko) 2013-05-16 2019-12-06 삼성전자주식회사 반도체 패키지
US9134193B2 (en) * 2013-12-06 2015-09-15 Freescale Semiconductor, Inc. Stacked die sensor package
US9960135B2 (en) * 2015-03-23 2018-05-01 Texas Instruments Incorporated Metal bond pad with cobalt interconnect layer and solder thereon
JP6672812B2 (ja) * 2016-01-14 2020-03-25 三菱電機株式会社 半導体装置及びその製造方法
KR101973446B1 (ko) 2017-11-28 2019-04-29 삼성전기주식회사 팬-아웃 반도체 패키지
KR20200047845A (ko) * 2018-10-24 2020-05-08 삼성전자주식회사 반도체 패키지
KR102879321B1 (ko) * 2020-04-17 2025-10-31 에스케이하이닉스 주식회사 저항 소자를 구비하는 반도체 장치
US11676920B2 (en) 2021-01-26 2023-06-13 United Microelectronics Corp. Semiconductor device and method for fabricating the same

Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0221496A2 (en) * 1985-11-04 1987-05-13 International Business Machines Corporation Integrated circuit package
US4723197A (en) * 1985-12-16 1988-02-02 National Semiconductor Corporation Bonding pad interconnection structure
JPH06275794A (ja) * 1993-03-18 1994-09-30 Matsushita Electric Ind Co Ltd 半導体記憶装置およびその製造方法
DE19610302A1 (de) * 1995-03-30 1996-10-02 Mitsubishi Electric Corp Halbleiterverkappung
US5723822A (en) * 1995-03-24 1998-03-03 Integrated Device Technology, Inc. Structure for fabricating a bonding pad having improved adhesion to an underlying structure
US5751065A (en) * 1993-08-05 1998-05-12 Lucent Technologies Inc. Integrated circuit with active devices under bond pads
US5834844A (en) * 1995-03-24 1998-11-10 Shinko Electric Industries Co., Ltd. Semiconductor device having an element with circuit pattern thereon
US6111317A (en) * 1996-01-18 2000-08-29 Kabushiki Kaisha Toshiba Flip-chip connection type semiconductor integrated circuit device
US6175149B1 (en) * 1998-02-13 2001-01-16 Micron Technology, Inc. Mounting multiple semiconductor dies in a package
EP1094517A2 (en) * 1999-10-19 2001-04-25 Fujitsu Limited Semiconductor device and method for producing the same

Family Cites Families (51)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59181041A (ja) 1983-03-31 1984-10-15 Toshiba Corp 半導体集積回路装置
JPH0193136A (ja) 1987-10-05 1989-04-12 Nec Corp 半導体装置
JP2692099B2 (ja) * 1988-01-14 1997-12-17 日本電気株式会社 マスタースライス方式の集積回路
JPH04324958A (ja) * 1991-04-25 1992-11-13 Hitachi Ltd 半導体装置
US5422435A (en) * 1992-05-22 1995-06-06 National Semiconductor Corporation Stacked multi-chip modules and method of manufacturing
JP3101077B2 (ja) * 1992-06-11 2000-10-23 株式会社日立製作所 半導体集積回路装置
JPH0737988A (ja) * 1993-07-20 1995-02-07 Hitachi Ltd 半導体集積回路装置の製造方法
JP2792532B2 (ja) * 1994-09-30 1998-09-03 日本電気株式会社 半導体装置の製造方法及び半導体ウエハー
JP3362545B2 (ja) * 1995-03-09 2003-01-07 ソニー株式会社 半導体装置の製造方法
JP3301894B2 (ja) 1995-04-10 2002-07-15 新光電気工業株式会社 半導体装置の製造方法
KR100218996B1 (ko) * 1995-03-24 1999-09-01 모기 쥰이찌 반도체장치
JP2763020B2 (ja) * 1995-04-27 1998-06-11 日本電気株式会社 半導体パッケージ及び半導体装置
KR0154647B1 (ko) * 1995-09-20 1998-10-15 김광호 노출된 공통 패드를 갖는 멀티 칩 패키지
KR100274333B1 (ko) * 1996-01-19 2001-01-15 모기 쥰이찌 도체층부착 이방성 도전시트 및 이를 사용한 배선기판
US5969424A (en) * 1997-03-19 1999-10-19 Fujitsu Limited Semiconductor device with pad structure
JP3545200B2 (ja) * 1997-04-17 2004-07-21 シャープ株式会社 半導体装置
JPH1140624A (ja) 1997-07-22 1999-02-12 Mitsubishi Electric Corp 半導体装置のリペア方法
JP3152180B2 (ja) 1997-10-03 2001-04-03 日本電気株式会社 半導体装置及びその製造方法
JPH11204576A (ja) * 1998-01-19 1999-07-30 Citizen Watch Co Ltd 半導体配線の構造
US6429528B1 (en) * 1998-02-27 2002-08-06 Micron Technology, Inc. Multichip semiconductor package
JPH11354563A (ja) * 1998-06-11 1999-12-24 Citizen Watch Co Ltd 半導体配線の構造
JP2000031191A (ja) 1998-07-15 2000-01-28 Mitsui High Tec Inc 半導体装置
JP3643706B2 (ja) 1998-07-31 2005-04-27 三洋電機株式会社 半導体装置
US6103552A (en) * 1998-08-10 2000-08-15 Lin; Mou-Shiung Wafer scale packaging scheme
JP3494901B2 (ja) * 1998-09-18 2004-02-09 シャープ株式会社 半導体集積回路装置
JP3389517B2 (ja) 1998-12-10 2003-03-24 三洋電機株式会社 チップサイズパッケージ及びその製造方法
US6869870B2 (en) 1998-12-21 2005-03-22 Megic Corporation High performance system-on-chip discrete components using post passivation process
SG93278A1 (en) * 1998-12-21 2002-12-17 Mou Shiung Lin Top layers of metal for high performance ics
US6383916B1 (en) * 1998-12-21 2002-05-07 M. S. Lin Top layers of metal for high performance IC's
US6495442B1 (en) * 2000-10-18 2002-12-17 Magic Corporation Post passivation interconnection schemes on top of the IC chips
KR100301052B1 (ko) * 1998-12-28 2001-11-02 윤종용 소프트에러를감소하기위한반도체소자의제조방법
SG93192A1 (en) * 1999-01-28 2002-12-17 United Microelectronics Corp Face-to-face multi chip package
JP2000243876A (ja) * 1999-02-23 2000-09-08 Fujitsu Ltd 半導体装置とその製造方法
JP3423245B2 (ja) 1999-04-09 2003-07-07 沖電気工業株式会社 半導体装置及びその実装方法
US6228687B1 (en) * 1999-06-28 2001-05-08 Micron Technology, Inc. Wafer-level package and methods of fabricating
JP3497775B2 (ja) * 1999-08-23 2004-02-16 松下電器産業株式会社 半導体装置
JP2001085604A (ja) * 1999-09-14 2001-03-30 Toshiba Corp 半導体装置
US6439370B1 (en) * 1999-10-05 2002-08-27 M&R Printing Equipment, Inc. Method and apparatus for the automatic loading of an article onto a printing machine
JP2001156172A (ja) * 1999-11-24 2001-06-08 Hitachi Ltd 半導体装置
US6344687B1 (en) * 1999-12-22 2002-02-05 Chih-Kung Huang Dual-chip packaging
JP2003520444A (ja) * 2000-01-20 2003-07-02 アンバーウェーブ システムズ コーポレイション 高温成長を不要とする低貫通転位密度格子不整合エピ層
JP3798620B2 (ja) * 2000-12-04 2006-07-19 富士通株式会社 半導体装置の製造方法
US6503776B2 (en) * 2001-01-05 2003-01-07 Advanced Semiconductor Engineering, Inc. Method for fabricating stacked chip package
US20020100600A1 (en) * 2001-01-26 2002-08-01 Albert Douglas M. Stackable microcircuit layer formed from a plastic encapsulated microcircuit and method of making the same
DE10231385B4 (de) * 2001-07-10 2007-02-22 Samsung Electronics Co., Ltd., Suwon Halbleiterchip mit Bondkontaktstellen und zugehörige Mehrchippackung
US6977440B2 (en) * 2001-10-09 2005-12-20 Tessera, Inc. Stacked packages
US6737750B1 (en) * 2001-12-07 2004-05-18 Amkor Technology, Inc. Structures for improving heat dissipation in stacked semiconductor packages
US6870276B1 (en) * 2001-12-26 2005-03-22 Micron Technology, Inc. Apparatus for supporting microelectronic substrates
US7423336B2 (en) * 2002-04-08 2008-09-09 Micron Technology, Inc. Bond pad rerouting element, rerouted semiconductor devices including the rerouting element, and assemblies including the rerouted semiconductor devices
KR100524974B1 (ko) * 2003-07-01 2005-10-31 삼성전자주식회사 양면 스택 멀티 칩 패키징을 위한 인라인 집적회로 칩패키지 제조 장치 및 이를 이용한 집적회로 칩 패키지제조 방법
US7368320B2 (en) * 2003-08-29 2008-05-06 Micron Technology, Inc. Method of fabricating a two die semiconductor assembly

Patent Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0221496A2 (en) * 1985-11-04 1987-05-13 International Business Machines Corporation Integrated circuit package
US4723197A (en) * 1985-12-16 1988-02-02 National Semiconductor Corporation Bonding pad interconnection structure
JPH06275794A (ja) * 1993-03-18 1994-09-30 Matsushita Electric Ind Co Ltd 半導体記憶装置およびその製造方法
US5751065A (en) * 1993-08-05 1998-05-12 Lucent Technologies Inc. Integrated circuit with active devices under bond pads
US5723822A (en) * 1995-03-24 1998-03-03 Integrated Device Technology, Inc. Structure for fabricating a bonding pad having improved adhesion to an underlying structure
US5834844A (en) * 1995-03-24 1998-11-10 Shinko Electric Industries Co., Ltd. Semiconductor device having an element with circuit pattern thereon
DE19610302A1 (de) * 1995-03-30 1996-10-02 Mitsubishi Electric Corp Halbleiterverkappung
US6111317A (en) * 1996-01-18 2000-08-29 Kabushiki Kaisha Toshiba Flip-chip connection type semiconductor integrated circuit device
US6175149B1 (en) * 1998-02-13 2001-01-16 Micron Technology, Inc. Mounting multiple semiconductor dies in a package
EP1094517A2 (en) * 1999-10-19 2001-04-25 Fujitsu Limited Semiconductor device and method for producing the same

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
MASATOSHI YASUNAGA: Chip Scale Package: "A Lighthy Dressed LSI Chip". In: IEEE Transact. on Components, Packaging, and Manufacturing Technology-Post A, Vol. 18, No. 3, Sept. 1995, pp. 451-7 *

Also Published As

Publication number Publication date
US20070108632A1 (en) 2007-05-17
US20070057367A1 (en) 2007-03-15
US7576440B2 (en) 2009-08-18
US20070057383A1 (en) 2007-03-15
US7547977B2 (en) 2009-06-16
US20070108562A1 (en) 2007-05-17
US20070108633A1 (en) 2007-05-17
US20040041258A1 (en) 2004-03-04
US20030011068A1 (en) 2003-01-16
US7825523B2 (en) 2010-11-02
US7453159B2 (en) 2008-11-18
JP2003100894A (ja) 2003-04-04
US7148578B2 (en) 2006-12-12
DE10231385A1 (de) 2003-01-30
US6642627B2 (en) 2003-11-04
US7541682B2 (en) 2009-06-02

Similar Documents

Publication Publication Date Title
DE10231385B4 (de) Halbleiterchip mit Bondkontaktstellen und zugehörige Mehrchippackung
DE10259221B4 (de) Elektronisches Bauteil mit einem Stapel aus Halbleiterchips und Verfahren zur Herstellung desselben
DE19520700B4 (de) Halbleiterbausteinanordnung
DE69325749T2 (de) Gestapelte Mehrchip-Module und Verfahren zur Herstellung
DE10295972B4 (de) Nicht in einer Form hergestellte Packung für eine Halbleiteranordnung und Verfahren zur Herstellung
DE4301915C2 (de) Mehrfachchip-Halbleitervorrichtung
DE10250538B4 (de) Elektronisches Bauteil als Multichipmodul und Verfahren zu dessen Herstellung
DE69621851T2 (de) Mehrchipanlage und sandwich-typ verfahren zur herstellung durch verwendung von leitern
DE102005010156B4 (de) Verfahren zum Ausbilden einer Anordnung aus gestapelten Einzelschaltkreisen
DE60030931T2 (de) Halbleiteranordnung und Herstellungsverfahren dafür
DE10201781B4 (de) Hochfrequenz-Leistungsbauteil und Hochfrequenz-Leistungsmodul sowie Verfahren zur Herstellung derselben
DE60132855T2 (de) Kontaktierungsstruktur einer integrierten Leistungsschaltung
DE102004004532B4 (de) Halbleitervorrichtung
DE102011056315B4 (de) Halbleiterbauelement und Verfahren zu dessen Herstellung
DE69422463T2 (de) Halbleiteranordnung mit einem Halbleiterchip mit Rückseitenelektrode
DE19747105A1 (de) Bauelement mit gestapelten Halbleiterchips
DE3233195A1 (de) Halbleitervorrichtung
WO2000048249A1 (de) Halbleiterbauelement mit einem chipträger mit öffnungen zur kontaktierung
DE10339770B4 (de) Verfahren zum Herstellen einer FBGA-Anordnung
DE68928193T2 (de) Halbleiterchip und Verfahren zu seiner Herstellung
DE102020108846B4 (de) Chip-zu-chip-verbindung in der verkapselung eines vergossenen halbleitergehäuses und verfahren zu dessen herstellung
DE69418037T2 (de) Leistungshalbleitervorrichtung aus MOS-Technology-Chips und Gehäuseaufbau
DE102009001522B4 (de) Halbleiterstruktur mit Kondensator
DE69223825T2 (de) Isolierter Leiterrahmen für eingekapselte Halbleiteranordnungen
DE10255289A1 (de) Elektronisches Bauteil mit gestapelten Halbleiterchips in paralleler Anordnung und Verfahren zu dessen Herstellung

Legal Events

Date Code Title Description
OP8 Request for examination as to paragraph 44 patent law
8364 No opposition during term of opposition
R071 Expiry of right