DE68928193T2 - Halbleiterchip und Verfahren zu seiner Herstellung - Google Patents

Halbleiterchip und Verfahren zu seiner Herstellung

Info

Publication number
DE68928193T2
DE68928193T2 DE68928193T DE68928193T DE68928193T2 DE 68928193 T2 DE68928193 T2 DE 68928193T2 DE 68928193 T DE68928193 T DE 68928193T DE 68928193 T DE68928193 T DE 68928193T DE 68928193 T2 DE68928193 T2 DE 68928193T2
Authority
DE
Germany
Prior art keywords
production
semiconductor chip
chip
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE68928193T
Other languages
English (en)
Other versions
DE68928193D1 (de
Inventor
Hiroyuko Misawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Application granted granted Critical
Publication of DE68928193D1 publication Critical patent/DE68928193D1/de
Publication of DE68928193T2 publication Critical patent/DE68928193T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H01L23/5286—Arrangements of power or ground buses
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
DE68928193T 1988-09-28 1989-09-25 Halbleiterchip und Verfahren zu seiner Herstellung Expired - Fee Related DE68928193T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63245053A JPH0290651A (ja) 1988-09-28 1988-09-28 半導体集積回路

Publications (2)

Publication Number Publication Date
DE68928193D1 DE68928193D1 (de) 1997-08-28
DE68928193T2 true DE68928193T2 (de) 1997-11-13

Family

ID=17127880

Family Applications (1)

Application Number Title Priority Date Filing Date
DE68928193T Expired - Fee Related DE68928193T2 (de) 1988-09-28 1989-09-25 Halbleiterchip und Verfahren zu seiner Herstellung

Country Status (4)

Country Link
US (1) US5119168A (de)
EP (1) EP0361825B1 (de)
JP (1) JPH0290651A (de)
DE (1) DE68928193T2 (de)

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2965626B2 (ja) * 1990-06-25 1999-10-18 株式会社東芝 半導体集積回路
JP2677737B2 (ja) * 1992-06-24 1997-11-17 株式会社東芝 半導体装置
JP2930174B2 (ja) * 1993-09-01 1999-08-03 日本電気株式会社 半導体集積回路装置
JPH08106617A (ja) * 1994-10-04 1996-04-23 Fujitsu Ltd 磁気ディスク装置
US6098271A (en) * 1994-10-04 2000-08-08 Fujitsu Limited Method for assembling a magnetic disk drive with a relaying flexible printed circuit sheet
US6049136A (en) * 1998-06-03 2000-04-11 Hewlett-Packard Company Integrated circuit having unique lead configuration
JP4330676B2 (ja) * 1998-08-17 2009-09-16 株式会社東芝 半導体集積回路
JP4615117B2 (ja) * 2000-11-21 2011-01-19 パナソニック株式会社 半導体ウエハへのバンプ形成方法及びバンプ形成装置
JP2002157582A (ja) * 2000-11-21 2002-05-31 Matsushita Electric Ind Co Ltd 半導体ウエハ上のｉｃ傾き補正方法、及びｉｃ傾き補正装置
US6653563B2 (en) * 2001-03-30 2003-11-25 Intel Corporation Alternate bump metallurgy bars for power and ground routing
US6894399B2 (en) 2001-04-30 2005-05-17 Intel Corporation Microelectronic device having signal distribution functionality on an interfacial layer thereof
US6888240B2 (en) 2001-04-30 2005-05-03 Intel Corporation High performance, low cost microelectronic circuit package with interposer
US7071024B2 (en) 2001-05-21 2006-07-04 Intel Corporation Method for packaging a microelectronic device using on-die bond pad expansion
US7183658B2 (en) 2001-09-05 2007-02-27 Intel Corporation Low cost microelectronic circuit package
US6825509B1 (en) * 2001-11-26 2004-11-30 Corrent Corporation Power distribution system, method, and layout for an electronic device
US6538314B1 (en) * 2002-03-29 2003-03-25 International Business Machines Corporation Power grid wiring for semiconductor devices having voltage islands
JP2010074018A (ja) * 2008-09-22 2010-04-02 Nec Electronics Corp 半導体装置
DE102013102542A1 (de) * 2013-03-13 2014-09-18 Schweizer Electronic Ag Elektronisches Bauteil und Verfahren zum Herstellen eines elektronischen Bauteils

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1982001102A1 (en) * 1980-09-15 1982-04-01 Mulholland W Integrated circuit power distribution network
FR2495835A1 (fr) * 1980-12-05 1982-06-11 Cii Honeywell Bull Dispositif a circuits integres a reseau metallique d'interconnexion, et procede de fabrication de ce dispositif
JPS5835963A (ja) * 1981-08-28 1983-03-02 Fujitsu Ltd 集積回路装置
IT1213261B (it) * 1984-12-20 1989-12-14 Sgs Thomson Microelectronics Dispositivo a semiconduttore con metallizzazione a piu' spessori eprocedimento per la sua fabbricazione.
US4602270A (en) * 1985-05-17 1986-07-22 United Technologies Corporation Gate array with reduced isolation

Also Published As

Publication number Publication date
EP0361825A3 (de) 1990-12-05
EP0361825B1 (de) 1997-07-23
US5119168A (en) 1992-06-02
EP0361825A2 (de) 1990-04-04
DE68928193D1 (de) 1997-08-28
JPH0290651A (ja) 1990-03-30

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee