DE3688711D1 - Integrierte halbleiterschaltungsanordnung und verfahren zu ihrer herstellung. - Google Patents
Integrierte halbleiterschaltungsanordnung und verfahren zu ihrer herstellung.Info
- Publication number
- DE3688711D1 DE3688711D1 DE8686102856T DE3688711T DE3688711D1 DE 3688711 D1 DE3688711 D1 DE 3688711D1 DE 8686102856 T DE8686102856 T DE 8686102856T DE 3688711 T DE3688711 T DE 3688711T DE 3688711 D1 DE3688711 D1 DE 3688711D1
- Authority
- DE
- Germany
- Prior art keywords
- production
- semiconductor circuit
- integrated semiconductor
- integrated
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000004065 semiconductor Substances 0.000 title 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0692—Surface layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
- H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
- H01L21/2251—Diffusion into or out of group IV semiconductors
- H01L21/2254—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides
- H01L21/2257—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides the applied layer being silicon or silicide or SIPOS, e.g. polysilicon, porous silicon
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8222—Bipolar technology
- H01L21/8226—Bipolar technology comprising merged transistor logic or integrated injection logic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8248—Combination of bipolar and field-effect technology
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8248—Combination of bipolar and field-effect technology
- H01L21/8249—Bipolar and MOS technology
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0214—Particular design considerations for integrated circuits for internal polarisation, e.g. I2L
- H01L27/0229—Particular design considerations for integrated circuits for internal polarisation, e.g. I2L of bipolar structures
- H01L27/0233—Integrated injection logic structures [I2L]
- H01L27/0244—I2L structures integrated in combination with analog structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/45—Ohmic electrodes
- H01L29/456—Ohmic electrodes on silicon
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/73—Bipolar junction transistors
- H01L29/732—Vertical transistors
- H01L29/7325—Vertical transistors having an emitter-base junction leaving at a main surface and a base-collector junction leaving at a peripheral surface of the body, e.g. mesa planar transistor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Bipolar Transistors (AREA)
Applications Claiming Priority (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP60045137A JPS61203676A (ja) | 1985-03-07 | 1985-03-07 | バイポ−ラ型半導体装置 |
JP4602385A JPS61206250A (ja) | 1985-03-08 | 1985-03-08 | 半導体集積回路装置及びその製造方法 |
JP5172085A JPS61210668A (ja) | 1985-03-15 | 1985-03-15 | 半導体装置 |
JP60065231A JPS61224448A (ja) | 1985-03-29 | 1985-03-29 | 半導体装置の製造方法 |
JP6523085A JPS61224456A (ja) | 1985-03-29 | 1985-03-29 | バイポ−ラ型半導体装置の製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
DE3688711D1 true DE3688711D1 (de) | 1993-08-26 |
DE3688711T2 DE3688711T2 (de) | 1993-12-16 |
Family
ID=27522449
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE86102856T Expired - Fee Related DE3688711T2 (de) | 1985-03-07 | 1986-03-05 | Integrierte Halbleiterschaltungsanordnung und Verfahren zu ihrer Herstellung. |
Country Status (3)
Country | Link |
---|---|
US (1) | US5144408A (de) |
EP (1) | EP0193934B1 (de) |
DE (1) | DE3688711T2 (de) |
Families Citing this family (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB2194676B (en) * | 1986-07-30 | 1991-03-20 | Mitsubishi Electric Corp | A semiconductor integrated circuit device and a method of producing same |
DE68928787T2 (de) * | 1988-04-11 | 1998-12-24 | Synergy Semiconductor Corp., Santa Clara, Calif. | Verfahren zur Herstellung eines Bipolartransistors |
US6004855A (en) * | 1988-04-11 | 1999-12-21 | Synergy Semiconductor Corporation | Process for producing a high performance bipolar structure |
KR930004720B1 (ko) * | 1988-11-04 | 1993-06-03 | 마쯔시따 덴끼 산교 가부시끼가이샤 | 반도체장치 및 그 제조방법 |
JPH03152939A (ja) * | 1989-11-09 | 1991-06-28 | Toshiba Corp | 半導体集積回路装置 |
US5288651A (en) * | 1989-11-09 | 1994-02-22 | Kabushiki Kaisha Toshiba | Method of making semiconductor integrated circuit device including bipolar transistors, MOS FETs and CCD |
EP0534632B1 (de) * | 1991-09-24 | 2002-01-16 | Matsushita Electronics Corporation, Ltd. | Integrierte Halbleiterschaltungsanordnung und Verfahren zu ihrer Herstellung |
JP3263299B2 (ja) * | 1995-12-04 | 2002-03-04 | 株式会社東芝 | 半導体装置およびその製造方法 |
JP3309959B2 (ja) * | 1998-04-16 | 2002-07-29 | 日本電気株式会社 | 半導体装置 |
US7166232B2 (en) * | 2000-12-21 | 2007-01-23 | Micronas Gmbh | Method for producing a solid body including a microstructure |
JP2003197908A (ja) * | 2001-09-12 | 2003-07-11 | Seiko Instruments Inc | 半導体素子及びその製造方法 |
JP2008288386A (ja) * | 2007-05-17 | 2008-11-27 | Hitachi Ltd | 半導体装置 |
Family Cites Families (22)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3375418A (en) * | 1964-09-15 | 1968-03-26 | Sprague Electric Co | S-m-s device with partial semiconducting layers |
JPS5139075B1 (de) * | 1966-09-22 | 1976-10-26 | ||
US3762966A (en) * | 1968-09-18 | 1973-10-02 | Gen Electric | Method of fabricating high emitter efficiency semiconductor device with low base resistance by selective diffusion of base impurities |
US3667008A (en) * | 1970-10-29 | 1972-05-30 | Rca Corp | Semiconductor device employing two-metal contact and polycrystalline isolation means |
US3742319A (en) * | 1971-03-08 | 1973-06-26 | Communications Transistor Corp | R f power transistor |
US4106051A (en) * | 1972-11-08 | 1978-08-08 | Ferranti Limited | Semiconductor devices |
JPS51127682A (en) * | 1975-04-30 | 1976-11-06 | Fujitsu Ltd | Manufacturing process of semiconductor device |
US4161742A (en) * | 1975-08-02 | 1979-07-17 | Ferranti Limited | Semiconductor devices with matched resistor portions |
US4329706A (en) * | 1979-03-01 | 1982-05-11 | International Business Machines Corporation | Doped polysilicon silicide semiconductor integrated circuit interconnections |
JPS55153369A (en) * | 1979-05-18 | 1980-11-29 | Nec Corp | Manufacturing method of semiconductor device |
JPS56115560A (en) * | 1980-02-18 | 1981-09-10 | Toshiba Corp | Manufacture of semiconductor device |
US4259680A (en) * | 1980-04-17 | 1981-03-31 | Bell Telephone Laboratories, Incorporated | High speed lateral bipolar transistor |
US4400865A (en) * | 1980-07-08 | 1983-08-30 | International Business Machines Corporation | Self-aligned metal process for integrated circuit metallization |
US4512075A (en) * | 1980-08-04 | 1985-04-23 | Fairchild Camera & Instrument Corporation | Method of making an integrated injection logic cell having self-aligned collector and base reduced resistance utilizing selective diffusion from polycrystalline regions |
US4339869A (en) * | 1980-09-15 | 1982-07-20 | General Electric Company | Method of making low resistance contacts in semiconductor devices by ion induced silicides |
IE52791B1 (en) * | 1980-11-05 | 1988-03-02 | Fujitsu Ltd | Semiconductor devices |
US4433470A (en) * | 1981-05-19 | 1984-02-28 | Tokyo Shibaura Denki Kabushiki Kaisha | Method for manufacturing semiconductor device utilizing selective etching and diffusion |
FR2508704B1 (fr) * | 1981-06-26 | 1985-06-07 | Thomson Csf | Procede de fabrication de transistors bipolaires integres de tres petites dimensions |
JPS58122777A (ja) * | 1982-01-14 | 1983-07-21 | Toshiba Corp | 半導体装置 |
JPS58225663A (ja) * | 1982-06-23 | 1983-12-27 | Toshiba Corp | 半導体装置の製造方法 |
DE3334774A1 (de) * | 1983-09-26 | 1985-04-11 | Siemens AG, 1000 Berlin und 8000 München | Integrierbarer npn-transistor |
JPS60164356A (ja) * | 1984-02-06 | 1985-08-27 | Hitachi Ltd | 半導体装置 |
-
1986
- 1986-03-05 EP EP86102856A patent/EP0193934B1/de not_active Expired - Lifetime
- 1986-03-05 DE DE86102856T patent/DE3688711T2/de not_active Expired - Fee Related
-
1991
- 1991-07-12 US US07/730,518 patent/US5144408A/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
EP0193934A3 (en) | 1988-01-07 |
DE3688711T2 (de) | 1993-12-16 |
EP0193934A2 (de) | 1986-09-10 |
US5144408A (en) | 1992-09-01 |
EP0193934B1 (de) | 1993-07-21 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8339 | Ceased/non-payment of the annual fee |