DE3769400D1 - Verkapselte halbleiteranordnung und verfahren zu deren herstellung. - Google Patents

Verkapselte halbleiteranordnung und verfahren zu deren herstellung.

Info

Publication number
DE3769400D1
DE3769400D1 DE8787401745T DE3769400T DE3769400D1 DE 3769400 D1 DE3769400 D1 DE 3769400D1 DE 8787401745 T DE8787401745 T DE 8787401745T DE 3769400 T DE3769400 T DE 3769400T DE 3769400 D1 DE3769400 D1 DE 3769400D1
Authority
DE
Germany
Prior art keywords
production
semiconductor arrangement
enclosed semiconductor
enclosed
arrangement
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE8787401745T
Other languages
English (en)
Inventor
Toshimi Kawahara
Michio Sono
Hiroaki Hayashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu VLSI Ltd
Fujitsu Ltd
Original Assignee
Fujitsu VLSI Ltd
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu VLSI Ltd, Fujitsu Ltd filed Critical Fujitsu VLSI Ltd
Application granted granted Critical
Publication of DE3769400D1 publication Critical patent/DE3769400D1/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565—Moulds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3135—Double encapsulation or coating and encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01057—Lanthanum [La]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
DE8787401745T 1986-07-25 1987-07-24 Verkapselte halbleiteranordnung und verfahren zu deren herstellung. Expired - Fee Related DE3769400D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61174854A JPS6331149A (ja) 1986-07-25 1986-07-25 半導体装置

Publications (1)

Publication Number Publication Date
DE3769400D1 true DE3769400D1 (de) 1991-05-23

Family

ID=15985812

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8787401745T Expired - Fee Related DE3769400D1 (de) 1986-07-25 1987-07-24 Verkapselte halbleiteranordnung und verfahren zu deren herstellung.

Country Status (5)

Country Link
US (1) US4788583A (de)
EP (1) EP0258098B1 (de)
JP (1) JPS6331149A (de)
KR (1) KR910002292B1 (de)
DE (1) DE3769400D1 (de)

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US4974057A (en) * 1986-10-31 1990-11-27 Texas Instruments Incorporated Semiconductor device package with circuit board and resin
JP2708191B2 (ja) 1988-09-20 1998-02-04 株式会社日立製作所 半導体装置
US5208467A (en) * 1988-07-28 1993-05-04 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device having a film-covered packaged component
JP2522524B2 (ja) * 1988-08-06 1996-08-07 株式会社東芝 半導体装置の製造方法
EP0361194A3 (de) * 1988-09-30 1991-06-12 Siemens Aktiengesellschaft Verfahren zum Umhüllen von elektrischen oder elektronischen Bauelementen oder Baugruppen und Umhüllung für elektrische oder elektronische Bauelemente oder Baugruppen
US5018003A (en) * 1988-10-20 1991-05-21 Mitsubishi Denki Kabushiki Kaisha Lead frame and semiconductor device
US4989063A (en) * 1988-12-09 1991-01-29 The United States Of America As Represented By The Secretary Of The Air Force Hybrid wafer scale microcircuit integration
US5008213A (en) * 1988-12-09 1991-04-16 The United States Of America As Represented By The Secretary Of The Air Force Hybrid wafer scale microcircuit integration
US5047834A (en) * 1989-06-20 1991-09-10 International Business Machines Corporation High strength low stress encapsulation of interconnected semiconductor devices
JPH0350758A (ja) * 1989-07-18 1991-03-05 Toshiba Corp 樹脂封止型半導体装置
US5349136A (en) * 1989-08-02 1994-09-20 Matsushita Electric Industrial Co., Ltd. Mold tool assembly
US5030796A (en) * 1989-08-11 1991-07-09 Rockwell International Corporation Reverse-engineering resistant encapsulant for microelectric device
JP2515406B2 (ja) * 1989-09-05 1996-07-10 株式会社東芝 樹脂封止型半導体装置
US5300459A (en) * 1989-12-28 1994-04-05 Sanken Electric Co., Ltd. Method for reducing thermal stress in an encapsulated integrated circuit package
JP2890662B2 (ja) * 1990-04-25 1999-05-17 ソニー株式会社 樹脂封止型半導体装置の製造方法とそれに用いるリードフレーム
FR2667441B1 (fr) * 1990-09-27 1997-03-28 Sgs Thomson Microelectronics Procede de moulage pour boitiers de circuit integre et moule.
US5214846A (en) * 1991-04-24 1993-06-01 Sony Corporation Packaging of semiconductor chips
US5221812A (en) * 1991-06-28 1993-06-22 Vlsi Technology, Inc. System for protecting leads to a semiconductor chip package during testing, burn-in and handling
KR930006868A (ko) * 1991-09-11 1993-04-22 문정환 반도체 패키지
US5197183A (en) * 1991-11-05 1993-03-30 Lsi Logic Corporation Modified lead frame for reducing wire wash in transfer molding of IC packages
US5331205A (en) * 1992-02-21 1994-07-19 Motorola, Inc. Molded plastic package with wire protection
US5358905A (en) * 1993-04-02 1994-10-25 Texas Instruments Incorporated Semiconductor device having die pad locking to substantially reduce package cracking
US5381599A (en) * 1993-04-12 1995-01-17 Delco Electronics Corp. Liquid crystal polymer encapsulated electronic devices and methods of making the same
US5430331A (en) * 1993-06-23 1995-07-04 Vlsi Technology, Inc. Plastic encapsulated integrated circuit package having an embedded thermal dissipator
US5585600A (en) * 1993-09-02 1996-12-17 International Business Machines Corporation Encapsulated semiconductor chip module and method of forming the same
US5641997A (en) * 1993-09-14 1997-06-24 Kabushiki Kaisha Toshiba Plastic-encapsulated semiconductor device
US5436203A (en) * 1994-07-05 1995-07-25 Motorola, Inc. Shielded liquid encapsulated semiconductor device and method for making the same
DE9413550U1 (de) * 1994-08-23 1996-01-11 Dylec Ltd Halbleiteranordnung mit wenigstens einem Halbleiterbauelement
GB2295722B (en) * 1994-11-30 1997-12-17 Motorola Ltd Method of packaging integrated circuits
JP2871591B2 (ja) * 1996-05-14 1999-03-17 日本電気株式会社 高周波用電子部品および高周波用電子部品の製造方法
JPH10116940A (ja) * 1996-10-09 1998-05-06 Toshiba Corp 樹脂封止型半導体装置及びその製造方法
WO1999015582A1 (de) * 1997-09-22 1999-04-01 Siemens Aktiengesellschaft Duroplast verbundwerkstoff mit ausdehnbare mikrohohlkugeln, sowie seine verwendung zur verkapselung
US6188897B1 (en) 1998-08-17 2001-02-13 At&T Wireless Svcs. Inc. Mobile station roaming in a multiple service provider area
US6576988B2 (en) * 1999-08-30 2003-06-10 Micron Technology, Inc. Semiconductor package
US6339253B1 (en) * 1999-08-30 2002-01-15 Micron Technology, Inc. Semiconductor package
US6700210B1 (en) * 1999-12-06 2004-03-02 Micron Technology, Inc. Electronic assemblies containing bow resistant semiconductor packages
US6384487B1 (en) 1999-12-06 2002-05-07 Micron Technology, Inc. Bow resistant plastic semiconductor package and method of fabrication
US6818968B1 (en) * 2000-10-12 2004-11-16 Altera Corporation Integrated circuit package and process for forming the same
JP4620303B2 (ja) * 2001-09-20 2011-01-26 株式会社東海理化電機製作所 半導体装置及びその製造方法
JP2003133484A (ja) * 2001-10-30 2003-05-09 Tokai Rika Co Ltd 半導体装置及びその製造方法
US7179688B2 (en) * 2003-10-16 2007-02-20 Kulicke And Soffa Industries, Inc. Method for reducing or eliminating semiconductor device wire sweep in a multi-tier bonding device and a device produced by the method
US6955949B2 (en) * 2003-10-16 2005-10-18 Kulicke & Soffa Investments, Inc. System and method for reducing or eliminating semiconductor device wire sweep
US6847122B1 (en) 2003-10-16 2005-01-25 Kulicke & Soffa Investments, Inc. System and method for preventing and alleviating short circuiting in a semiconductor device
WO2006019032A1 (ja) * 2004-08-17 2006-02-23 Matsushita Electric Industrial Co., Ltd. プラズマディスプレイパネルとその製造方法
US7435625B2 (en) * 2005-10-24 2008-10-14 Freescale Semiconductor, Inc. Semiconductor device with reduced package cross-talk and loss
DE102006012615A1 (de) * 2006-03-20 2007-10-11 Kromberg & Schubert Gmbh & Co. Kg Umhülltes Bauelement und Verfahren zu dessen Herstellung
DE102006047938A1 (de) * 2006-10-10 2008-04-17 Robert Bosch Gmbh Gespritztes Kunststoffbauteil mit Einlegeteil
US7821116B2 (en) * 2007-02-05 2010-10-26 Fairchild Semiconductor Corporation Semiconductor die package including leadframe with die attach pad with folded edge
DE102009026804A1 (de) * 2009-06-08 2010-12-09 Robert Bosch Gmbh Verfahren zur Herstellung elektronischer Bauteile
CN102104028B (zh) * 2010-11-05 2012-12-12 南通富士通微电子股份有限公司 半导体塑封体及分层扫描方法
US20120313272A1 (en) * 2011-06-10 2012-12-13 Aliphcom, Inc. Component protective overmolding
US20120313296A1 (en) * 2011-06-10 2012-12-13 Aliphcom Component protective overmolding
US9069380B2 (en) 2011-06-10 2015-06-30 Aliphcom Media device, application, and content management using sensory input
WO2016051449A1 (ja) * 2014-09-29 2016-04-07 新電元工業株式会社 半導体パッケージの製造方法および半導体パッケージ
JP6693441B2 (ja) * 2017-02-27 2020-05-13 オムロン株式会社 電子装置およびその製造方法

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JPS59181034A (ja) * 1983-03-31 1984-10-15 Toshiba Corp 樹脂封止型半導体装置
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Also Published As

Publication number Publication date
EP0258098A1 (de) 1988-03-02
EP0258098B1 (de) 1991-04-17
JPS6331149A (ja) 1988-02-09
US4788583A (en) 1988-11-29
KR910002292B1 (ko) 1991-04-11
KR890003009A (ko) 1989-04-12

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8339 Ceased/non-payment of the annual fee