DE3778331D1 - Halbleiterspeicheranordnung und verfahren zu ihrer herstellung. - Google Patents

Halbleiterspeicheranordnung und verfahren zu ihrer herstellung.

Info

Publication number
DE3778331D1
DE3778331D1 DE8787311422T DE3778331T DE3778331D1 DE 3778331 D1 DE3778331 D1 DE 3778331D1 DE 8787311422 T DE8787311422 T DE 8787311422T DE 3778331 T DE3778331 T DE 3778331T DE 3778331 D1 DE3778331 D1 DE 3778331D1
Authority
DE
Germany
Prior art keywords
production
semiconductor storage
storage arrangement
arrangement
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE8787311422T
Other languages
English (en)
Inventor
Masaki Patent Division Sato
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP61308610A external-priority patent/JPS63164370A/ja
Priority claimed from JP62136315A external-priority patent/JPH0642547B2/ja
Application filed by Toshiba Corp filed Critical Toshiba Corp
Application granted granted Critical
Publication of DE3778331D1 publication Critical patent/DE3778331D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H10B41/42—Simultaneous manufacture of periphery and memory cells
    • H10B41/43—Simultaneous manufacture of periphery and memory cells comprising only one type of peripheral transistor
    • H10B41/44—Simultaneous manufacture of periphery and memory cells comprising only one type of peripheral transistor with a control gate layer also being used as part of the peripheral transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H10B41/42—Simultaneous manufacture of periphery and memory cells
    • H10B41/43—Simultaneous manufacture of periphery and memory cells comprising only one type of peripheral transistor
    • H10B41/48—Simultaneous manufacture of periphery and memory cells comprising only one type of peripheral transistor with a tunnel dielectric layer also being used as part of the peripheral transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/68—Floating-gate IGFETs
    • H10D30/681—Floating-gate IGFETs having only two programming levels
    • H10D30/684—Floating-gate IGFETs having only two programming levels programmed by hot carrier injection
    • H10D30/685—Floating-gate IGFETs having only two programming levels programmed by hot carrier injection from the channel

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Non-Volatile Memory (AREA)
DE8787311422T 1986-12-26 1987-12-23 Halbleiterspeicheranordnung und verfahren zu ihrer herstellung. Expired - Lifetime DE3778331D1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP61308610A JPS63164370A (ja) 1986-12-26 1986-12-26 半導体記憶装置
JP62136315A JPH0642547B2 (ja) 1987-05-30 1987-05-30 不揮発性半導体メモリおよびその製造方法

Publications (1)

Publication Number Publication Date
DE3778331D1 true DE3778331D1 (de) 1992-05-21

Family

ID=26469941

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8787311422T Expired - Lifetime DE3778331D1 (de) 1986-12-26 1987-12-23 Halbleiterspeicheranordnung und verfahren zu ihrer herstellung.

Country Status (3)

Country Link
US (1) US4835740A (de)
EP (1) EP0273728B1 (de)
DE (1) DE3778331D1 (de)

Families Citing this family (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3059442B2 (ja) 1988-11-09 2000-07-04 株式会社日立製作所 半導体記憶装置
KR890001099A (ko) * 1987-06-08 1989-03-18 미다 가쓰시게 반도체 기억장치
US5445980A (en) 1988-05-10 1995-08-29 Hitachi, Ltd. Method of making a semiconductor memory device
US5153144A (en) * 1988-05-10 1992-10-06 Hitachi, Ltd. Method of making tunnel EEPROM
US5153684A (en) * 1988-10-19 1992-10-06 Kabushiki Kaisha Toshiba Nonvolatile semiconductor memory device with offset transistor
JP2509697B2 (ja) * 1989-04-28 1996-06-26 株式会社東芝 半導体装置およびその製造方法
US5172200A (en) * 1990-01-12 1992-12-15 Mitsubishi Denki Kabushiki Kaisha MOS memory device having a LDD structure and a visor-like insulating layer
US5032881A (en) * 1990-06-29 1991-07-16 National Semiconductor Corporation Asymmetric virtual ground EPROM cell and fabrication method
US5612914A (en) * 1991-06-25 1997-03-18 Texas Instruments Incorporated Asymmetrical non-volatile memory cell, arrays and methods for fabricating same
JP3111090B2 (ja) * 1990-08-29 2000-11-20 テキサス インスツルメンツ インコーポレイテツド 不揮発性メモリセルを作製する方法
US5202576A (en) * 1990-08-29 1993-04-13 Texas Instruments Incorporated Asymmetrical non-volatile memory cell, arrays and methods for fabricating same
JPH04206933A (ja) * 1990-11-30 1992-07-28 Nec Corp 半導体装置
US5424567A (en) * 1991-05-15 1995-06-13 North American Philips Corporation Protected programmable transistor with reduced parasitic capacitances and method of fabrication
US5264384A (en) * 1991-08-30 1993-11-23 Texas Instruments Incorporated Method of making a non-volatile memory cell
JP3236720B2 (ja) * 1993-02-10 2001-12-10 三菱電機株式会社 半導体記憶装置およびその製造方法
JPH0897163A (ja) * 1994-07-28 1996-04-12 Hitachi Ltd 半導体ウエハの製造方法、半導体ウエハ、半導体集積回路装置の製造方法および半導体集積回路装置
US5705415A (en) * 1994-10-04 1998-01-06 Motorola, Inc. Process for forming an electrically programmable read-only memory cell
JP2757814B2 (ja) * 1995-03-30 1998-05-25 日本電気株式会社 不揮発性半導体記憶装置およびその製造方法
JP3498116B2 (ja) * 1995-10-26 2004-02-16 株式会社ルネサステクノロジ 不揮発性半導体記憶装置
US5780893A (en) 1995-12-28 1998-07-14 Nippon Steel Corporation Non-volatile semiconductor memory device including memory transistor with a composite gate structure
US5897363A (en) * 1996-05-29 1999-04-27 Micron Technology, Inc. Shallow junction formation using multiple implant sources
US6051860A (en) * 1998-01-16 2000-04-18 Matsushita Electric Industrial Co., Ltd. Nonvolatile semiconductor memory device and method for fabricating the same and semiconductor integrated circuit
US6127706A (en) * 1998-04-23 2000-10-03 Texas Instruments - Acer Incorporated Trench-free buried contact for SRAM devices
US6238975B1 (en) 1998-11-25 2001-05-29 Advanced Micro Devices, Inc. Method for improving electrostatic discharge (ESD) robustness
US7235810B1 (en) 1998-12-03 2007-06-26 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method of fabricating the same
US7525165B2 (en) * 2000-04-17 2009-04-28 Semiconductor Energy Laboratory Co., Ltd. Light emitting device and manufacturing method thereof
JP5458526B2 (ja) * 2008-08-08 2014-04-02 富士通セミコンダクター株式会社 半導体装置及びその製造方法

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5232277A (en) * 1975-09-05 1977-03-11 Toshiba Corp Insulated gate type field-effect transistor
US4235011A (en) * 1979-03-28 1980-11-25 Honeywell Inc. Semiconductor apparatus
US4376947A (en) * 1979-09-04 1983-03-15 Texas Instruments Incorporated Electrically programmable floating gate semiconductor memory device
US4317273A (en) * 1979-11-13 1982-03-02 Texas Instruments Incorporated Method of making high coupling ratio DMOS electrically programmable ROM
DE3174858D1 (en) * 1980-12-25 1986-07-24 Fujitsu Ltd Nonvolatile semiconductor memory device
JPS59126674A (ja) * 1983-01-10 1984-07-21 Toshiba Corp 情報記憶用半導体装置
JPS61105862A (ja) * 1984-10-30 1986-05-23 Toshiba Corp 半導体装置
JPS61216364A (ja) * 1985-03-20 1986-09-26 Fujitsu Ltd 半導体装置
US4750024A (en) * 1986-02-18 1988-06-07 Texas Instruments Incorporated Offset floating gate EPROM memory cell

Also Published As

Publication number Publication date
EP0273728A3 (en) 1989-03-29
EP0273728A2 (de) 1988-07-06
EP0273728B1 (de) 1992-04-15
US4835740A (en) 1989-05-30

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee