DE3587798D1 - SoI-Halbleiteranordnung und Verfahren zu ihrer Herstellung. - Google Patents

SoI-Halbleiteranordnung und Verfahren zu ihrer Herstellung.

Info

Publication number
DE3587798D1
DE3587798D1 DE3587798T DE3587798T DE3587798D1 DE 3587798 D1 DE3587798 D1 DE 3587798D1 DE 3587798 T DE3587798 T DE 3587798T DE 3587798 T DE3587798 T DE 3587798T DE 3587798 D1 DE3587798 D1 DE 3587798D1
Authority
DE
Germany
Prior art keywords
production
semiconductor device
soi semiconductor
soi
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE3587798T
Other languages
English (en)
Other versions
DE3587798T2 (de
Inventor
Kaoru Nakagawa
Yoshio Yamamoto
Nobutaka Matsuoka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Publication of DE3587798D1 publication Critical patent/DE3587798D1/de
Application granted granted Critical
Publication of DE3587798T2 publication Critical patent/DE3587798T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

    • H—ELECTRICITY
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    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H01L21/2003—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate
    • H01L21/2007—Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer
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    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
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    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
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    • H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/24225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/24226—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the HDI interconnect connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the item being planar
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    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/012—Bonding, e.g. electrostatic for strain gauges
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/135—Removal of substrate
DE3587798T 1984-09-19 1985-09-18 SoI-Halbleiteranordnung und Verfahren zu ihrer Herstellung. Expired - Fee Related DE3587798T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59194600A JPS6173345A (ja) 1984-09-19 1984-09-19 半導体装置

Publications (2)

Publication Number Publication Date
DE3587798D1 true DE3587798D1 (de) 1994-05-19
DE3587798T2 DE3587798T2 (de) 1994-08-25

Family

ID=16327240

Family Applications (1)

Application Number Title Priority Date Filing Date
DE3587798T Expired - Fee Related DE3587798T2 (de) 1984-09-19 1985-09-18 SoI-Halbleiteranordnung und Verfahren zu ihrer Herstellung.

Country Status (4)

Country Link
US (1) US4888304A (de)
EP (1) EP0182032B1 (de)
JP (1) JPS6173345A (de)
DE (1) DE3587798T2 (de)

Families Citing this family (36)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5086011A (en) * 1987-01-27 1992-02-04 Advanced Micro Devices, Inc. Process for producing thin single crystal silicon islands on insulator
JPH067594B2 (ja) * 1987-11-20 1994-01-26 富士通株式会社 半導体基板の製造方法
JPH0237771A (ja) * 1988-07-28 1990-02-07 Fujitsu Ltd Ｓｏｉ基板
JPH0636414B2 (ja) * 1989-08-17 1994-05-11 信越半導体株式会社 半導体素子形成用基板の製造方法
DE69126153T2 (de) * 1990-02-28 1998-01-08 Shinetsu Handotai Kk Verfahren zur Herstellung von verbundenen Halbleiterplättchen
JPH0719737B2 (ja) * 1990-02-28 1995-03-06 信越半導体株式会社 Ｓ０１基板の製造方法
US5034343A (en) * 1990-03-08 1991-07-23 Harris Corporation Manufacturing ultra-thin wafer using a handle wafer
JP2721265B2 (ja) * 1990-07-05 1998-03-04 株式会社東芝 半導体基板の製造方法
JPH0488657A (ja) * 1990-07-31 1992-03-23 Toshiba Corp 半導体装置とその製造方法
JPH0719738B2 (ja) * 1990-09-06 1995-03-06 信越半導体株式会社 接合ウェーハ及びその製造方法
JPH04278562A (ja) * 1991-03-06 1992-10-05 Mitsubishi Electric Corp 半導体装置およびその製造方法
US5110748A (en) * 1991-03-28 1992-05-05 Honeywell Inc. Method for fabricating high mobility thin film transistors as integrated drivers for active matrix display
US5366924A (en) * 1992-03-16 1994-11-22 At&T Bell Laboratories Method of manufacturing an integrated circuit including planarizing a wafer
JP2821830B2 (ja) * 1992-05-14 1998-11-05 セイコーインスツルメンツ株式会社 半導体薄膜素子その応用装置および半導体薄膜素子の製造方法
JPH06142647A (ja) * 1992-11-11 1994-05-24 Yoshizawa L D Kk 浮遊物等の汚物回収装置
JPH06252073A (ja) * 1993-02-26 1994-09-09 Mitsubishi Electric Corp 半導体基板及びその製造方法
US5314841A (en) * 1993-04-30 1994-05-24 International Business Machines Corporation Method of forming a frontside contact to the silicon substrate of a SOI wafer
JP2542295Y2 (ja) * 1993-05-26 1997-07-23 上田サーボ機械株式会社 水面の浮遊油分除去装置
JPH1027893A (ja) * 1993-10-29 1998-01-27 Amer Fib Inc 電荷シンク又は電位ウェルとして設けられた絶縁層の下の基板内に電気的に結合され別に形成されたドープされた領域を有するｓｏｉウエーハ上に設けられた集積回路（ｉｃ）装置
JP2531491B2 (ja) * 1993-11-19 1996-09-04 憲造 稲葉 液面上層の浮揚汚物の吸収濾過装置
US5468674A (en) * 1994-06-08 1995-11-21 The United States Of America As Represented By The Secretary Of The Navy Method for forming low and high minority carrier lifetime layers in a single semiconductor structure
US5668045A (en) * 1994-11-30 1997-09-16 Sibond, L.L.C. Process for stripping outer edge of BESOI wafers
US6484585B1 (en) 1995-02-28 2002-11-26 Rosemount Inc. Pressure sensor for a pressure transmitter
US5985728A (en) * 1995-09-01 1999-11-16 Elantec Semiconductor, Inc. Silicon on insulator process with recovery of a device layer from an etch stop layer
JP3485707B2 (ja) * 1996-01-09 2004-01-13 沖電気工業株式会社 透過型電子顕微鏡用の平面サンプルの作製方法及びその透過型電子顕微鏡による欠陥測定方法
DE19704546A1 (de) * 1997-02-06 1998-08-13 Wacker Siltronic Halbleitermat Verfahren zur Herstellung einer einseitig beschichteten und mit einem Finish versehenen Halbleiterscheibe
EP1244900B1 (de) 2000-01-06 2005-01-05 Rosemount Inc. Kornwachstumsverfahren zur herstellung einer elektrischen verbindung für mikroelektromechanische systeme (mems)
US6520020B1 (en) 2000-01-06 2003-02-18 Rosemount Inc. Method and apparatus for a direct bonded isolated pressure sensor
US6505516B1 (en) 2000-01-06 2003-01-14 Rosemount Inc. Capacitive pressure sensing with moving dielectric
US6561038B2 (en) 2000-01-06 2003-05-13 Rosemount Inc. Sensor with fluid isolation barrier
US6508129B1 (en) 2000-01-06 2003-01-21 Rosemount Inc. Pressure sensor capsule with improved isolation
FR2837322B1 (fr) * 2002-03-14 2005-02-04 Commissariat Energie Atomique DIODE SCHOTTKY DE PUISSANCE A SUBSTRAT SiCOI, ET PROCEDE DE REALISATION D'UN TELLE DIODE
FR2914497B1 (fr) * 2007-04-02 2009-06-12 St Microelectronics Sa Structure de composants haute frequence a faibles capacites parasites
US8158964B2 (en) 2009-07-13 2012-04-17 Seagate Technology Llc Schottky diode switch and memory units containing the same
US8853054B2 (en) * 2012-03-06 2014-10-07 Sunedison Semiconductor Limited Method of manufacturing silicon-on-insulator wafers
US8902663B1 (en) 2013-03-11 2014-12-02 Monolithic 3D Inc. Method of maintaining a memory state

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL122607C (de) * 1961-07-26 1900-01-01
CA942893A (en) * 1963-12-04 1974-02-26 North American Aviation Electrically isolated semiconductor devices on common crystalline substrate and method of making same
US3351502A (en) * 1964-10-19 1967-11-07 Massachusetts Inst Technology Method of producing interface-alloy epitaxial heterojunctions
US3416224A (en) * 1966-03-08 1968-12-17 Ibm Integrated semiconductor devices and fabrication methods therefor
US3508980A (en) * 1967-07-26 1970-04-28 Motorola Inc Method of fabricating an integrated circuit structure with dielectric isolation
NL6813833A (de) * 1968-09-27 1970-04-01
US3836991A (en) * 1970-11-09 1974-09-17 Texas Instruments Inc Semiconductor device having epitaxial region of predetermined thickness
US3749987A (en) * 1971-08-09 1973-07-31 Ibm Semiconductor device embodying field effect transistors and schottky barrier diodes
US3944447A (en) * 1973-03-12 1976-03-16 Ibm Corporation Method for fabrication of integrated circuit structure with full dielectric isolation utilizing selective oxidation
US3900344A (en) * 1973-03-23 1975-08-19 Ibm Novel integratable schottky barrier structure and method for the fabrication thereof
US4045248A (en) * 1973-06-26 1977-08-30 U.S. Philips Corporation Making Schottky barrier devices
JPS5329551B2 (de) * 1974-08-19 1978-08-22
US3997381A (en) * 1975-01-10 1976-12-14 Intel Corporation Method of manufacture of an epitaxial semiconductor layer on an insulating substrate
JPS5247686A (en) * 1975-10-15 1977-04-15 Toshiba Corp Semiconductor device and process for production of same
US4127860A (en) * 1977-04-18 1978-11-28 Rca Corporation Integrated circuit mesa bipolar device on insulating substrate incorporating Schottky barrier contact
US4282538A (en) * 1977-11-11 1981-08-04 Rca Corporation Method of integrating semiconductor components
US4261003A (en) * 1979-03-09 1981-04-07 International Business Machines Corporation Integrated circuit structures with full dielectric isolation and a novel method for fabrication thereof
DE3583183D1 (de) * 1984-05-09 1991-07-18 Toshiba Kawasaki Kk Verfahren zur herstellung eines halbleitersubstrates.
US4649627A (en) * 1984-06-28 1987-03-17 International Business Machines Corporation Method of fabricating silicon-on-insulator transistors with a shared element

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US4888304A (en) 1989-12-19
JPS6173345A (ja) 1986-04-15
EP0182032A2 (de) 1986-05-28
EP0182032A3 (en) 1988-03-23
EP0182032B1 (de) 1994-04-13
DE3587798T2 (de) 1994-08-25

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