DE69232348T2 - Integrierte Halbleiterschaltungsanordnung und Verfahren zu ihrer Herstellung - Google Patents

Integrierte Halbleiterschaltungsanordnung und Verfahren zu ihrer Herstellung

Info

Publication number
DE69232348T2
DE69232348T2 DE69232348T DE69232348T DE69232348T2 DE 69232348 T2 DE69232348 T2 DE 69232348T2 DE 69232348 T DE69232348 T DE 69232348T DE 69232348 T DE69232348 T DE 69232348T DE 69232348 T2 DE69232348 T2 DE 69232348T2
Authority
DE
Germany
Prior art keywords
production
circuit arrangement
semiconductor circuit
integrated semiconductor
integrated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69232348T
Other languages
English (en)
Other versions
DE69232348D1 (de
Inventor
Shigeki Sawada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Application granted granted Critical
Publication of DE69232348D1 publication Critical patent/DE69232348D1/de
Publication of DE69232348T2 publication Critical patent/DE69232348T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0214—Particular design considerations for integrated circuits for internal polarisation, e.g. I2L
    • H01L27/0229—Particular design considerations for integrated circuits for internal polarisation, e.g. I2L of bipolar structures
    • H01L27/0233—Integrated injection logic structures [I2L]
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/01—Bipolar transistors-ion implantation

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Bipolar Transistors (AREA)
DE69232348T 1991-09-24 1992-09-08 Integrierte Halbleiterschaltungsanordnung und Verfahren zu ihrer Herstellung Expired - Fee Related DE69232348T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP24305891 1991-09-24

Publications (2)

Publication Number Publication Date
DE69232348D1 DE69232348D1 (de) 2002-02-21
DE69232348T2 true DE69232348T2 (de) 2002-08-14

Family

ID=17098179

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69232348T Expired - Fee Related DE69232348T2 (de) 1991-09-24 1992-09-08 Integrierte Halbleiterschaltungsanordnung und Verfahren zu ihrer Herstellung

Country Status (3)

Country Link
US (2) US5504368A (de)
EP (1) EP0534632B1 (de)
DE (1) DE69232348T2 (de)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0787256B1 (de) * 1995-03-29 2002-06-19 Robert Bosch Gmbh Verfahren zur herstellung einer lochscheibe
US6204717B1 (en) * 1995-05-22 2001-03-20 Hitachi, Ltd. Semiconductor circuit and semiconductor device for use in equipment such as a power converting apparatus
JPH10189755A (ja) * 1996-12-20 1998-07-21 Nec Corp 半導体装置及びその製造方法
US5773350A (en) * 1997-01-28 1998-06-30 National Semiconductor Corporation Method for forming a self-aligned bipolar junction transistor with silicide extrinsic base contacts and selective epitaxial grown intrinsic base
JP3653963B2 (ja) * 1997-12-25 2005-06-02 ソニー株式会社 半導体装置およびその製造方法
US6049119A (en) * 1998-05-01 2000-04-11 Motorola, Inc. Protection circuit for a semiconductor device
US6140694A (en) * 1998-12-30 2000-10-31 Philips Electronics North America Corporation Field isolated integrated injection logic gate
US6809024B1 (en) 2003-05-09 2004-10-26 International Business Machines Corporation Method to fabricate high-performance NPN transistors in a BiCMOS process
EP1646084A1 (de) * 2004-10-06 2006-04-12 Infineon Technologies AG Verfahren zur Herstellung einer integrierten Injektions-Logikschaltung
JP4784595B2 (ja) * 2007-12-21 2011-10-05 株式会社デンソー バイポーラ型の半導体装置の製造方法
US9184097B2 (en) * 2009-03-12 2015-11-10 System General Corporation Semiconductor devices and formation methods thereof
US8890247B2 (en) * 2012-10-15 2014-11-18 International Business Machines Corporation Extremely thin semiconductor-on-insulator with back gate contact
US9196606B2 (en) * 2013-01-09 2015-11-24 Nthdegree Technologies Worldwide Inc. Bonding transistor wafer to LED wafer to form active LED modules
US9572249B2 (en) * 2013-03-14 2017-02-14 Nthdegree Technologies Worldwide Inc. Printing complex electronic circuits
US8999804B2 (en) 2013-05-06 2015-04-07 International Business Machines Corporation Methods for fabricating a bipolar junction transistor with self-aligned terminals

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5942463B2 (ja) * 1972-09-22 1984-10-15 ソニー株式会社 半導体集積回路装置
JPS56150850A (en) * 1980-04-22 1981-11-21 Toshiba Corp Manufacture of semiconductor integrated circuit
JPS5821366A (ja) * 1981-07-30 1983-02-08 Toshiba Corp 半導体集積回路装置
DE3361832D1 (en) * 1982-04-19 1986-02-27 Matsushita Electric Ind Co Ltd Semiconductor ic and method of making the same
DE3688711T2 (de) * 1985-03-07 1993-12-16 Toshiba Kawasaki Kk Integrierte Halbleiterschaltungsanordnung und Verfahren zu ihrer Herstellung.
JPS62277745A (ja) * 1986-05-27 1987-12-02 Toshiba Corp 半導体集積回路
JPS6343357A (ja) * 1986-08-08 1988-02-24 Sanyo Electric Co Ltd 半導体集積回路
US5014107A (en) * 1987-07-29 1991-05-07 Fairchild Semiconductor Corporation Process for fabricating complementary contactless vertical bipolar transistors
JP2788269B2 (ja) * 1988-02-08 1998-08-20 株式会社東芝 半導体装置およびその製造方法
US5096842A (en) * 1988-05-16 1992-03-17 Kabushiki Kaisha Toshiba Method of fabricating bipolar transistor using self-aligned polysilicon technology
EP0395358B1 (de) * 1989-04-25 2001-03-14 Matsushita Electronics Corporation Verfahren zur Herstellung eines bipolaren Transistors
JPH0319278A (ja) * 1989-06-15 1991-01-28 Matsushita Electron Corp 半導体集積回路の製造方法
KR950011017B1 (ko) * 1991-07-01 1995-09-27 미쯔시다덴기산교 가부시기가이샤 반도체장치 및 그 제조방법

Also Published As

Publication number Publication date
EP0534632B1 (de) 2002-01-16
DE69232348D1 (de) 2002-02-21
EP0534632A2 (de) 1993-03-31
US5591656A (en) 1997-01-07
US5504368A (en) 1996-04-02
EP0534632A3 (en) 1995-11-02

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Legal Events

Date Code Title Description
8327 Change in the person/name/address of the patent owner

Owner name: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD., KADOMA,

8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee