CN1971882A - 双应力记忆技术方法和相关半导体器件 - Google Patents

双应力记忆技术方法和相关半导体器件 Download PDF

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CN1971882A
CN1971882A CNA2006101463928A CN200610146392A CN1971882A CN 1971882 A CN1971882 A CN 1971882A CN A2006101463928 A CNA2006101463928 A CN A2006101463928A CN 200610146392 A CN200610146392 A CN 200610146392A CN 1971882 A CN1971882 A CN 1971882A
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方隼飞
骆志炯
郑阳伟
尼沃·罗夫多
金田中
吴洪业
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GlobalFoundries Singapore Pte Ltd
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Abstract

公开了一种用于在包括nFET和pFET的半导体器件中提供双应力记忆技术的方法以及相关结构。本方法的一个实施例包括：在nFET上方形成张应力层且在pFET上方形成压应力层，进行退火以在半导体器件中记忆应力并去除应力层。压应力层可以包括使用高密度等离子体(HDP)淀积方法淀积的高应力氮化硅。退火步骤可以包括使用约400－1200℃的温度。高应力压缩氮化硅和/或退火温度确保在pFET中保持压应力记忆。

Description

双应力记忆技术方法和相关半导体器件
技术领域
本发明一般地涉及应力记忆技术，且更特别地涉及提供双应力记忆技术的方法和相关结构。
背景技术
已知将应力施加于场效应晶体管(FET)可以改进它们的性能。当在纵向方向(即，在电流方向)上施加应力时，张应力可以提高电子迁移率(或n沟道FET(nFET)驱动电流)，而已知压应力可以提高空穴迁移率(或p沟道FET(pFET)驱动电流)。
一种提供这种应力的方式被称为应力记忆技术(SMT：stressmemorization technique)，其包括在沟道区上方施加固有应变的材料(例如，氮化硅)并进行退火以使应力被记忆在例如栅极多晶硅或扩散区中。然后去除应变材料。然而，应力得以保留并改进电子或空穴的迁移率，这提高了整体的性能。典型地将该退火提供为掺杂剂激活退火的一部分。
SMT的一个问题是其只能应用于n型场效应晶体管(nFET)。具体而言，尽管可以在pFET上方形成压应变氮化硅层来带来压应力，但通过随后必经的掺杂剂激活退火去除了大部分的应力。即，大多数压应力没有被记忆在pFET中。
考虑到上述内容，需要在本技术中提供一种可以用于nFET和pFET的SMT。
发明内容
公开了一种用于在包括nFET和pFET的半导体器件中提供双应力记忆技术的方法以及相关结构。本方法的一个实施例包括：在nFET上方形成张应力层且在pFET上方形成压应力层，进行退火以在半导体器件中记忆应力，以及去除应力层。压应力层可以包括使用高密度等离子体(HDP)淀积方法淀积的高应力氮化硅。退火步骤可以包括使用约400-1200℃的温度。高应力压缩氮化硅和/或退火温度确保在pFET中保持压应力记忆。
本发明的第一方面提供了一种在包括nFET和pFET的半导体器件中提供双应力记忆技术的方法，该方法包括以下步骤：在半导体器件上方形成第一应力层；在第一应力层上方形成刻蚀停止层；去除在nFET和pFET中第一个的上方的第一应力层和刻蚀停止层；在半导体器件上方形成第二应力层，其中在pFET上方的应力层包括压应力氮化硅；进行退火以将应力记忆在半导体器件中；以及去除第一应力层和第二应力层以及刻蚀停止层。
本发明的第二方面提供了一种针对包括nFET和pFET的半导体器件提供双应力记忆技术的方法，所述方法包括以下步骤：在nFET上方形成张应力层且在pFET上方形成压应力层，其中压应力层包括在随后退火期间至少保持部分压应力的高应力膜；进行退火以在半导体器件中记忆应力；以及去除压应力层和张应力层。
本发明的第三方面提供了一种半导体器件，其包括：具有记忆在其一部分中的张应力的nFET；以及具有记忆在其一部分中的压应力的pFET。
设计了本发明的示例方面，来解决由本领域技术人员发现的这里所述的问题和没有讨论的其它问题。
附图说明
从以下结合描述本发明各个实施例的附图对本发明各个方面所做出的详细描述，可以更容易地理解本发明的这些和其它特征，其中：
图1示出用于根据本发明方法的一个实施例的初步结构。
图2至图7示出根据本发明一个实施例的方法。
应注意，本发明的附图并非是按比例绘出。附图旨在仅描述本发明的典型方面，且因此不应被视作是限制本发明的范围。在附图中，相同的标号表示附图之间相同的元件。
具体实施方式
从附图开始，图1示出用于向半导体器件100提供双应力记忆技术(SMT)的方法的一个实施例的初步结构。该初步结构包括衬底102，该衬底102具有形成在其上的n型场效应晶体管(nFET)104和p型场效应晶体管(pFET)106。如图所示，半导体器件100已经完成初始处理，诸如常规浅沟槽隔离(STI)110的形成、阱注入、栅极电介质112的形成、栅极导体114的形成以及用于扩散116的扩展/晕圈(halo)/源极/漏极的注入。
参考图2，在该方法的一个实施例中，第一步骤包括在nFET 104上方形成张应力层120和在pFET 106上方形成压应力层122。张应力层120和压应力层122都可以包括固有应变的氮化硅(Si3N4)。然而，在一个优选实施例中，压应力层122包括高密度等离子体(HDP)氮化硅(Si3N4)，即，使用高密度等离子体淀积工艺形成的氮化硅。在一个优选实施例中，压应力层形成步骤包括使用以下条件来执行氮化硅的HDP淀积：约50mTorr的压力、约200标准立方厘米(sccm)的氩气(Ar)、约100sccm的硅烷(SiH4)、约300sccm的氮气(N2)、约0-1500W的射频(RF)偏置功率以及约2000W-4500W的RF源功率。因而，压应力层122包括高应力氮化硅，因为所述高应力氮化硅允许压应力的保持(完全或部分)，使得在以下描述的后续退火步骤期间应力被记忆在pFET 106的一部分中，所以所述高应力氮化硅能够提供双SMT。
可以用许多方式来提供该形成步骤，这里将只描述它的两个说明性实施例。图3至图6示出了这两个说明性实施例。如图3所示，第一可选的初步步骤包括形成例如二氧化硅(SiO2)的刻蚀停止层118(在图3中只用虚线示出)。接着，如图3中所示，第一子步骤包括在半导体器件100上方形成第一应力层130。如以下将要描述的，第一应力层130可以是张应力层120(图2)或压应力层122(图2)。然而，如图3中所示，第一应力层130包括固有张应变的氮化硅。还如图3中所示，第二子步骤包括在第一应力层130上方形成刻蚀停止层132。刻蚀停止层132可以包括诸如二氧化硅(SiO2)的任何现在已知或以后要研制的刻蚀停止材料。接着，还如图3中所示，去除在nFET 104和pFET 106中第一个(图中所示的pFET 106)的上方的第一应力层130和刻蚀停止层132，以暴露FET中的一个。刻蚀138可以包括针对所使用的材料来使用构图掩膜136(图中以虚线示出)以及任何常规的干法刻蚀。图4示出包括被暴露的pFET 106的生成结构。
接着，如图5中所示，在半导体衬底100上方形成第二应力层140。如图所示，第二应力层140形成在pFET 106上方，且因此包括上述高密度、压应力的氮化硅。在一个可替选实施例中，下一步骤可以包括在以下描述的退火步骤之前去除在nFET 104上方的第二应力层140。去除步骤可以包括针对所使用的材料来使用构图掩膜146(图中以虚线示出)以及任何常规的干法刻蚀144。图6示出了生成的结构。在没有去除第二应力层140的情况下，应认识到可能出现由第一应力层130所带来的应力的一些退化，但这种退化是最小限度的。
在可替选实施例中，可以改变上述步骤。即，形成步骤可以包括：在半导体器件100上方形成压应力层122，在压应力层上方形成刻蚀停止层132，去除在nFET 104上方的压应力层122和刻蚀停止层132，以及在半导体器件100上方形成张应力层120。如上述实施例中那样，可以在以下描述的退火步骤之前将张应力层120可选地去除。在没有去除张应力层120的情况下，应认识到可能出现由压应力层122所带来的应力的一些退化，但这种退化是最小限度的。
图6还示出了根据本方法的一个实施例的第二步骤，其包括进行退火150以在半导体器件100中记忆应力。退火150优选地包括使用不小于约400℃且不大于约1200℃的温度。对退火温度进行优化，使得器件100将能够记忆来自应力层120、122的应力，而不丢失在pFET106的部分上的压应力，这将在其上引起中性应力或张应力。例如，一种常规的等离子体增强型化学汽相淀积(PECVD)的压缩氮化硅，其形成有约-1.8GPa/cm2的应力，在退火后下降到约0.04GPa/cm2的应力，即张应力。相比之下，在一个实施例中，根据本发明的HDP压应力氮化硅形成有约-3.0GPa/cm2的应力，这产生不小于-100MPa/cm2的应力，因而保持了压应力。在一个实施例中，压应力可以在约-1GPa/cm2的范围中。
图7示出包括去除应力层120、122和刻蚀停止层132的第三步骤。这个去除步骤148可以包括湿法或干法刻蚀、或它们的组合；例如，使用湿法或干法刻蚀来去除刻蚀停止层132，然后使用热磷酸的湿法剥离来去除氮化硅应力层。图7还示出了根据本发明的半导体器件200，其包括nFET 204，该nFET 204具有记忆到其一部分中——例如栅极导体214和/或扩散区216——的张应力260，以及pFET 206，该pFET 206具有记忆到其一部分中——例如栅极导体220和/或扩散区222——的压应力262。
为了说明和描述的目的，给出了本发明各个方面的以上描述。其并不旨在穷尽列举或将本发明限制为所公开的精确形式，且明显地，可以进行多种修改和变化。本发明旨在将对于本领域技术人员是显而易见的这些修改和变化包括在由所附权利要求限定的本发明的范围内。

Claims (20)

1.一种用于在包括nFET和pFET的半导体器件中提供双应力记忆技术的方法，所述方法包括以下步骤：
在所述半导体器件上方形成第一应力层；
在所述第一应力层上方形成刻蚀停止层；
去除在所述nFET和所述pFET中第一个的上方的所述第一应力层和所述刻蚀停止层；
在所述半导体器件上方形成第二应力层，其中在所述pFET上方的应力层包括压应力氮化硅；
进行退火以将应力记忆在所述半导体器件中；以及
去除所述第一应力层和所述第二应力层及所述刻蚀停止层。
2.如权利要求1的方法，其中所述压应力氮化硅包括高密度等离子体(HDP)氮化硅。
3.如权利要求1的方法，进一步包括在所述第一应力层的形成步骤之前，淀积附加的刻蚀停止层的步骤。
4.如权利要求1的方法，其中所述压应力氮化硅在所述退火步骤后具有不小于-100Mpa/cm2的应力。
5.如权利要求1的方法，其中所述退火步骤包括使用不低于约400℃且不高于约1200℃的温度。
6.如权利要求1的方法，进一步包括在所述退火步骤之前，去除在所述nFET和所述pFET中另一个的上方的所述第二应力层的步骤。
7.如权利要求1的方法，其中所述nFET和所述pFET中的所述第一个包括所述nFET，且所述第一应力层包括固有张应变的材料，所述第二应力层包括所述压应力氮化硅。
8.如权利要求1的方法，其中每个应力层包括氮化硅。
9.如权利要求1的方法，其中所述刻蚀停止层包括二氧化硅。
10.一种针对包括nFET和pFET的半导体器件提供双应力记忆技术的方法，所述方法包括以下步骤：
在所述nFET上方形成张应力层且在所述pFET上方形成压应力层，其中所述压应力层包括在随后退火期间至少保持部分压应力的高应力膜；
进行退火以在所述半导体器件中记忆应力；以及
去除所述压应力层和所述张应力层。
11.如权利要求10的方法，其中所述压应力层形成步骤包括使用以下条件来执行氮化硅的高密度等离子体(HDP)淀积：约50mTorr的压力、约200标准立方厘米(Sccm)的氩气(Ar)、约100sccm的硅烷(SiH4)、约300sccm的氮气(N2)、约0-1500W的射频(RF)偏置功率以及约2000W-4500W的RF源功率。
12.如权利要求10的方法，其中所述退火步骤包括使用不低于约400℃且不高于约1200℃的温度。
13.如权利要求10的方法，其中每个应力层包括氮化硅。
14.如权利要求10的方法，其中所述形成步骤包括：
在所述半导体器件上方形成所述张应力层；
在所述张应力层上方形成刻蚀停止层；
去除在所述pFET上方的所述张应力层和所述刻蚀停止层；以及
在所述半导体器件上方形成所述压应力层。
15.如权利要求14的方法，进一步包括在所述退火步骤之前，去除在所述nFET上方的所述压应力层的步骤。
16.如权利要求14的方法，其中所述刻蚀停止层包括二氧化硅。
17.如权利要求10的方法，其中所述形成步骤包括：
在所述半导体器件上方形成所述压应力层；
在所述压应力层上方形成刻蚀停止层；
去除在所述nFET上方的所述压应力层和所述刻蚀停止层；
在所述半导体器件上方形成所述张应力层。
18.如权利要求17的方法，进一步包括在所述退火步骤之前，去除在所述pFET上方的所述张应力层的步骤。
19.一种半导体器件，包括：
nFET，具有记忆到其一部分中的张应力；以及
pFET，具有记忆到其一部分中的压应力。
20.如权利要求19的半导体器件，其中所述pFET具有通过压缩的高密度等离子体(HDP)氮化硅层而被记忆的压应力。
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CN103094108A (zh) * 2011-10-29 2013-05-08 中芯国际集成电路制造(上海)有限公司 半导体器件的制作方法
CN103094108B (zh) * 2011-10-29 2015-12-02 中芯国际集成电路制造(上海)有限公司 半导体器件的制作方法
CN103183307B (zh) * 2011-12-28 2016-04-20 中国科学院微电子研究所 张应力LPCVD SiO2膜的制造方法
CN103183307A (zh) * 2011-12-28 2013-07-03 中国科学院微电子研究所 张应力 LPCVD SiO2膜的制造方法
CN102709178A (zh) * 2012-05-22 2012-10-03 上海华力微电子有限公司 一种形成双应力层氮化硅薄膜的方法
CN102709178B (zh) * 2012-05-22 2015-08-19 上海华力微电子有限公司 一种形成双应力层氮化硅薄膜的方法
CN103839800A (zh) * 2012-11-20 2014-06-04 中国科学院微电子研究所 氮化硅制造方法
CN103107239A (zh) * 2012-12-06 2013-05-15 杭州赛昂电力有限公司 异质结太阳能电池及其制作方法
CN103107239B (zh) * 2012-12-06 2016-08-31 杭州赛昂电力有限公司 异质结太阳能电池及其制作方法
CN103700631A (zh) * 2013-11-29 2014-04-02 上海华力微电子有限公司 无结mos fet器件的制备方法
CN104733391A (zh) * 2015-03-31 2015-06-24 上海华力微电子有限公司 半导体器件的制造方法

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