CN1428855A - 半导体器件 - Google Patents
半导体器件 Download PDFInfo
- Publication number
- CN1428855A CN1428855A CN02157548A CN02157548A CN1428855A CN 1428855 A CN1428855 A CN 1428855A CN 02157548 A CN02157548 A CN 02157548A CN 02157548 A CN02157548 A CN 02157548A CN 1428855 A CN1428855 A CN 1428855A
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- Prior art keywords
- wiring
- connecting hole
- dielectric film
- semiconductor device
- film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 74
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 30
- 229910052802 copper Inorganic materials 0.000 claims description 28
- 239000010949 copper Substances 0.000 claims description 28
- 239000004411 aluminium Substances 0.000 claims description 10
- 229910052782 aluminium Inorganic materials 0.000 claims description 10
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 9
- 239000000463 material Substances 0.000 claims description 9
- 229920000090 poly(aryl ether) Polymers 0.000 claims description 5
- 239000010410 layer Substances 0.000 description 75
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 66
- 229910052751 metal Inorganic materials 0.000 description 66
- 239000002184 metal Substances 0.000 description 66
- 229910052814 silicon oxide Inorganic materials 0.000 description 64
- 238000000034 method Methods 0.000 description 52
- 230000004888 barrier function Effects 0.000 description 43
- 230000005012 migration Effects 0.000 description 31
- 238000013508 migration Methods 0.000 description 31
- 238000005530 etching Methods 0.000 description 30
- 230000035882 stress Effects 0.000 description 30
- 229910052581 Si3N4 Inorganic materials 0.000 description 24
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 24
- 229920002120 photoresistant polymer Polymers 0.000 description 16
- 230000007797 corrosion Effects 0.000 description 13
- 238000005260 corrosion Methods 0.000 description 13
- 230000014509 gene expression Effects 0.000 description 11
- 238000004519 manufacturing process Methods 0.000 description 9
- 238000004088 simulation Methods 0.000 description 9
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 8
- 238000001020 plasma etching Methods 0.000 description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 230000015572 biosynthetic process Effects 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- 238000002955 isolation Methods 0.000 description 5
- 238000005498 polishing Methods 0.000 description 5
- 239000003870 refractory metal Substances 0.000 description 5
- 230000008901 benefit Effects 0.000 description 4
- 229910052715 tantalum Inorganic materials 0.000 description 4
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 4
- 230000002180 anti-stress Effects 0.000 description 3
- 239000011229 interlayer Substances 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 238000001259 photo etching Methods 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 230000002950 deficient Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 230000002401 inhibitory effect Effects 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 150000001398 aluminium Chemical class 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 238000004380 ashing Methods 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 150000001879 copper Chemical class 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- 238000011049 filling Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 230000008646 thermal stress Effects 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
- H01L21/76811—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving multiple stacked pre-patterned masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
- H01L21/76813—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving a partial via etch
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/7684—Smoothing; Planarisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5226—Via connections in a multilevel interconnection structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
- H01L23/5283—Cross-sectional geometry
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
- H01L2221/1005—Formation and after-treatment of dielectrics
- H01L2221/101—Forming openings in dielectrics
- H01L2221/1015—Forming openings in dielectrics for dual damascene structures
- H01L2221/1036—Dual damascene with different via-level and trench-level dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Abstract
Description
Claims (15)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2001390710A JP3790469B2 (ja) | 2001-12-21 | 2001-12-21 | 半導体装置 |
JP390710/2001 | 2001-12-21 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN1428855A true CN1428855A (zh) | 2003-07-09 |
CN1231970C CN1231970C (zh) | 2005-12-14 |
Family
ID=19188438
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CNB021575487A Expired - Fee Related CN1231970C (zh) | 2001-12-21 | 2002-12-20 | 半导体器件 |
Country Status (6)
Country | Link |
---|---|
US (2) | US7067919B2 (zh) |
EP (2) | EP1326276B1 (zh) |
JP (1) | JP3790469B2 (zh) |
KR (1) | KR100847649B1 (zh) |
CN (1) | CN1231970C (zh) |
TW (1) | TW569389B (zh) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102760693A (zh) * | 2011-04-29 | 2012-10-31 | 瑞萨电子株式会社 | 形成半导体器件的方法 |
Families Citing this family (43)
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JP4005873B2 (ja) | 2002-08-15 | 2007-11-14 | 株式会社東芝 | 半導体装置 |
JP3858849B2 (ja) * | 2003-04-16 | 2006-12-20 | ソニー株式会社 | 半導体装置およびその製造方法 |
JP2004363256A (ja) * | 2003-06-03 | 2004-12-24 | Nec Electronics Corp | 半導体装置及び半導体装置の製造方法 |
JP2005064226A (ja) | 2003-08-12 | 2005-03-10 | Renesas Technology Corp | 配線構造 |
US20050045993A1 (en) * | 2003-08-28 | 2005-03-03 | Sanyo Electric Co., Ltd. | Semiconductor device with concave patterns in dielectric film and manufacturing method thereof |
US7387960B2 (en) | 2003-09-16 | 2008-06-17 | Texas Instruments Incorporated | Dual depth trench termination method for improving Cu-based interconnect integrity |
JP2006024698A (ja) * | 2004-07-07 | 2006-01-26 | Toshiba Corp | 半導体装置及びその製造方法 |
US20060180934A1 (en) * | 2005-02-14 | 2006-08-17 | Taiwan Semiconductor Manufacturing Co., Ltd. | Wiring structures for semiconductor devices |
JP4590556B2 (ja) * | 2005-03-11 | 2010-12-01 | 国立大学法人 奈良先端科学技術大学院大学 | 半導体装置の製造方法 |
KR100640535B1 (ko) * | 2005-05-13 | 2006-10-30 | 동부일렉트로닉스 주식회사 | 더미 비아 컨택을 가지는 반도체 소자의 다층 구리 배선구조 및 그 형성 방법 |
US7224069B2 (en) * | 2005-07-25 | 2007-05-29 | Taiwan Semiconductor Manufacturing Company, Ltd. | Dummy structures extending from seal ring into active circuit area of integrated circuit chip |
WO2007064471A1 (en) * | 2005-11-30 | 2007-06-07 | Advanced Micro Devices, Inc. | A technique for increasing adhesion of metallization layers by providing dummy vias |
DE102005057076A1 (de) * | 2005-11-30 | 2007-05-31 | Advanced Micro Devices, Inc., Sunnyvale | Technik zum Verbessern der Haftung von Metallisierungsschichten durch Vorsehen von Platzhalterkontaktdurchführungen |
CN1983550A (zh) * | 2005-12-14 | 2007-06-20 | 中芯国际集成电路制造(上海)有限公司 | 提高可靠性和成品率的消除铜位错的方法 |
TW200735274A (en) * | 2005-12-29 | 2007-09-16 | Koninkl Philips Electronics Nv | Reliability improvement of metal-interconnect structure by capping spacers |
US7767570B2 (en) * | 2006-03-22 | 2010-08-03 | Taiwan Semiconductor Manufacturing Company, Ltd. | Dummy vias for damascene process |
JP2007305713A (ja) * | 2006-05-10 | 2007-11-22 | Matsushita Electric Ind Co Ltd | 半導体装置及び配線補助パターン生成方法 |
JP5050413B2 (ja) * | 2006-06-09 | 2012-10-17 | 富士通株式会社 | 設計支援プログラム、該プログラムを記録した記録媒体、設計支援方法、および設計支援装置 |
US7777340B2 (en) * | 2006-11-08 | 2010-08-17 | Rohm Co., Ltd. | Semiconductor device |
US8912657B2 (en) * | 2006-11-08 | 2014-12-16 | Rohm Co., Ltd. | Semiconductor device |
JP4731456B2 (ja) | 2006-12-19 | 2011-07-27 | 富士通セミコンダクター株式会社 | 半導体装置 |
JP4871168B2 (ja) | 2007-02-26 | 2012-02-08 | 富士通セミコンダクター株式会社 | 集積回路の配線経路探索方法、集積回路の自動配線装置およびプログラム |
US8030733B1 (en) | 2007-05-22 | 2011-10-04 | National Semiconductor Corporation | Copper-compatible fuse target |
US7964934B1 (en) | 2007-05-22 | 2011-06-21 | National Semiconductor Corporation | Fuse target and method of forming the fuse target in a copper process flow |
US20090079080A1 (en) * | 2007-09-24 | 2009-03-26 | Infineon Technologies Ag | Semiconductor Device with Multi-Layer Metallization |
KR20090054544A (ko) * | 2007-11-27 | 2009-06-01 | 주식회사 동부하이텍 | 금속 배선 공정 |
JP5251153B2 (ja) * | 2008-02-07 | 2013-07-31 | 富士通セミコンダクター株式会社 | 半導体装置 |
US7951704B2 (en) * | 2008-05-06 | 2011-05-31 | Spansion Llc | Memory device peripheral interconnects and method of manufacturing |
US8669597B2 (en) | 2008-05-06 | 2014-03-11 | Spansion Llc | Memory device interconnects and method of manufacturing |
JP5350681B2 (ja) * | 2008-06-03 | 2013-11-27 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
JP5353109B2 (ja) | 2008-08-15 | 2013-11-27 | 富士通セミコンダクター株式会社 | 半導体装置の製造方法 |
US7709956B2 (en) * | 2008-09-15 | 2010-05-04 | National Semiconductor Corporation | Copper-topped interconnect structure that has thin and thick copper traces and method of forming the copper-topped interconnect structure |
JP5434355B2 (ja) * | 2009-08-11 | 2014-03-05 | 富士通セミコンダクター株式会社 | 設計支援プログラム、設計支援装置、および設計支援方法 |
DE102009056562A1 (de) * | 2009-12-03 | 2011-06-09 | Telefunken Semiconductors Gmbh & Co. Kg | Integrierter Schaltungsteil |
US20110133286A1 (en) * | 2009-12-03 | 2011-06-09 | Franz Dietz | Integrierter schaltungsteil |
KR20120138875A (ko) * | 2011-06-16 | 2012-12-27 | 삼성전자주식회사 | 배선 구조물 및 이의 제조 방법 |
US8941242B2 (en) * | 2011-12-07 | 2015-01-27 | Freescale Semiconductor, Inc. | Method of protecting against via failure and structure therefor |
US9343411B2 (en) * | 2013-01-29 | 2016-05-17 | Intel Corporation | Techniques for enhancing fracture resistance of interconnects |
US9966338B1 (en) * | 2017-04-18 | 2018-05-08 | Globalfoundries Inc. | Pre-spacer self-aligned cut formation |
KR102307127B1 (ko) * | 2017-06-14 | 2021-10-05 | 삼성전자주식회사 | 반도체 소자 |
JP7085417B2 (ja) * | 2018-06-25 | 2022-06-16 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
JP7082019B2 (ja) * | 2018-09-18 | 2022-06-07 | 株式会社東芝 | 固体撮像装置 |
US20210265411A1 (en) * | 2020-02-21 | 2021-08-26 | Canon Kabushiki Kaisha | Semiconductor device and method for manufacturing semiconductor device |
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EP0457449A1 (en) * | 1990-04-27 | 1991-11-21 | Fujitsu Limited | Semiconductor device having via hole and method of producing the same |
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JPH10233442A (ja) | 1997-02-18 | 1998-09-02 | Sony Corp | 半導体装置及びその製造方法 |
JP3638778B2 (ja) * | 1997-03-31 | 2005-04-13 | 株式会社ルネサステクノロジ | 半導体集積回路装置およびその製造方法 |
JP2926568B1 (ja) | 1998-02-25 | 1999-07-28 | 九州日本電気株式会社 | 半導体集積回路とその配線方法 |
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- 2001-12-21 JP JP2001390710A patent/JP3790469B2/ja not_active Expired - Lifetime
-
2002
- 2002-11-26 TW TW091134354A patent/TW569389B/zh not_active IP Right Cessation
- 2002-12-04 US US10/309,113 patent/US7067919B2/en not_active Expired - Lifetime
- 2002-12-05 EP EP02026987.4A patent/EP1326276B1/en not_active Expired - Fee Related
- 2002-12-05 EP EP10177318.2A patent/EP2264758B1/en not_active Expired - Fee Related
- 2002-12-20 KR KR1020020081656A patent/KR100847649B1/ko active IP Right Grant
- 2002-12-20 CN CNB021575487A patent/CN1231970C/zh not_active Expired - Fee Related
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2005
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Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102760693A (zh) * | 2011-04-29 | 2012-10-31 | 瑞萨电子株式会社 | 形成半导体器件的方法 |
CN102760693B (zh) * | 2011-04-29 | 2015-05-20 | 瑞萨电子株式会社 | 形成半导体器件的方法 |
Also Published As
Publication number | Publication date |
---|---|
EP1326276A2 (en) | 2003-07-09 |
TW200301543A (en) | 2003-07-01 |
EP2264758A3 (en) | 2012-01-25 |
EP2264758B1 (en) | 2017-03-01 |
JP2003197623A (ja) | 2003-07-11 |
KR20030053047A (ko) | 2003-06-27 |
TW569389B (en) | 2004-01-01 |
EP1326276B1 (en) | 2014-10-15 |
JP3790469B2 (ja) | 2006-06-28 |
US20030116852A1 (en) | 2003-06-26 |
CN1231970C (zh) | 2005-12-14 |
KR100847649B1 (ko) | 2008-07-21 |
US20050121788A1 (en) | 2005-06-09 |
EP1326276A3 (en) | 2005-04-06 |
EP2264758A2 (en) | 2010-12-22 |
US7067919B2 (en) | 2006-06-27 |
US7173337B2 (en) | 2007-02-06 |
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