CN1280392A - 半导体存储元件的电容器及其制造方法 - Google Patents
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- 239000003990 capacitor Substances 0.000 title claims abstract description 60
- 238000003860 storage Methods 0.000 title claims description 7
- 239000004065 semiconductor Substances 0.000 claims abstract description 67
- PBCFLUZVCVVTBY-UHFFFAOYSA-N tantalum pentoxide Inorganic materials O=[Ta](=O)O[Ta](=O)=O PBCFLUZVCVVTBY-UHFFFAOYSA-N 0.000 claims abstract description 61
- 230000004888 barrier function Effects 0.000 claims abstract description 44
- 238000000034 method Methods 0.000 claims abstract description 41
- 238000004519 manufacturing process Methods 0.000 claims abstract description 32
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 29
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 29
- 239000000758 substrate Substances 0.000 claims abstract description 14
- 238000006243 chemical reaction Methods 0.000 claims description 30
- 238000010438 heat treatment Methods 0.000 claims description 30
- 239000007789 gas Substances 0.000 claims description 20
- 238000005121 nitriding Methods 0.000 claims description 20
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical group [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 19
- 238000011065 in-situ storage Methods 0.000 claims description 13
- 239000012528 membrane Substances 0.000 claims description 13
- 230000015572 biosynthetic process Effects 0.000 claims description 12
- 239000000126 substance Substances 0.000 claims description 10
- 229910052751 metal Inorganic materials 0.000 claims description 8
- 239000002184 metal Substances 0.000 claims description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 8
- 229920005591 polysilicon Polymers 0.000 claims description 8
- 238000009832 plasma treatment Methods 0.000 claims description 6
- QJGQUHMNIGDVPM-UHFFFAOYSA-N nitrogen group Chemical group [N] QJGQUHMNIGDVPM-UHFFFAOYSA-N 0.000 claims description 4
- HTXDPTMKBJXEOW-UHFFFAOYSA-N iridium(IV) oxide Inorganic materials O=[Ir]=O HTXDPTMKBJXEOW-UHFFFAOYSA-N 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims description 2
- WOCIAKWEIIZHES-UHFFFAOYSA-N ruthenium(iv) oxide Chemical compound O=[Ru]=O WOCIAKWEIIZHES-UHFFFAOYSA-N 0.000 claims 4
- 125000001967 indiganyl group Chemical group [H][In]([H])[*] 0.000 claims 2
- 230000001546 nitrifying effect Effects 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 29
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 16
- 238000007254 oxidation reaction Methods 0.000 description 9
- 238000000137 annealing Methods 0.000 description 7
- 239000011229 interlayer Substances 0.000 description 7
- 230000003647 oxidation Effects 0.000 description 7
- 229910052760 oxygen Inorganic materials 0.000 description 7
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 6
- 239000001301 oxygen Substances 0.000 description 6
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical group [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 5
- 229910052799 carbon Inorganic materials 0.000 description 5
- 239000002245 particle Substances 0.000 description 5
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 4
- 239000002243 precursor Substances 0.000 description 4
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 3
- 150000001722 carbon compounds Chemical class 0.000 description 3
- 239000012535 impurity Substances 0.000 description 3
- 239000012495 reaction gas Substances 0.000 description 3
- 238000004544 sputter deposition Methods 0.000 description 3
- 229910052715 tantalum Inorganic materials 0.000 description 3
- 239000006227 byproduct Substances 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 238000002425 crystallisation Methods 0.000 description 2
- 230000008025 crystallization Effects 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 239000007788 liquid Substances 0.000 description 2
- 230000009257 reactivity Effects 0.000 description 2
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 description 2
- 239000012808 vapor phase Substances 0.000 description 2
- NGCRLFIYVFOUMZ-UHFFFAOYSA-N 2,3-dichloroquinoxaline-6-carbonyl chloride Chemical compound N1=C(Cl)C(Cl)=NC2=CC(C(=O)Cl)=CC=C21 NGCRLFIYVFOUMZ-UHFFFAOYSA-N 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 229910003074 TiCl4 Inorganic materials 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 238000011066 ex-situ storage Methods 0.000 description 1
- 238000010574 gas phase reaction Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 239000005416 organic matter Substances 0.000 description 1
- 238000000197 pyrolysis Methods 0.000 description 1
- 230000001105 regulatory effect Effects 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N titanium dioxide Inorganic materials O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 1
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Abstract
本发明提供一种在电介质膜和上部电极之间具有台阶覆盖好的导电性阻挡层的半导体存储元件的电容器。本发明的特征在于,包括,在半导体衬底上形成下部电极的工序;对所述下部电极的表面进行氮化处理、以便阻止在该表面的自然氧化膜产生的工序;在所述下部电极上形成作为电介质膜的Ta2O5膜的工序;在所述Ta2O5膜上形成由氮化硅膜构成的导电性阻挡层的工序;以及在所述导电性阻挡层上形成上部电极的工序。
Description
本发明涉及半导体存储元件的电容器及其制造方法,特别是涉及在电介质膜和上部电极之间具有台阶覆盖良好的导电性阻挡层的半导体存储元件的电容器及其制造方法。
近来,随着构成DRAM半导体元件的存储单元数量的增加,各存储单元占有面积日益减少。另一方面,为了正确地读出存储数据,各存储单元内形成的电容器必须有足够的容量。因此,现在的DRAM半导体元件要求存储单元形成占据面积既小、容量又大的电容器。电容器的静电容量(capacitance)是通过采用高介电常数的绝缘体、或者扩大下部电极表面积来增大的。目前的高集成化的DRAM半导体元件中,采用介电常数比NO(氮化物-氧化物)膜更高的Ta2O5作为电介质,形成3维的下部电极。
图1是显示已有的半导体存储元件的电容器的剖面图。如图1所示,在预定部位形成场氧化膜11的半导体衬底10上,按公知方式形成下部带有栅绝缘膜12的栅电极13。在栅电极13两侧的半导体衬底10上形成结区14,形成MOS晶体管。在形成了MOS晶体管的半导体衬底10上形成第一层间绝缘膜16和第二层间绝缘膜18。在第一和第二层间绝缘膜16、18内形成存储结点接触孔h,以露出结区14。采用公知方式在存储结点接触孔h内形成圆筒状的下部电极20,与露出的结区14接触。为了进一步增大下部电极20的表面积,在下部电极20的表面形成HSG(半球形颗粒)膜21。可以采用PECVD(等离子体增强化学汽相淀积)或者LPCVD(低压化学汽相淀积)方式形成Ta2O5膜23。此时,采用PECVD方式形成的Ta2O5膜的膜质好,但是由于台阶覆盖(step coverage)特性差,所以已有的Ta2O5膜22是采用台阶覆盖特性好的LPCVD方式形成的。之后,通过预定的热处理工序使Ta2O5膜22结晶化。在Ta2O5膜22上形成用作导电性阻挡层(conduction barrier)的氮化钛膜(TiN:23)。采用LPCVD方式或者溅射方式形成氮化钛膜23。在氮化钛膜上形成掺杂多晶硅膜构成的上部电极24。
但是,以Ta2O5膜为电介质膜的已有电容器存在以下问题。
首先,由于一般的Ta2O5膜具有不稳定的化学计量比(stoichiometry),所以Ta和O的组成比例产生差异。因此,在薄膜内产生代位式Ta原子即空位原子(vacancy atom)。这种空位原子是氧空位(oxygen vacancy),所以成为产生漏电流的原因,可以通过构成Ta2O5膜的组成元素的含量和结合程度来调节空位原子的量,但是难以完全去除。现在,为了稳定Ta2O5膜的不稳定化学计量比,通过Ta2O5膜的氧化去除Ta2O5膜内的代位型Ta原子。但是,当为了防止漏电流而对Ta2O5膜进行氧化时,则出现以下问题。即,Ta2O5膜与多晶硅形成的下部电极的氧化反应性大。因此,为了氧化代位型Ta原子而进行氧化处理时,在Ta2O5膜与下部电极之间产生介电常数低的自然氧化膜,氧移动到Ta2O5膜和下部电极的界面,从而降低界面的均匀性。
而且,作为前驱物(precusor)使用的Ta(OC2H5)5的有机物和O2(或者N2O)气体发生反应,从而在Ta2O5膜内产生碳原子(C)、碳化合物(CH4、C2H4)和H2O等杂质。这些杂质增大了电容器的漏电流,并且降低了Ta2O5膜的介电常数,所以难以获得大容量的电容器。
另一方面,在上部电极24和Ta2O5膜22之间用作导电性阻挡层的TiN膜23也存在以下的问题。
首先,对采用LPCVD方式形成用作导电性阻挡层的TiN膜23时的问题进行说明。作为采用LPCVD方式形成的TiN膜的源气体一般地使用TiCl4气体和NH3气体。此时,由于TiCl4气体具有在600℃以上高温分解的特性,所以实际上在比600℃更高的温度形成TiN膜,以便易于调节TiN膜内部的Cl的浓度。但是,在形成TiN膜时实施高温工序时,Ta2O5膜22和构成下部电极20的原子间则发生相互扩散,由于反应性大的NH4气体而使反应室内的气体反应活泼,在膜内或者表面上产生过量的微粒。因此,电介质膜的均匀性降低。
另外,当在低温形成TiN膜时,由于难以调节TiN膜内的Cl量,TiN膜内便残留过量的Cl。这样,残留量过量Cl的TiN膜难以用作导电性阻挡层,所以电容器产生漏电流。
而且,采用溅射方式形成的TiN膜23,由于台阶覆盖特性极差,所以难以在Ta2O5膜22上均匀蒸镀200-400A的厚度。因此,HSG膜21的晶粒之间形成空隙,电容器的特性降低。
并且,TiN膜23和Ta2O5膜22在687K(414℃)的温度发生如下反应。
亦即,在687K的温度范围内,TiN膜23和Ta2O5膜24反应,在TiN膜23和Ta2O5膜22的界面产生不希望的TiO2电介质(图中无显示)。TiO2电介质增大了电介质膜的膜厚度,降低了电容量。但是,由于TiO2本身具有高漏电流特性,所以增大了电介质膜的漏电流。
因此,本发明的目的在于防止下部电极和Ta2O5膜之间产生自然氧化膜,从而改善电介质膜的均匀性。
而且,本发明的另一目的在于减少漏电流的发生,确保大的电容量。
本发明的又一目的在于形成台阶覆盖特性良好的导电性阻挡层。
为了实现所述目的,本发明为一种半导体存储元件的电容器,其特征在于,包括,下部电极;在所述下部电极表面上形成的用于抑制自然氧化膜的氮化硅膜;在所述氮化硅膜上形成的电介质膜;和在所述电介质膜上形成的上部电极,所述电介质膜是Ta2O5膜。
而且,本发明为一种半导体存储元件的电容器,其特征在于,包括,下部电极;在所述下部电极表面上形成的用于抑制自然氧化膜的氮化硅膜;在所述氮化硅膜上形成的电介质膜;在所述电介质膜表面形成的由氮化硅膜构成的导电性阻挡层;和在所述导电性阻挡层上形成的上部电极,所述电介质膜是Ta2O5膜。
而且,本发明的特征在于,包括,在半导体衬底上形成下部电极的工序;对所述下部电极表面进行氮化处理的工序;在进行了所述氮化处理的下部电极上蒸镀Ta2O5膜作为电介质膜的工序;和在所述电介质膜上形成上部电极的工序。
而且,本发明的特征在于,包括,在半导体衬底上形成下部电极的工序;在所述下部电极表面上进行阻止自然氧化膜发生的该表面氮化处理工序;在所述下部电极上形成Ta2O5膜作为电介质膜的工序;在所述Ta2O5膜上形成由氮化硅构成的导电性阻挡层的工序;和在所述导电性阻挡层上形成上部电极的工序。
再有,本发明的特征在于,包括,在半导体衬底上形成下部电极的工序;在保持200-700℃的温度和NH3或N2/H2等离子体气体的反应室内,对所述下部电极表面进行阻止该表面的自然氧化膜的产生的氮化处理的工序;在所述下部电极上形成Ta2O5膜作为电介质膜的工序;对所述Ta2O5膜热处理使其结晶化的工序;在保持200-400℃的温度和含氮等离子体气体的反应室内,在所述Ta2O5膜上形成由氮化硅膜构成的导电性阻挡层的工序;和在所述导电性阻挡层上形成上部电极的工序,所述下部电极的表面氮化处理工序、Ta2O5膜的形成工序、所述Ta2O5膜热处理结晶化的工序和形成导电性阻挡层的工序是在同一反应室就地(in-situ)进行的。
图1是显示已有的半导体存储元件的电容器的剖面图。
图2A-图2D是用于说明本发明第1实施例的半导体存储元件的电容器制造方法的剖面图。
图3是用于说明本发明第2实施例的半导体存储元件的电容器的剖面图。
图4A和图4B是说明本发明实施例3的半导体存储元件的电容器的剖面图。
以下,详细说明本发明的优选的实施例。
(实施例1)
参见图2A,在具有预定导电性的半导体衬底30的预定部位,按公知方式形成场氧化膜31。在半导体衬底30上的预定部位形成底部具有栅绝缘膜32的栅电极33,在栅电极33的两侧按公知方式形成隔离层34。在栅电极33两侧的半导体衬底30上形成结区35从而制成MOS晶体管。在形成了MOS晶体管的半导体衬底30上形成第1层间绝缘膜36和第2层间绝缘膜38。之后,对第2和第1层间绝缘膜38、36进行布图,以便露出结区35之中的任一个,形成存储结点接触孔H。形成圆筒状的下部电极40,以便与露出的结区35接触。为了增大下部电极40的表面积,采用公知方式在下部电极40的表面形成HSG膜41。
之后,为了防止在含有HSG膜41的下部电极40和以后形成的电介质膜(图中无显示)之间的界面上产生低介电自然氧化膜,对含有HSG膜41的下部电极40和第2层间绝缘膜38的表面进行氮化处理。在保持NH3气体或N2/H2气体等离子体状态的LPCVD(低压化学汽相淀积)反应室内进行表面氮化处理,应在200-700℃、优选300-500℃的温度进行。
参见图2B,在第1氮化硅膜42表面形成作为电介质膜的Ta2O5膜43。采用化学汽相淀积方式例如LPCVD方式形成本发明的Ta2O5膜43,采用Ta(O(C2H5)5(乙醇钽)这样的有机物作为前驱物。其中,Ta(OC2H5)5这样的有机物由于公知的为液态,转变为蒸汽状态后,供给到LPCVD反应室内。亦即,采用MFC(质流控制器)这样的流量调节器使液态的前驱物定量化后,通过包含小孔(orifice)或喷嘴(nozzle)的蒸发器或蒸发管进行蒸发,而形成Ta化学蒸汽。之后,应按80-100mg/min的流量向LPCVD反应室内供给Ta化学蒸汽。此时,蒸发器和成为Ta蒸汽的流动路径(flow path)的供给管的温度应保持在150-200℃,以便能够防止Ta化学蒸汽冷凝。采用这种方法供给到LPCVD反应室内的Ta化学蒸汽与反应气体的过剩的O2气体(过量气体)发生相互反应,在HSG膜41上形成厚约100-150A的非晶态的Ta2O5膜43。此时,为了使产生的颗粒最小化,边抑制Ta化学蒸汽和O2气体在反应室内的汽相反应(gas phase reaction),边使化学反应仅产生于晶片表面。这里,通过反应气体等的流量和反应室内的压力来调节汽相反应。而且,在本实施例中,为了能够抑制汽相反应,按10-500sccm程度的流量向LPCVD反应室内供给反应气体的O2气体,LPCVD反应室内的温度优选保持在300-500℃。此时,在LPCVD反应室内在不停止真空状态的同时就地进行Ta2O5膜的形成工序和下部电极表面的氮化处理工序。由此,不会产生附加的自然氧化和颗粒等。
之后,为了除去Ta2O5膜43内残留的代位型Ta原子(氧空位原子)和未结合碳成分,首先在300-500℃的温度和O3或UV-O3气氛下,对Ta2O5膜43进行低温退火。之后,为了边除去低温退火工序尚未除去而残留的碳化合物等,边使Ta2O5膜43结晶化,在700-950℃的温度和N2O、O2或N2气氛中进行5-30分钟的高温退火。此时,采用就地同时进行退火工序、下部电极表面的氮化处理工序和Ta2O5膜的形成工序。
之后,如图2C所示,在Ta2O5膜43上蒸镀作为导电性阻挡层的第2氮化硅膜44。通过采用等离子体的氮化处理、采用电炉的氮化处理或者RTN方式、按就地或者分批方式形成第2氮化硅膜44。首先,采用等离子体的氮化处理,是在含氮气体例如NH3、N2/O2或N2O气氛中,在200-400℃的温度下进行的。另一方面,采用电炉的氮化处理和RTN工序,分别在NH3、N2O2或N2O气氛中,在750-950℃的温度下进行的。这里,通过采用等离子体的氮化处理形成作为导电性阻挡层的第2氮化硅膜44的情况,下部电极表面氮化处理工序、Ta2O5膜的形成工序和Ta2O5膜的退火工序都是就地共同进行的。
然后,参见图2D,在第2氮化硅膜44上形成上部电极45。可以采用掺杂的多晶硅膜或TiN、TaN、W、WN、WSi、Ru、RuO2、Ir、IrO2或Pt这样的金属层制成上部电极45。采用掺杂的多晶硅膜作为上部电极45的情况,优选蒸镀约1000-1500A厚的掺杂多晶硅膜。另外,采用金属层作为上部电极45的情况,优选制成100-600A厚的金属层。总之,可以采用CVD方式制成多晶硅膜,可以采用LPCVD、PECVD、RF磁溅射法中的任一种制成金属层。
根据本实施例,在形成Ta2O5膜43之前就地进行氮化处理,在用于除去代位型Ta原子和杂质进行的氧化工序时,可以抑制下部电极40和Ta2O5膜43的氧化反应,减少氧的移动。由此,可以降低电介质膜的等效厚度,确保下部电极40和Ta2O5膜43之间界面的均匀性。
由于就地进行下部电极表面的氮化处理、Ta2O5膜的形成工序、Ta2O5膜的热处理工序和导电性阻挡层用的氮化硅膜的形成工序,所以能够防止附加的自然氧化和颗粒的产生。
而且,由于是通过在NH3、N2/O2或N2O气氛中的等离子体处理、电炉氮化处理或者RTN工序制成作为导电性阻挡层的氮化硅膜44,所以能够在Ta2O5膜上均匀地蒸镀10-20A的厚度。因此,改善了导电性阻挡层的台阶覆盖特性。
而且,由于无需用于形成TiN膜的TiCl4源气体,所以能够防止反应室内和Ta2O5膜43内受Cl离子的污染,防止漏电流。总之,在特定温度下氮化硅膜构成的导电性阻挡层和Ta2O5膜之间不会产生反应,所以不会产生因反应副产物引起漏电流和有效厚度的增加。
而且,由于采用介电常数非常高的Ta2O5膜作为电介质膜,所以可以得到具有高电容量的电容器。
(实施例2)
除了下部电极的结构之外,其余与实施例1相同。
如图3所示,按层叠结构形成本实施例的下部电极400。即使层叠结构的下部电极400的表面积比圆柱形的下部电极的表面积小,由于采用介电常数优异的Ta2O5膜作为电介质膜,所以可以得到所期容量的电容器。此时,在层叠结构的下部电极400的表面可以形成HSG膜41。
(实施例3)
除了Ta2O5膜的制造方法之外,其余与实施例1或2相同。而且,直至形成第1氮化硅膜42的全工序,都与实施例1或实施例2相同,所以本实施例仅说明Ta2O5膜制造方法。
参见图4A,在约400-450℃的温度下,在第1氧化硅膜42上形成厚53-57A的第1Ta2O5膜43-1。之外,为了除去第1 Ta2O5膜43-1膜内存在的代位型Ta分子和碳成分,在N2O或O2等离子体状态就地进行退火。或者采用UV-O3可非就地除去第1 Ta2O5膜43-1膜内存在的代位型Ta分子和碳成分。之后,按与第1 Ta2O5膜43-1的形成条件相同的方法,在已退火的第1Ta2O5膜43-1表面形成第2Ta2O5膜43-2膜。
然后,如图4B所示,如除去第1Ta2O5膜43-1膜内存在的代位型Ta分子和碳成分那样,对第2Ta2O5膜43-2膜进一步进行等离子体退火。由于等离子体退火工序,第1Ta2O5膜43-1膜和第2Ta2O5膜43-2膜为单层。
正如以上详细说明,本发明具有如下效果。
首先,通过在形成Ta2O5膜43之前就地进行氮化处理,在进行用于除去代位型Ta原子和杂质的氧化工序时,可以抑制下部电极40和Ta2O5膜43的氧化反应,减少氧的移动。由此,可以降低电介质膜的等效厚度,确保下部电极40和Ta2O5膜43之间界面的均匀性。
而且,由于就地进行下部电极的表面氮化处理、Ta2O5膜的形成工序、Ta2O5膜的热处理工序和导电性阻挡层用的氮化硅膜的形成工序,所以能够防止附加的自然氧化和颗粒的产生。
而且,作为导电性阻挡层的氮化硅膜,是利用NH3、N2/O2或N2O气氛中的等离子体处理或者RTN工序形成的,所以与可能发生的台阶高差无关都能够在Ta2O5膜上均匀地蒸镀10-20A的厚度。因此,改善了导电性阻挡层的台阶覆盖特性。
而且,由于无需用于形成TiN膜的TiCl4源气体,所以能够防止反应室内和Ta2O5膜43内的Cl离子的污染,防止漏电流。总之,在特定温度下氮化硅膜构成的导电性阻挡层和Ta2O5膜之间不发生反应,所以不发生因反应副产物引起漏电流和有效厚度的增加。
而且,由于在形成导电性阻挡层的同时Ta2O5膜结晶化,所以能够减少制造工序。
而且,由于采用介电常数非常高的Ta2O5膜作为电介质膜,所以可以得到具有大电容量的电容器。
Claims (39)
1.一种半导体存储元件的电容器,包括:
下部电极;
在所述下部电极表面上形成的抑制自然氧化膜用的氮化硅膜;
在所述氮化硅膜上形成的电介质膜;和
在所述电介质膜上形成的上部电极,
其特征在于,所述电介质膜是Ta2O5膜。
2.根据权利要求1的半导体存储元件的电容器,其特征在于,在所述电介质膜和所述上部电极之间还含有氮化硅膜构成的导电性阻挡层。
3.根据权利要求2的半导体存储元件的电容器,其特征在于,所述导电性阻挡层的厚度是10-20A。
4.根据权利要求1的半导体存储元件的电容器,其特征在于,所述下部电极是在表面形成有HSG膜的圆柱形或层叠结构。
5.根据权利要求1的半导体存储元件的电容器,其特征在于,所述Ta2O5膜具有100-150A的厚度。
6.根据权利要求1的半导体存储元件的电容器,其特征在于,所述上部电极由掺杂的多晶硅膜形成。
7.根据权利要求1的半导体存储元件的电容器,其特征在于,所述上部电极由金属层形成。
8.根据权利要求6的半导体存储元件的电容器,其特征在于,所述金属层是TiN、TaN、W、WN、WSi、Ru、RuO2、Ir、IrO2、Pt中的任意一种。
9.一种半导体存储元件的电容器,包括:
下部电极;
在所述下部电极表面上形成的抑制自然氧化膜用的氮化硅膜;
在所述氮化硅膜上形成的电介质膜;
在所述电介质膜表面上形成的氮化硅膜构成的导电性阻挡层;和
在所述导电性阻挡层上形成的上部电极,
其特征在于,所述电介质膜是Ta2O5膜。
10.根据权利要求9的半导体存储元件的电容器,其特征在于,所述导电性阻挡层的厚度是10-20A。
11.根据权利要求9的半导体存储元件的电容器,其特征在于,所述下部电极是在表面形成有HSG膜的圆柱形或层叠结构。
12.根据权利要求9的半导体存储元件的电容器,其特征在于,所述Ta2O5膜具有100-150A的厚度。
13.根据权利要求9的半导体存储元件的电容器,其特征在于,所述上部电极由掺杂的多晶硅膜形成。
14.根据权利要求9的半导体存储元件的电容器,其特征在于,所述上部电极由金属层形成。
15.根据权利要求14的半导体存储元件的电容器,其特征在于,所述金属层是TiN、TaN、W、WN、WSi、Ru、RuO2、Ir、IrO2、Pt中的任意一种。
16.一种半导体存储元件的电容器的制造方法,其特征在于,包括:
在半导体衬底上形成下部电极的工序;
对所述下部电极的表面进行氮化处理的工序;
在所述表面已做氮化处理的下部电极上蒸镀作为电介质膜的Ta2O5膜的工序;和
在所述电介质膜上形成上部电极的工序。
17.根据权利要求16的半导体存储元件的电容器的制造方法,其特征在于,Ta化学蒸汽和O2气体在CVD反应室内进行表面化学反应,形成所述Ta2O5膜。
18.根据权利要求16的半导体存储元件的电容器的制造方法,其特征在于,在所述Ta2O5膜的形成工序和上部电极的形成工序之间,在200-400℃的温度和O3及UV-O3气氛中,对所述Ta2O5膜进行低温热处理的工序,和在750-950℃的温度中进行高温热处理的工序。
19.根据权利要求16的半导体存储元件的电容器的制造方法,其特征在于,Ta2O5膜的形成工序包括:
第1Ta2O5膜的形成工序;
对所述第1Ta2O5膜进行第1热处理的工序;
在所述热处理后的第1Ta2O5膜上形成第2Ta2O5膜的工序;和
对所述第2Ta2O5膜进行第2热处理的工序。
20.根据权利要求19的半导体存储元件的电容器的制造方法,其特征在于,所述第1热处理工序或者第2热处理工序为N2O或O2等离子体处理或者UV-O3处理。
21.根据权利要求16的半导体存储元件的电容器的制造方法,其特征在于,在保持200-700℃的温度和NH3或N2/H2等离子体的反应室内,就地进行所述下部电极的表面氮化处理。
22.根据权利要求16的半导体存储元件的电容器的制造方法,其特征在于,在所述Ta2O5膜的形成工序和所述上部电极的形成工序之间,还含有在上部形成由氮化硅膜构成的导电性阻挡层的工序。
23.根据权利要求22的半导体存储元件的电容器的制造方法,其特征在于,在200-400℃的温度和含氮的等离子体气氛中形成所述导电性阻挡层。
24.根据权利要求22的半导体存储元件的电容器的制造方法,其特征在于,在具有750-950℃的温度和含氮气氛的电炉内形成所述导电性阻挡层。
25.根据权利要求22的半导体存储元件的电容器的制造方法,其特征在于,在750-950℃的温度和含氮气氛中通过RTN形成所述导电性阻挡层。
26.一种半导体存储元件的电容器的制造方法,其特征在于,包括:
在半导体衬底上形成下部电极的工序;
对所述下部电极的表面进行氮化处理,以便阻止其表面产生自然氧化膜的工序;
在所述下部电极上形成作为电介质膜的Ta2O5膜的工序;
在Ta2O5膜上形成由氮化硅膜构成的导电性阻挡层的工序;和
在所述导电性阻挡层上形成上部电极的工序。
27.根据权利要求26的半导体存储元件的电容器的制造方法,其特征在于,Ta化学蒸汽和O2气体在CVD反应室内进行表面化学反应,形成所述Ta2O5膜。
28.根据权利要求26的半导体存储元件的电容器的制造方法,其特征在于,在所述Ta2O5膜的形成工序和上部电极的形成工序之间,在200-400℃的温度和O3及UV-O3气氛中,对所述Ta2O5膜进行低温热处理的工序,和在750-950℃的温度中进行高温热处理的工序。
29.根据权利要求26的半导体存储元件的电容器的制造方法,其特征在于,Ta2O5膜的形成工序包括:
第1Ta2O5膜的形成工序;
对所述第1Ta2O5膜进行第1热处理的工序;
在所述热处理后的第1Ta2O5膜上形成第2Ta2O5膜的工序;和
对所述第2Ta2O5膜进行第2热处理的工序。
30.根据权利要求29的半导体存储元件的电容器的制造方法,其特征在于,所述第1热处理工序或者第2热处理工序为N2O或O2等离子体处理或者UV-O3处理。
31.根据权利要求26的半导体存储元件的电容器的制造方法,其特征在于,在保持200-700℃的温度和NH3或N2/H2等离子体的反应室内,就地进行所述下部电极的表面氮化处理。
32.根据权利要求26的半导体存储元件的电容器的制造方法,其特征在于,采用含氮气体,通过200-400℃的温度的等离子体处理,形成所述导电性阻挡层。
33.根据权利要求26的半导体存储元件的电容器的制造方法,其特征在于,在含氮气氛的电炉内在750-950℃的温度形成所述导电性阻挡层。
34.根据权利要求26的半导体存储元件的电容器的制造方法,其特征在于,在含氛成份的气氛、在750-950℃的温度按RTN形成所述导电性阻挡层。
35.一种半导体存储元件的制造方法,包括:
在半导体衬底上形成下部电极的工序;
在保持200-700℃的温度和NH3或N2/H2等离子体的反应室内,对所述下部电极的表面进行氮化处理,以便阻止产生自然氧化膜的工序;
在所述下部电极上形成作为电介质膜的Ta2O5膜的工序;
对所述Ta2O5膜进行热处理而结晶化的工序;
在保持200-400℃的温度和含氮等离子体的反应室内,在所述Ta2O5膜上形成由氮化硅膜构成的导电性阻挡层的工序;和
在所述导电性阻挡层上形成上部电极的工序,
其特征在于,在同一的反应室内就地进行所述下部电极的表面氮化处理工序、Ta2O5膜的形成工序、所述Ta2O5膜的热处理从而结晶化的工序和形成导电性阻挡层的工序。
36.根据权利要求35的半导体存储元件的制造方法,其特征在于,Ta化学蒸汽和O2气体在CVD反应室内进行表面化学反应,从而形成所述Ta2O5膜。
37.根据权利要求36的半导体存储元件的电容器的制造方法,其特征在于,所述Ta2O5膜的热处理工序为在200-400℃的温度和O3及UV-O3气氛中进行低温热处理的工序和在750-950℃的温度进行高温热处理的工序。
38.根据权利要求35的半导体存储元件的电容器的制造方法,其特征在于,Ta2O5膜的形成工序包括:
第1Ta2O5膜的形成工序;
对所述第1Ta2O5膜进行第1热处理的工序;
在所述热处理后的第1Ta2O5膜上形成第2Ta2O5膜的工序;和
对所述第2Ta2O5膜进行第2热处理的工序。
39.根据权利要求38的半导体存储元件的电容器的制造方法,其特征在于,所述第1热处理工序或者第2热处理工序为N2O或O2等离子体处理或者UV-O3处理。
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KR49503/1999 | 1999-11-09 | ||
KR49503/99 | 1999-11-09 | ||
KR10-1999-0049503A KR100373159B1 (ko) | 1999-11-09 | 1999-11-09 | 반도체 소자의 캐패시터 제조방법 |
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JP (1) | JP2001053253A (zh) |
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- 2000-06-30 TW TW089113014A patent/TW449912B/zh not_active IP Right Cessation
- 2000-06-30 JP JP2000199264A patent/JP2001053253A/ja active Pending
- 2000-07-02 CN CNB001240285A patent/CN100383971C/zh not_active Expired - Fee Related
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Publication number | Priority date | Publication date | Assignee | Title |
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CN100452320C (zh) * | 2004-06-30 | 2009-01-14 | 海力士半导体有限公司 | 形成半导体器件的电容器的方法 |
CN112018090A (zh) * | 2020-07-21 | 2020-12-01 | 中国科学院微电子研究所 | 一种电容结构及其制备方法和半导体器件 |
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CN100383971C (zh) | 2008-04-23 |
JP2001053253A (ja) | 2001-02-23 |
DE10032213B4 (de) | 2008-10-09 |
US20020100959A1 (en) | 2002-08-01 |
DE10032213A1 (de) | 2001-05-31 |
DE10032213B8 (de) | 2009-02-12 |
TW449912B (en) | 2001-08-11 |
GB2358284A (en) | 2001-07-18 |
US6376299B1 (en) | 2002-04-23 |
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GB0015991D0 (en) | 2000-08-23 |
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